diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -2151,7 +2151,8 @@
         assert((LaneBits == 64 || Val >= -(1ll << (LaneBits - 1))) &&
                "Unexpected out of bounds negative value");
         if (Const && LaneBits != 64 && Val > (1ll << (LaneBits - 1)) - 1) {
-          auto NewVal = ((uint64_t)Val % (1ll << LaneBits)) - (1ll << LaneBits);
+          uint64_t Mask = (1ll << LaneBits) - 1;
+          auto NewVal = (((uint64_t)Val & Mask) - (1ll << LaneBits)) & Mask;
           ConstLanes.push_back(DAG.getConstant(NewVal, SDLoc(Lane), LaneT));
         } else {
           ConstLanes.push_back(Lane);
diff --git a/llvm/test/CodeGen/WebAssembly/simd-pr61780.ll b/llvm/test/CodeGen/WebAssembly/simd-pr61780.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-pr61780.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=wasm32 -mattr=+simd128 -opaque-pointers 
+
+define void @f(ptr %0, ptr %pr) {
+BB:
+  %v0 = load <4 x i32>, ptr %0
+  %v1 = icmp ugt <4 x i32> %v0, <i32 0, i32 1, i32 2, i32 3>
+  %v2 = zext <4 x i1> %v1 to <4 x i8>
+  %v3 = ashr <4 x i8> <i8 16, i8 16, i8 16, i8 16>, %v2
+  %v4 = mul <4 x i8> %v3, %v3
+  store <4 x i8> %v4, ptr %pr
+  ret void
+}
+