diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -196,7 +196,7 @@
 
     // Support splatting
     for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
-		   MVT::v2f64})
+                   MVT::v2f64})
       setOperationAction(ISD::SPLAT_VECTOR, T, Legal);
 
     // Custom lowering since wasm shifts must have a scalar shift amount
@@ -2240,7 +2240,7 @@
                                                     SelectionDAG &DAG) const {
   // Allow constant lane indices, expand variable lane indices
   SDNode *IdxNode = Op.getOperand(Op.getNumOperands() - 1).getNode();
-  if (isa<ConstantSDNode>(IdxNode) || IdxNode->isUndef()) {
+  if (isa<ConstantSDNode>(IdxNode)) {
     // Ensure the index type is i32 to match the tablegen patterns
     uint64_t Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
     SmallVector<SDValue, 3> Ops(Op.getNode()->ops());
diff --git a/llvm/test/CodeGen/WebAssembly/pr61828.ll b/llvm/test/CodeGen/WebAssembly/pr61828.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/pr61828.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mattr=+simd128 -mtriple=wasm64
+
+define void @foo(i64 %i0, i64 %i1, ptr %p) {
+  %B4 = urem i64 %i0, %i0
+  %B5 = udiv i64 %i1, %B4
+  %I = insertelement <4 x float> <float 0.25, float 0.25, float 0.25, float 0.25>, float 0.5, i64 %B5
+  store <4 x float> %I, ptr %p
+  ret void
+}