diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -73,6 +73,11 @@
 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
 }
 
+// v8.9a/v9.4a FEAT_ATS1A
+def : AT<"S1E1A", 0b000, 0b0111, 0b1001, 0b010>;
+def : AT<"S1E2A", 0b100, 0b0111, 0b1001, 0b010>;
+def : AT<"S1E3A", 0b110, 0b0111, 0b1001, 0b010>;
+
 //===----------------------------------------------------------------------===//
 // DMB/DSB (data barrier) instruction options.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AArch64/armv8.9a-ats1a.s b/llvm/test/MC/AArch64/armv8.9a-ats1a.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-ats1a.s
@@ -0,0 +1,10 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s
+
+at s1e1a, x1
+// CHECK: at s1e1a, x1                        // encoding: [0x41,0x79,0x08,0xd5]
+
+at s1e2a, x1
+// CHECK: at s1e2a, x1                        // encoding: [0x41,0x79,0x0c,0xd5]
+
+at s1e3a, x1
+// CHECK: at s1e3a, x1                        // encoding: [0x41,0x79,0x0e,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s
+
+[0x41,0x79,0x08,0xd5]
+# CHECK: at s1e1a, x1
+
+[0x41,0x79,0x0c,0xd5]
+# CHECK: at s1e2a, x1
+
+[0x41,0x79,0x0e,0xd5]
+# CHECK: at s1e3a, x1