diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -58,6 +58,7 @@ // CHECK-NOT: __riscv_zvks {{.*$}} // CHECK-NOT: __riscv_zvksed {{.*$}} // CHECK-NOT: __riscv_zvksh {{.*$}} +// CHECK-NOT: __riscv_zicond {{.*$}} // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ // RUN: -o - | FileCheck %s @@ -595,3 +596,11 @@ // RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s // CHECK-ZVKSH-EXT: __riscv_zvksh 3000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s +// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -155,6 +155,9 @@ ``experimental-zfa`` LLVM implements a subset of `0.1 draft specification `_ (see Chapter 25). Load-immediate instructions (fli.s/fli.d/fli.h) haven't been implemented yet. +``experimental-zicond`` + LLVM implements the `1.0-rc1 draft specification _. + ``experimental-zihintntl`` LLVM implements the `0.2 draft specification `_. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -151,6 +151,8 @@ * Adds support for the vendor-defined XTHeadSync (multi-core synchronization instructions) extension. * Added support for the vendor-defined XTHeadFMemIdx (indexed memory operations for floating point) extension. * Assembler support for RV64E was added. +* Assembler support was added for the experimental Zicond (integer conditional + operations) extension. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -135,6 +135,7 @@ {"zcd", RISCVExtensionVersion{1, 0}}, {"zcf", RISCVExtensionVersion{1, 0}}, {"zfa", RISCVExtensionVersion{0, 1}}, + {"zicond", RISCVExtensionVersion{1, 0}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -536,6 +536,13 @@ AssemblerPredicate<(all_of FeatureStdExtZvksh), "'Zvksh' (SM3 Hash Function Instructions.)">; +def FeatureStdExtZicond + : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true", + "'Zicond' (Integer Conditional Operations)">; +def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, + AssemblerPredicate<(all_of FeatureStdExtZicond), + "'Zicond' (Integer Conditional Operations)">; + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1913,6 +1913,7 @@ include "RISCVInstrInfoZfa.td" include "RISCVInstrInfoZfh.td" include "RISCVInstrInfoZicbo.td" +include "RISCVInstrInfoZicond.td" //===----------------------------------------------------------------------===// // Vendor extensions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td @@ -0,0 +1,25 @@ +//===-- RISCVInstrInfoZicond.td ----------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard Integer +// Conditional operations extension (Zicond). +// This version is still experimental as the 'Zicond' extension hasn't been +// ratified yet. It is based on v1.0-rc1 of the specification. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZicond] in { +def CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; +def CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; +} // Predicates = [HasStdExtZicond] diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -64,6 +64,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -135,6 +136,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; CHECK: .attribute 4, 16 @@ -201,6 +203,7 @@ ; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" ; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" ; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" +; RV32ZICOND: .attribute 5, "rv32i2p0_zicond1p0" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" @@ -271,6 +274,7 @@ ; RV64ZVKS: .attribute 5, "rv64i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" ; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" ; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" +; RV64ZICOND: .attribute 5, "rv64i2p0_zicond1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -236,3 +236,6 @@ .attribute arch, "rv32izfa0p1" # CHECK: attribute 5, "rv32i2p0_f2p0_zfa0p1" + +.attribute arch, "rv32izicond1p0" +# CHECK: attribute 5, "rv32i2p0_zicond1p0" diff --git a/llvm/test/MC/RISCV/rv32zicond-invalid.s b/llvm/test/MC/RISCV/rv32zicond-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zicond-invalid.s @@ -0,0 +1,18 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s + +# Use of operand modifier on register name +czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction + +# Invalid register name +czero.nez a4, a3, foo # CHECK: :[[@LINE]]:19: error: invalid operand for instruction + +# Invalid operand type +czero.eqz t1, 2, t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction + +# Too many operands +czero.eqz t1, t2, t3, t4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction +czero.nez t1, t2, t3, 4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + +# Too few operands +czero.eqz t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32zicond-valid.s b/llvm/test/MC/RISCV/rv32zicond-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zicond-valid.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra +# CHECK-ASM: encoding: [0xb3,0xd2,0x16,0x0e] +czero.eqz t0, a3, ra + +# CHECK-ASM-AND-OBJ: czero.nez a1, gp, t6 +# CHECK-ASM: encoding: [0xb3,0xf5,0xf1,0x0f] +czero.nez a1, gp, t6