Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1692,17 +1692,23 @@
 ///        MI and CmpInstr
 ///        or if MI opcode is not the S form there must be neither defs of flags
 ///        nor uses of flags between MI and CmpInstr.
-/// - and  C/V flags are not used after CmpInstr
+/// - and  C flag is not used after CmpInstr
 static bool canInstrSubstituteCmpInstr(MachineInstr &MI, MachineInstr &CmpInstr,
                                        const TargetRegisterInfo &TRI) {
+  // NOTE this assertion guarantees that MI.getOpcode() is the S-form of add or
+  // subtraction.
   assert(sForm(MI) != AArch64::INSTRUCTION_LIST_END);
 
   const unsigned CmpOpcode = CmpInstr.getOpcode();
   if (!isADDSRegImm(CmpOpcode) && !isSUBSRegImm(CmpOpcode))
     return false;
 
+  assert((CmpInstr.getOperand(2).isImm() &&
+          CmpInstr.getOperand(2).getImm() == 0) &&
+         "Caller guarantees that CmpInstr compares with constant 0");
+
   std::optional<UsedNZCV> NZVCUsed = examineCFlagsUse(MI, CmpInstr, TRI);
-  if (!NZVCUsed || NZVCUsed->C || NZVCUsed->V)
+  if (!NZVCUsed || NZVCUsed->C)
     return false;
 
   AccessKind AccessToCheck = AK_Write;
Index: llvm/test/CodeGen/AArch64/aarch64-icmp-opt.ll
===================================================================
--- llvm/test/CodeGen/AArch64/aarch64-icmp-opt.ll
+++ llvm/test/CodeGen/AArch64/aarch64-icmp-opt.ll
@@ -7,8 +7,7 @@
 define i32 @sub_icmp_i32(i32 %0, i32 %1) {
 ; CHECK-LABEL: sub_icmp_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub w0, w0, w1
-; CHECK-NEXT:    cmp w0, #0
+; CHECK-NEXT:    subs w0, w0, w1
 ; CHECK-NEXT:    b.le .LBB0_2
 ; CHECK-NEXT:  // %bb.1:
 ; CHECK-NEXT:    b _Z2f2i
@@ -36,8 +35,7 @@
 define i64 @sub_icmp_i64(i64 %0, i64 %1) {
 ; CHECK-LABEL: sub_icmp_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub x0, x0, x1
-; CHECK-NEXT:    cmp x0, #0
+; CHECK-NEXT:    subs x0, x0, x1
 ; CHECK-NEXT:    b.le .LBB1_2
 ; CHECK-NEXT:  // %bb.1:
 ; CHECK-NEXT:    b _Z2f4l
@@ -63,8 +61,7 @@
 define i64 @add_i64(i64 %0, i64 %1) {
 ; CHECK-LABEL: add_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    add x0, x1, x0
-; CHECK-NEXT:    cmp x0, #0
+; CHECK-NEXT:    adds x0, x1, x0
 ; CHECK-NEXT:    b.le .LBB2_2
 ; CHECK-NEXT:  // %bb.1:
 ; CHECK-NEXT:    b _Z2f4l
@@ -90,8 +87,7 @@
 define i32 @add_i32(i32 %0, i32 %1) {
 ; CHECK-LABEL: add_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    add w0, w1, w0
-; CHECK-NEXT:    cmp w0, #0
+; CHECK-NEXT:    adds w0, w1, w0
 ; CHECK-NEXT:    b.le .LBB3_2
 ; CHECK-NEXT:  // %bb.1:
 ; CHECK-NEXT:    b _Z2f4l
Index: llvm/test/CodeGen/AArch64/arm64-csel.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -79,8 +79,7 @@
 define i32@foo6(i32 %a, i32 %b) nounwind ssp {
 ; CHECK-LABEL: foo6:
 ; CHECK:       // %bb.0: // %common.ret
-; CHECK-NEXT:    sub w8, w0, w1
-; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    subs w8, w0, w1
 ; CHECK-NEXT:    csinc w0, w8, wzr, le
 ; CHECK-NEXT:    ret
   %sub = sub nsw i32 %a, %b