diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3872,6 +3872,14 @@
           "GEP address space doesn't match type", &GEP);
   }
 
+  if (TT.isAMDGCN()) {
+    auto *PTy = dyn_cast<PointerType>(GEP.getPointerOperandType());
+    if (auto *VPtrTy = dyn_cast<VectorType>(GEP.getPointerOperandType()))
+      PTy = dyn_cast<PointerType>(VPtrTy->getElementType());
+    Check(!PTy || PTy->getAddressSpace() != 8,
+          "AMDGCN does not allow GEP of buffer resources (addrspace 8)", &GEP);
+  }
+
   visitInstruction(GEP);
 }
 
@@ -3958,6 +3966,13 @@
           "Non-atomic load cannot have SynchronizationScope specified", &LI);
   }
 
+  if (TT.isAMDGCN()) {
+    Check(PTy->getAddressSpace() != 8,
+          "AMDGCN does not allow loads from buffer resources (addrspace 8), "
+          "use intrinsics instead",
+          &LI);
+  }
+
   visitInstruction(LI);
 }
 
@@ -3985,6 +4000,14 @@
     Check(SI.getSyncScopeID() == SyncScope::System,
           "Non-atomic store cannot have SynchronizationScope specified", &SI);
   }
+
+  if (TT.isAMDGCN()) {
+    Check(PTy->getAddressSpace() != 8,
+          "AMDGCN does not allow stores to buffer resources (addrspace 8), use "
+          "intrinsics instead",
+          &SI);
+  }
+
   visitInstruction(SI);
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - < %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s
+; RUN: not --crash llc -disable-verify -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - < %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s
 
 ; GISEL-ERR: LLVM ERROR: cannot select: %{{[0-9]+}}:vgpr_32(s32) = G_LOAD %{{[0-9]+}}:vgpr(p8) :: (load (s32) from %ir.rsrc, addrspace 8)
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - < %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s
+; RUN: not --crash llc -disable-verify -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - < %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s
 
 ; GISEL-ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(p8) = G_PTR_ADD %{{[0-9]+}}:_, %{{[0-9]+}}:_(s128)
 
diff --git a/llvm/test/Verifier/AMDGPU/buffer-rsrc-pointers.ll b/llvm/test/Verifier/AMDGPU/buffer-rsrc-pointers.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Verifier/AMDGPU/buffer-rsrc-pointers.ll
@@ -0,0 +1,31 @@
+; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
+
+target triple = "amdgcn--";
+
+define ptr addrspace(8) @scalar_gep(ptr addrspace(8) %p) {
+  ; CHECK: AMDGCN does not allow GEP of buffer resources (addrspace 8)
+  ; CHECK-NEXT: %ret = getelementptr i8, ptr addrspace(8) %p, i32 0
+  %ret = getelementptr i8, ptr addrspace(8) %p, i32 0
+  ret ptr addrspace(8) %ret
+}
+
+define <2 x ptr addrspace(8)> @vec_gep(<2 x ptr addrspace(8)> %p) {
+  ; CHECK: AMDGCN does not allow GEP of buffer resources (addrspace 8)
+  ; CHECK-NEXT: %ret = getelementptr i8, <2 x ptr addrspace(8)> %p, <2 x i32> <i32 0, i32 1>
+  %ret = getelementptr i8, <2 x ptr addrspace(8)> %p, <2 x i32> <i32 0, i32 1>
+  ret <2 x ptr addrspace(8)> %ret
+}
+
+define i32 @load(ptr addrspace(8) %p) {
+  ; CHECK: AMDGCN does not allow loads from buffer resources (addrspace 8), use intrinsics instead
+  ; CHECK-NEXT: %ret = load i32, ptr addrspace(8) %p, align 4
+  %ret = load i32, ptr addrspace(8) %p
+  ret i32 %ret
+}
+
+define void @store(ptr addrspace(8) %p) {
+  ; CHECK: AMDGCN does not allow stores to buffer resources (addrspace 8), use intrinsics instead
+  ; CHECK-NEXT: store i32 0, ptr addrspace(8) %p, align 4
+  store i32 0, ptr addrspace(8) %p
+  ret void
+}