diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -94,8 +94,7 @@
   // if ignoreCSRForAllocationOrder is evaluated differently.
   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
   for (const MCPhysReg *I = CSR; *I; ++I)
-    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
-      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
+    CSRHintsForAllocOrder[*I] = STI.ignoreCSRForAllocationOrder(mf, *I);
   if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
       IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;