diff --git a/llvm/include/llvm/CMakeLists.txt b/llvm/include/llvm/CMakeLists.txt --- a/llvm/include/llvm/CMakeLists.txt +++ b/llvm/include/llvm/CMakeLists.txt @@ -1,3 +1,10 @@ +if(LLVM_TABLEGEN_TARGET STREQUAL "llvm-tblgen" + AND LLVM_TABLEGEN_EXE STREQUAL "llvm-tblgen" + AND TARGET llvm-min-tblgen) + set(LLVM_TABLEGEN_TARGET "llvm-min-tblgen") + set(LLVM_TABLEGEN_EXE "llvm-min-tblgen") +endif() + add_subdirectory(IR) add_subdirectory(Support) add_subdirectory(Frontend) diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt --- a/llvm/utils/TableGen/CMakeLists.txt +++ b/llvm/utils/TableGen/CMakeLists.txt @@ -1,6 +1,18 @@ add_subdirectory(GlobalISel) -set(LLVM_LINK_COMPONENTS Support) +set(LLVM_LINK_COMPONENTS Support TableGen) + +add_llvm_executable(llvm-min-tblgen EXCLUDE_FROM_ALL + Attributes.cpp + CodeGenIntrinsics.cpp + DirectiveEmitter.cpp + IntrinsicEmitter.cpp + RISCVTargetDefEmitter.cpp + SDNodeProperties.cpp + TableGen.cpp + PARTIAL_SOURCES_INTENDED + ) +set_target_properties(llvm-min-tblgen PROPERTIES FOLDER "Tablegenning") add_tablegen(llvm-tblgen LLVM DESTINATION "${LLVM_TOOLS_INSTALL_DIR}" @@ -8,14 +20,13 @@ AsmMatcherEmitter.cpp AsmWriterEmitter.cpp AsmWriterInst.cpp - Attributes.cpp + CTagsEmitter.cpp CallingConvEmitter.cpp CodeEmitterGen.cpp CodeGenDAGPatterns.cpp CodeGenHwModes.cpp CodeGenInstAlias.cpp CodeGenInstruction.cpp - CodeGenIntrinsics.cpp CodeGenMapTable.cpp CodeGenRegisters.cpp CodeGenSchedule.cpp @@ -28,7 +39,6 @@ DecoderEmitter.cpp DFAEmitter.cpp DFAPacketizerEmitter.cpp - DirectiveEmitter.cpp DisassemblerEmitter.cpp DXILEmitter.cpp ExegesisEmitter.cpp @@ -38,7 +48,6 @@ InfoByHwMode.cpp InstrInfoEmitter.cpp InstrDocsEmitter.cpp - IntrinsicEmitter.cpp OptEmitter.cpp OptParserEmitter.cpp OptRSTEmitter.cpp @@ -47,12 +56,9 @@ CompressInstEmitter.cpp RegisterBankEmitter.cpp RegisterInfoEmitter.cpp - RISCVTargetDefEmitter.cpp - SDNodeProperties.cpp SearchableTableEmitter.cpp SubtargetEmitter.cpp SubtargetFeatureInfo.cpp - TableGen.cpp Types.cpp VarLenCodeEmitterGen.cpp X86DisassemblerTables.cpp @@ -62,7 +68,7 @@ X86ModRMFilters.cpp X86RecognizableInstr.cpp WebAssemblyDisassemblerEmitter.cpp - CTagsEmitter.cpp + $ ) target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel) set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning") diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -568,6 +568,30 @@ ], ) +cc_binary( + name = "llvm-min-tblgen", + srcs = [ + "utils/TableGen/Attributes.cpp", + "utils/TableGen/CodeGenIntrinsics.cpp", + "utils/TableGen/DirectiveEmitter.cpp", + "utils/TableGen/IntrinsicEmitter.cpp", + "utils/TableGen/RISCVTargetDefEmitter.cpp", + "utils/TableGen/SDNodeProperties.cpp", + "utils/TableGen/TableGen.cpp", + + "utils/TableGen/CodeGenIntrinsics.h", + "utils/TableGen/SDNodeProperties.h", + "utils/TableGen/SequenceToOffsetTable.h", + ], + copts = llvm_copts, + stamp = 0, + deps = [ + ":Support", + ":TableGen", + ":config", + ], +) + cc_library( name = "LLVMTableGenGlobalISel", srcs = glob([ @@ -618,7 +642,7 @@ gentbl( name = "intrinsic_enums_gen", tbl_outs = [("-gen-intrinsic-enums", "include/llvm/IR/IntrinsicEnums.inc")], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/IR/Intrinsics.td", td_srcs = glob([ "include/llvm/CodeGen/*.td", @@ -629,7 +653,7 @@ gentbl( name = "intrinsics_impl_gen", tbl_outs = [("-gen-intrinsic-impl", "include/llvm/IR/IntrinsicImpl.inc")], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/IR/Intrinsics.td", td_srcs = glob([ "include/llvm/CodeGen/*.td", @@ -717,7 +741,7 @@ "-gen-intrinsic-enums -intrinsic-prefix=" + target["intrinsic_prefix"], "include/llvm/IR/Intrinsics" + target["name"] + ".h", )], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/IR/Intrinsics.td", td_srcs = glob([ "include/llvm/CodeGen/*.td", @@ -729,7 +753,7 @@ gentbl( name = "attributes_gen", tbl_outs = [("-gen-attrs", "include/llvm/IR/Attributes.inc")], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/IR/Attributes.td", td_srcs = ["include/llvm/IR/Attributes.td"], ) @@ -1099,7 +1123,7 @@ gentbl( name = "RISCVTargetParserDefGen", tbl_outs = [("-gen-riscv-target-def", "include/llvm/TargetParser/RISCVTargetParserDef.inc")], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "lib/Target/RISCV/RISCV.td", td_srcs = [ ":common_target_td_sources", @@ -1353,7 +1377,7 @@ tbl_outs = [ ("--gen-directive-decl", "include/llvm/Frontend/OpenMP/OMP.h.inc"), ], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenMP/OMP.td", td_srcs = [":omp_td_files"], ) @@ -1364,7 +1388,7 @@ tbl_outs = [ ("--gen-directive-impl", "include/llvm/Frontend/OpenMP/OMP.inc"), ], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenMP/OMP.td", td_srcs = [":omp_td_files"], ) @@ -1412,7 +1436,7 @@ tbl_outs = [ ("--gen-directive-decl", "include/llvm/Frontend/OpenACC/ACC.h.inc"), ], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenACC/ACC.td", td_srcs = [":acc_td_files"], ) @@ -1423,7 +1447,7 @@ tbl_outs = [ ("--gen-directive-impl", "include/llvm/Frontend/OpenACC/ACC.inc"), ], - tblgen = ":llvm-tblgen", + tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenACC/ACC.td", td_srcs = [":acc_td_files"], )