diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2204,8 +2204,12 @@
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
   def : InstAlias<"mov $Pd, $Pg/m, $Pn",
                   (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
+
   def : InstAlias<"mov $Pd, $Pn",
                   (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
+  def : InstAlias<"mov $Pd, $Pn",
+                  (ORR_PPzPP PNR8:$Pd, PNR8:$Pn, PNR8:$Pn, PNR8:$Pn), 0>;
+
   def : InstAlias<"mov $Pd, $Pg/z, $Pn",
                   (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
 
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -6570,6 +6570,12 @@
 
   def : InstAlias<asm # "\t$Pt, [$Rn]",
                   (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn, $imm9, mul vl]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -7797,6 +7803,12 @@
 
   def : InstAlias<asm # "\t$Pt, [$Rn]",
                   (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn, $imm9, mul vl]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
 }
 
 class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,
diff --git a/llvm/test/MC/AArch64/SVE/ldr.s b/llvm/test/MC/AArch64/SVE/ldr.s
--- a/llvm/test/MC/AArch64/SVE/ldr.s
+++ b/llvm/test/MC/AArch64/SVE/ldr.s
@@ -44,3 +44,15 @@
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 859f1d45 <unknown>
+
+ldr     pn0, [x0]
+// CHECK-INST: ldr     p0, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x80,0x85]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 85800000 <unknown>
+
+ldr     pn5, [x10, #255, mul vl]
+// CHECK-INST: ldr     p5, [x10, #255, mul vl]
+// CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 859f1d45 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/orr.s b/llvm/test/MC/AArch64/SVE/orr.s
--- a/llvm/test/MC/AArch64/SVE/orr.s
+++ b/llvm/test/MC/AArch64/SVE/orr.s
@@ -153,7 +153,11 @@
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 046831b7 <unknown>
 
-
+mov     pn0.b, pn0.b
+// CHECK-INST: mov     p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 25804000 <unknown>
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
diff --git a/llvm/test/MC/AArch64/SVE/str.s b/llvm/test/MC/AArch64/SVE/str.s
--- a/llvm/test/MC/AArch64/SVE/str.s
+++ b/llvm/test/MC/AArch64/SVE/str.s
@@ -44,3 +44,15 @@
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e59f1d45 <unknown>
+
+str     pn0, [x0]
+// CHECK-INST: str     p0, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x80,0xe5]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: e5800000 <unknown>
+
+str     pn5, [x10, #255, mul vl]
+// CHECK-INST: str     p5, [x10, #255, mul vl]
+// CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: e59f1d45 <unknown>