diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -17,6 +17,40 @@
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = !listremove(SchedMxList, ["MF8"]);
 
+// Multiplier of ResourceCycle for different LMULs.
+//
+// For resources whose cycles are relevant to LMULs, the differences between
+// fractional LMULs and M1 are not so big. So the multipliers of fractional LMULs
+// are 1 here (which is the same as M1) to simplify the scheduling model, so that
+// we can focus on modeling resource cycles based on M1.
+class multiplier<string mx> {
+  int value = !cond(!eq(mx, "UpperBound") : 8,
+                    !eq(mx, "M1")         : 1,
+                    !eq(mx, "M2")         : 2,
+                    !eq(mx, "M4")         : 4,
+                    !eq(mx, "M8")         : 8,
+                    !eq(mx, "MF2")        : 1,
+                    !eq(mx, "MF4")        : 1,
+                    !eq(mx, "MF8")        : 1);
+}
+class ResourceCycle<int cycles> {
+  int Cycles = cycles;
+}
+// ResourceCycle whose cycles are relevant to LMUL.
+class LMULResourceCycle<int cycles> : ResourceCycle<cycles>;
+// ResourceCycle whose cycles are fixed.
+class FixedResourceCycle<int cycles> : ResourceCycle<cycles>;
+// Helper class for generating a list of resource cycles of different LMULs.
+class ResourceCycles<list<ResourceCycle> resourceCycles, string mx> {
+  list<int> value = !foreach(resourceCycle, resourceCycles,
+                             !cond(!isa<LMULResourceCycle>(resourceCycle):
+                                     !mul(resourceCycle.Cycles, multiplier<mx>.value),
+                                   !isa<FixedResourceCycle>(resourceCycle):
+                                     resourceCycle.Cycles
+                                  )
+                            );
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair for each LMUL in each of the
 // SchedMxList variants above.
@@ -31,10 +65,13 @@
     def name # "_" # mx : SchedRead;
   }
 }
-multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {
+multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources,
+                            list<ResourceCycle> resourceCycles> {
   foreach mx = SchedMxList in {
     if !exists<SchedWrite>(name # "_" # mx) then
-      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources> {
+        let ResourceCycles = ResourceCycles<resourceCycles, mx>.value;
+      }
   }
 }
 multiclass LMULReadAdvanceImpl<string name, int val,
@@ -63,31 +100,35 @@
 
 multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
 multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
-multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteRes<string name, list<ProcResourceKind> resources,
+                        list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, resourceCycles>;
 multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
 
 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
-multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResW<string name, list<ProcResourceKind> resources,
+                         list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, resourceCycles>;
 multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
 
 multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
 multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
-multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources,
+                          list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, resourceCycles>;
 multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
 
 multiclass LMULSchedWritesFWRed<string name> : LMULSchedWritesImpl<name, SchedMxListFWRed>;
-multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources,
+                             list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, resourceCycles>;
 class LMULSchedWriteListFWRed<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFWRed>;