diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -38,6 +38,13 @@
                         !eq(mx, "MF4"): [16]);
 }
 
+// Create functions that return fixed cycles.
+function fixed(int cycles): function<int, string, int> {
+  return function(string lmul, int sew = 0): int {
+    return cycles;
+  };
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
@@ -54,12 +61,20 @@
     def name # "_" # mx : SchedRead;
   }
 }
-multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {
+multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources,
+                            function<int, string, int> latency,
+                            list<function<int, string, int>> resourceCycles> {
   if !exists<SchedWrite>(name # "_WorstCase") then
-    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
+    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources> {
+      let Latency = latency("WorstCase");
+      let ResourceCycles = !foreach(resourceCycle, resourceCycles, resourceCycle("WorstCase"));
+    }
   foreach mx = SchedMxList in {
     if !exists<SchedWrite>(name # "_" # mx) then
-      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources> {
+        let Latency = latency(mx);
+        let ResourceCycles = !foreach(resourceCycle, resourceCycles, resourceCycle(mx));
+      }
   }
 }
 multiclass LMULReadAdvanceImpl<string name, int val,
@@ -91,11 +106,19 @@
   }
 }
 multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
+                               function<int, string, int> latency,
+                               list<function<int, string, int>> resourceCycles,
                                bit isF = 0> {
-  def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
+  def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources> {
+    let Latency = latency("WorstCase");
+    let ResourceCycles = !foreach(resourceCycle, resourceCycles, resourceCycle("WorstCase"));
+  }
   foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
     foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
-      def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources> {
+        let Latency = latency(mx, sew);
+        let ResourceCycles = !foreach(resourceCycle, resourceCycles, resourceCycle(mx, sew));
+      }
   }
 }
 multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
@@ -124,45 +147,57 @@
 
 multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
 multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
-multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteRes<string name, list<ProcResourceKind> resources,
+                        function<int, string, int> latency = fixed(1),
+                        list<function<int, string, int>> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
 
 multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;
 multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;
-multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>
-  : LMULSEWWriteResImpl<name, resources>;
+multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources,
+                           function<int, string, int> latency = fixed(1),
+                           list<function<int, string, int>> resourceCycles = []>
+  : LMULSEWWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULSEWReadAdvanceImpl<name, val, writes>;
 
 multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, 1>;
 multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, 1>;
-multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>
-  : LMULSEWWriteResImpl<name, resources, 1>;
+multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources,
+                            function<int, string, int> latency = fixed(1),
+                            list<function<int, string, int>> resourceCycles = []>
+  : LMULSEWWriteResImpl<name, resources, latency, resourceCycles, 1>;
 multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
   : LMULSEWReadAdvanceImpl<name, val, writes, 1>;
 
 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
-multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResW<string name, list<ProcResourceKind> resources,
+                         function<int, string, int> latency = fixed(1),
+                         list<function<int, string, int>> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
 
 multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
 multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
-multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources,
+                          function<int, string, int> latency = fixed(1),
+                          list<function<int, string, int>> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
 
 multiclass LMULSchedWritesFWRed<string name> : LMULSchedWritesImpl<name, SchedMxListFWRed>;
-multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources,
+                             function<int, string, int> latency = fixed(1),
+                             list<function<int, string, int>> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 class LMULSchedWriteListFWRed<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFWRed>;