diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -26,6 +26,31 @@
                         !eq(mx, "MF8"): [8]);
 }
 
+// Index values by LMUL.
+class index<list<int> cycles, string mx> {
+  int value = !cond(!eq(mx, "UpperBound") : cycles[0],
+                    !eq(mx, "M1")         : cycles[1],
+                    !eq(mx, "M2")         : cycles[2],
+                    !eq(mx, "M4")         : cycles[3],
+                    !eq(mx, "M8")         : cycles[4],
+                    !eq(mx, "MF2")        : cycles[5],
+                    !eq(mx, "MF4")        : cycles[6],
+                    !eq(mx, "MF8")        : cycles[7]);
+}
+
+class ResourceCycle {
+  list<int> Cycles;
+}
+// ResourceCycle whose cycles are fixed.
+class FixedResourceCycle<int cycles> : ResourceCycle {
+  let Cycles = !listsplat(cycles, !size(SchedMxList));
+}
+
+// Helper class for generating a list of resource cycles of different LMULs.
+class ResourceCycles<list<ResourceCycle> resourceCycles, string mx> {
+  list<int> value = !foreach(resourceCycle, resourceCycles, index<resourceCycle.Cycles, mx>.value);
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
@@ -42,12 +67,16 @@
     def name # "_" # mx : SchedRead;
   }
 }
-multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {
+multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources,
+                            ResourceCycle latency, list<ResourceCycle> resourceCycles> {
   if !exists<SchedWrite>(name # "_WorstCase") then
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
   foreach mx = SchedMxList in {
     if !exists<SchedWrite>(name # "_" # mx) then
-      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources> {
+        let Latency = index<latency.Cycles, mx>.value;
+        let ResourceCycles = ResourceCycles<resourceCycles, mx>.value;
+      }
   }
 }
 multiclass LMULReadAdvanceImpl<string name, int val,
@@ -111,8 +140,10 @@
 
 multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
 multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
-multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteRes<string name, list<ProcResourceKind> resources,
+                        ResourceCycle latency = FixedResourceCycle<1>,
+                        list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
@@ -126,23 +157,29 @@
 
 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
-multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResW<string name, list<ProcResourceKind> resources,
+                         ResourceCycle latency = FixedResourceCycle<1>,
+                         list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
 
 multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
 multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
-multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources,
+                          ResourceCycle latency = FixedResourceCycle<1>,
+                          list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
 
 multiclass LMULSchedWritesFWRed<string name> : LMULSchedWritesImpl<name, SchedMxListFWRed>;
-multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources>
-  : LMULWriteResImpl<name, resources>;
+multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources,
+                             ResourceCycle latency = FixedResourceCycle<1>,
+                             list<ResourceCycle> resourceCycles = []>
+  : LMULWriteResImpl<name, resources, latency, resourceCycles>;
 class LMULSchedWriteListFWRed<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFWRed>;