diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -481,10 +481,10 @@ : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">; def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; -def IsRV64 : Predicate<"Subtarget->is64Bit()">, +def HasRV64 : Predicate<"Subtarget->hasRV64()">, AssemblerPredicate<(all_of Feature64Bit), "RV64I Base Instruction Set">; -def IsRV32 : Predicate<"!Subtarget->is64Bit()">, +def HasRV32 : Predicate<"!Subtarget->hasRV64()">, AssemblerPredicate<(all_of (not Feature64Bit)), "RV32I Base Instruction Set">; @@ -492,9 +492,9 @@ def RV64 : HwMode<"+64bit">; def FeatureRV32E - : SubtargetFeature<"e", "IsRV32E", "true", + : SubtargetFeature<"e", "HasRV32E", "true", "Implements RV32E (provides 16 rather than 32 GPRs)">; -def IsRV32E : Predicate<"Subtarget->isRV32E()">, +def HasRV32E : Predicate<"Subtarget->hasRV32E()">, AssemblerPredicate<(all_of FeatureRV32E)>; def FeatureRelax diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -69,7 +69,7 @@ const RISCVSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { - if (Subtarget.isRV32E()) + if (Subtarget.hasRV32E()) report_fatal_error("Codegen not yet implemented for RV32E"); RISCVABI::ABI ABI = Subtarget.getTargetABI(); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -762,7 +762,7 @@ /// RV64I instructions -let Predicates = [IsRV64] in { +let Predicates = [HasRV64] in { def LWU : Load_ri<0b110, "lwu">, Sched<[WriteLDW, ReadMemBase]>; def LD : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>; def SD : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>; @@ -789,7 +789,7 @@ def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">, Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>; } // IsSignExtendingOpW = 1 -} // Predicates = [IsRV64] +} // Predicates = [HasRV64] //===----------------------------------------------------------------------===// // Privileged instructions @@ -855,7 +855,7 @@ def HSV_H : HStore_rr<0b0110011, "hsv.h">, Sched<[]>; def HSV_W : HStore_rr<0b0110101, "hsv.w">, Sched<[]>; } -let Predicates = [IsRV64, HasStdExtH] in { +let Predicates = [HasRV64, HasStdExtH] in { def HLV_WU : HLoad_r<0b0110100, 0b00001, "hlv.wu">, Sched<[]>; def HLV_D : HLoad_r<0b0110110, 0b00000, "hlv.d">, Sched<[]>; def HSV_D : HStore_rr<0b0110111, "hsv.d">, Sched<[]>; @@ -898,21 +898,21 @@ def PseudoSH : PseudoStore<"sh">; def PseudoSW : PseudoStore<"sw">; -let Predicates = [IsRV64] in { +let Predicates = [HasRV64] in { def PseudoLWU : PseudoLoad<"lwu">; def PseudoLD : PseudoLoad<"ld">; def PseudoSD : PseudoStore<"sd">; -} // Predicates = [IsRV64] +} // Predicates = [HasRV64] def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm)>; def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>; -let Predicates = [IsRV64] in { +let Predicates = [HasRV64] in { def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>; def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>; -} // Predicates = [IsRV64] +} // Predicates = [HasRV64] def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>; def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>; @@ -976,11 +976,11 @@ def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, CYCLE.Encoding, X0)>; def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, TIME.Encoding, X0)>; -let Predicates = [IsRV32] in { +let Predicates = [HasRV32] in { def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>; def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>; def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>; -} // Predicates = [IsRV32] +} // Predicates = [HasRV32] def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>; def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>; @@ -1050,7 +1050,7 @@ (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; def : InstAlias<"sra $rd, $rs1, $shamt", (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; -let Predicates = [IsRV64] in { +let Predicates = [HasRV64] in { def : InstAlias<"lwu $rd, (${rs1})", (LWU GPR:$rd, GPR:$rs1, 0)>; def : InstAlias<"ld $rd, (${rs1})", @@ -1066,7 +1066,7 @@ (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; def : InstAlias<"sraw $rd, $rs1, $shamt", (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; -} // Predicates = [IsRV64] +} // Predicates = [HasRV64] def : InstAlias<"slt $rd, $rs1, $imm12", (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>; def : InstAlias<"sltu $rd, $rs1, $imm12", @@ -1594,10 +1594,10 @@ def PseudoZEXT_H : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.h", "$rd, $rs">; } // hasSideEffects = 0, ... -let Predicates = [IsRV64], hasSideEffects = 0, mayLoad = 0, mayStore = 0, +let Predicates = [HasRV64], hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, isAsmParserOnly = 1 in { def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs">; -} // Predicates = [IsRV64], ... +} // Predicates = [HasRV64], ... /// Loads @@ -1610,7 +1610,7 @@ defm : LdPat; defm : LdPat; defm : LdPat; -defm : LdPat, Requires<[IsRV32]>; +defm : LdPat, Requires<[HasRV32]>; defm : LdPat; defm : LdPat; @@ -1624,7 +1624,7 @@ defm : StPat; defm : StPat; -defm : StPat, Requires<[IsRV32]>; +defm : StPat, Requires<[HasRV32]>; /// Fences @@ -1715,7 +1715,7 @@ /// RV64 patterns -let Predicates = [IsRV64, NotHasStdExtZba] in { +let Predicates = [HasRV64, NotHasStdExtZba] in { def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>; // If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2 @@ -1747,7 +1747,7 @@ return isUInt<32>(Imm) && isInt<12>(SignExtend64<32>(Imm)); }], ImmSExt32>; -let Predicates = [IsRV64] in { +let Predicates = [HasRV64] in { def : Pat<(i64 (and GPR:$rs, LeadingOnesWMask:$mask)), (SLLI (SRLIW $rs, LeadingOnesWMask:$mask), LeadingOnesWMask:$mask)>; @@ -1807,15 +1807,15 @@ defm : StPat; defm : StPat; -} // Predicates = [IsRV64] +} // Predicates = [HasRV64] /// readcyclecounter // On RV64, we can directly read the 64-bit "cycle" CSR. -let Predicates = [IsRV64] in +let Predicates = [HasRV64] in def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, X0)>; // On RV32, ReadCycleWide will be expanded to the suggested loop reading both // halves of the 64-bit "cycle" CSR. -let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in +let Predicates = [HasRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [(set GPR:$lo, GPR:$hi, (riscv_read_cycle_wide))], "", "">; @@ -1830,7 +1830,7 @@ // debugger if possible. def : Pat<(debugtrap), (EBREAK)>; -let Predicates = [IsRV64], Uses = [X5], +let Predicates = [HasRV64], Uses = [X5], Defs = [X1, X6, X7, X28, X29, X30, X31] in def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo), @@ -1842,7 +1842,7 @@ (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)), (AddiPairImmSmall GPR:$rs2))>; -let Predicates = [IsRV64] in { +let Predicates = [HasRV64] in { // Select W instructions if only the lower 32-bits of the result are used. def : Pat<(binop_allwusers GPR:$rs1, (AddiPair:$rs2)), (ADDIW (ADDIW GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -77,7 +77,7 @@ Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>; } // Predicates = [HasStdExtA] -let Predicates = [HasStdExtA, IsRV64] in { +let Predicates = [HasStdExtA, HasRV64] in { defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>; defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">, Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>; @@ -99,7 +99,7 @@ Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>; defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>; -} // Predicates = [HasStdExtA, IsRV64] +} // Predicates = [HasStdExtA, HasRV64] //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns @@ -118,7 +118,7 @@ defm : AtomicStPat; } -let Predicates = [HasAtomicLdSt, IsRV64] in { +let Predicates = [HasAtomicLdSt, HasRV64] in { defm : LdPat; defm : AtomicStPat; } @@ -307,7 +307,7 @@ } // Predicates = [HasStdExtA] -let Predicates = [HasStdExtA, IsRV64] in { +let Predicates = [HasStdExtA, HasRV64] in { defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">; defm : AMOPat<"atomic_load_add_64", "AMOADD_D">; @@ -375,4 +375,4 @@ GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering), (PseudoMaskedCmpXchg32 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>; -} // Predicates = [HasStdExtA, IsRV64] +} // Predicates = [HasStdExtA, HasRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -328,7 +328,7 @@ } let DecoderNamespace = "RISCV32Only_", - Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in + Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>, Sched<[WriteFLD32, ReadMemBase]> { bits<7> imm; @@ -337,7 +337,7 @@ let Inst{5} = imm{6}; } -let Predicates = [HasStdExtCOrZca, IsRV64] in +let Predicates = [HasStdExtCOrZca, HasRV64] in def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>, Sched<[WriteLDD, ReadMemBase]> { bits<8> imm; @@ -362,7 +362,7 @@ } let DecoderNamespace = "RISCV32Only_", - Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in + Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>, Sched<[WriteFST32, ReadStoreData, ReadMemBase]> { bits<7> imm; @@ -371,7 +371,7 @@ let Inst{5} = imm{6}; } -let Predicates = [HasStdExtCOrZca, IsRV64] in +let Predicates = [HasStdExtCOrZca, HasRV64] in def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>, Sched<[WriteSTD, ReadStoreData, ReadMemBase]> { bits<8> imm; @@ -407,12 +407,12 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, DecoderNamespace = "RISCV32Only_", Defs = [X1], - Predicates = [HasStdExtCOrZca, IsRV32] in + Predicates = [HasStdExtCOrZca, HasRV32] in def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset), "c.jal", "$offset">, Sched<[WriteJal]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0, - Predicates = [HasStdExtCOrZca, IsRV64] in + Predicates = [HasStdExtCOrZca, HasRV64] in def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm6:$imm), "c.addiw", "$rd, $imm">, @@ -474,7 +474,7 @@ def C_AND : CA_ALU<0b100011, 0b11, "c.and", GPRC>, Sched<[WriteIALU, ReadIALU, ReadIALU]>; -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def C_SUBW : CA_ALU<0b100111, 0b00, "c.subw", GPRC>, Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; def C_ADDW : CA_ALU<0b100111, 0b01, "c.addw", GPRC>, @@ -515,14 +515,14 @@ } let DecoderNamespace = "RISCV32Only_", - Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in + Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>, Sched<[WriteFLD32, ReadMemBase]> { let Inst{6-4} = imm{4-2}; let Inst{3-2} = imm{7-6}; } -let Predicates = [HasStdExtCOrZca, IsRV64] in +let Predicates = [HasStdExtCOrZca, HasRV64] in def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>, Sched<[WriteLDD, ReadMemBase]> { let Inst{6-5} = imm{4-3}; @@ -575,14 +575,14 @@ } let DecoderNamespace = "RISCV32Only_", - Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in + Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>, Sched<[WriteFST32, ReadStoreData, ReadMemBase]> { let Inst{12-9} = imm{5-2}; let Inst{8-7} = imm{7-6}; } -let Predicates = [HasStdExtCOrZca, IsRV64] in +let Predicates = [HasStdExtCOrZca, HasRV64] in def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>, Sched<[WriteSTD, ReadStoreData, ReadMemBase]> { let Inst{12-10} = imm{5-3}; @@ -726,14 +726,14 @@ def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SPMem:$rs1, 0)>; } -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRCMem:$rs1, 0)>; def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRCMem:$rs1, 0)>; def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SPMem:$rs1, 0)>; def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SPMem:$rs1, 0)>; } -let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in { def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>; def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>; def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SPMem:$rs1, 0)>; @@ -771,15 +771,15 @@ (C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in { def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm), (C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtF, IsRV32] +} // Predicates = [HasStdExtC, HasStdExtF, HasRV32] -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm), (C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>; -} // Predicates = [HasStdExtCOrZca, IsRV64] +} // Predicates = [HasStdExtCOrZca, HasRV64] let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm), @@ -791,15 +791,15 @@ (C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in { def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm), (C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtF, IsRV32] +} // Predicates = [HasStdExtC, HasStdExtF, HasRV32] -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def : CompressPat<(SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm), (C_SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>; -} // Predicates = [HasStdExtCOrZca, IsRV64] +} // Predicates = [HasStdExtCOrZca, HasRV64] // Quadrant 1 let Predicates = [HasStdExtCOrZca] in { @@ -808,15 +808,15 @@ (C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtCOrZca, IsRV32] in { +let Predicates = [HasStdExtCOrZca, HasRV32] in { def : CompressPat<(JAL X1, simm12_lsb0:$offset), (C_JAL simm12_lsb0:$offset)>; -} // Predicates = [HasStdExtCOrZca, IsRV32] +} // Predicates = [HasStdExtCOrZca, HasRV32] -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def : CompressPat<(ADDIW GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm), (C_ADDIW GPRNoX0:$rs1, simm6:$imm)>; -} // Predicates = [HasStdExtCOrZca, IsRV64] +} // Predicates = [HasStdExtCOrZca, HasRV64] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm), @@ -850,7 +850,7 @@ (C_AND GPRC:$rs1, GPRC:$rs2)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { let isCompressOnly = true in def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm), (C_LI GPRNoX0:$rd, simm6:$imm)>; @@ -861,7 +861,7 @@ let isCompressOnly = true in def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1), (C_ADDW GPRC:$rs1, GPRC:$rs2)>; -} // Predicates = [HasStdExtCOrZca, IsRV64] +} // Predicates = [HasStdExtCOrZca, HasRV64] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(JAL X0, simm12_lsb0:$offset), @@ -888,15 +888,15 @@ (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in { def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm), (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtF, IsRV32] +} // Predicates = [HasStdExtC, HasStdExtF, HasRV32] -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm), (C_LDSP GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>; -} // Predicates = [HasStdExtCOrZca, IsRV64] +} // Predicates = [HasStdExtCOrZca, HasRV64] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0), @@ -930,12 +930,12 @@ (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtCOrZcf, HasStdExtF, HasRV32] in { def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm), (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtF, IsRV32] +} // Predicates = [HasStdExtC, HasStdExtF, HasRV32] -let Predicates = [HasStdExtCOrZca, IsRV64] in { +let Predicates = [HasStdExtCOrZca, HasRV64] in { def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm), (C_SDSP GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>; -} // Predicates = [HasStdExtCOrZca, IsRV64] +} // Predicates = [HasStdExtCOrZca, HasRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -53,9 +53,9 @@ } def DExt : ExtInfo<0, [HasStdExtD]>; -def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>; -def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>; -def Zdinx32Ext : ExtInfo<2, [HasStdExtZdinx, IsRV32]>; +def D64Ext : ExtInfo<0, [HasStdExtD, HasRV64]>; +def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, HasRV64]>; +def Zdinx32Ext : ExtInfo<2, [HasStdExtZdinx, HasRV32]>; def D : ExtInfo_r; def D_INX : ExtInfo_r; @@ -184,7 +184,7 @@ Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; defm : FPUnaryOpDynFrmAlias_m; -let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in +let Predicates = [HasStdExtD, HasRV64], mayRaiseFPException = 0 in def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">, Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>; @@ -196,7 +196,7 @@ Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; defm : FPUnaryOpDynFrmAlias_m; -let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in +let Predicates = [HasStdExtD, HasRV64], mayRaiseFPException = 0 in def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">, Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>; @@ -227,7 +227,7 @@ } } // Predicates = [HasStdExtD] -let Predicates = [HasStdExtZdinx, IsRV64] in { +let Predicates = [HasStdExtZdinx, HasRV64] in { def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; @@ -235,9 +235,9 @@ (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; def : InstAlias<"fge.d $rd, $rs, $rt", (FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; -} // Predicates = [HasStdExtZdinx, IsRV64] +} // Predicates = [HasStdExtZdinx, HasRV64] -let Predicates = [HasStdExtZdinx, IsRV32] in { +let Predicates = [HasStdExtZdinx, HasRV32] in { def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; @@ -245,7 +245,7 @@ (FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; def : InstAlias<"fge.d $rd, $rs, $rt", (FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; -} // Predicates = [HasStdExtZdinx, IsRV32] +} // Predicates = [HasStdExtZdinx, HasRV32] //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns @@ -259,7 +259,7 @@ def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>; def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>; -// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so +// [u]int<->double conversion patterns must be gated on HasRV32 or HasRV64, so // are defined later. /// Float arithmetic operations @@ -364,7 +364,7 @@ } // Predicates = [HasStdExtD] -let Predicates = [HasStdExtD, IsRV32] in { +let Predicates = [HasStdExtD, HasRV32] in { /// Float constants def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>; @@ -388,9 +388,9 @@ // [u]int->double. def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>; def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>; -} // Predicates = [HasStdExtD, IsRV32] +} // Predicates = [HasStdExtD, HasRV32] -let Predicates = [HasStdExtD, IsRV64] in { +let Predicates = [HasStdExtD, HasRV64] in { /// Float constants def : Pat<(f64 (fpimm0)), (FMV_D_X (i64 X0))>; @@ -430,4 +430,4 @@ // [u]int64->fp. Match GCC and default to using dynamic rounding mode. def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>; def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, 0b111)>; -} // Predicates = [HasStdExtD, IsRV64] +} // Predicates = [HasStdExtD, HasRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -110,9 +110,9 @@ } def FExt : ExtInfo<0, [HasStdExtF]>; -def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>; +def F64Ext : ExtInfo<0, [HasStdExtF, HasRV64]>; def ZfinxExt : ExtInfo<1, [HasStdExtZfinx]>; -def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>; +def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, HasRV64]>; def F : ExtInfo_r; def F_INX : ExtInfo_r; @@ -511,7 +511,7 @@ /// Float conversion operations -// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so +// [u]int32<->float conversion patterns must be gated on HasRV32 or HasRV64, so // are defined later. /// Float arithmetic operations @@ -599,7 +599,7 @@ } // Predicates = [HasStdExtF] -let Predicates = [HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtF, HasRV32] in { // Moves (no conversion) def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>; def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>; @@ -621,9 +621,9 @@ // [u]int->float. Match GCC and default to using dynamic rounding mode. def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>; def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; -} // Predicates = [HasStdExtF, IsRV32] +} // Predicates = [HasStdExtF, HasRV32] -let Predicates = [HasStdExtF, IsRV64] in { +let Predicates = [HasStdExtF, HasRV64] in { // Moves (no conversion) def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; @@ -657,4 +657,4 @@ def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>; def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>; def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>; -} // Predicates = [HasStdExtF, IsRV64] +} // Predicates = [HasStdExtF, HasRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td @@ -46,12 +46,12 @@ Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>; } // Predicates = [HasStdExtM] -let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtMOrZmmul, HasRV64], IsSignExtendingOpW = 1 in { def MULW : ALUW_rr<0b0000001, 0b000, "mulw", /*Commutable*/1>, Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>; -} // Predicates = [HasStdExtMOrZmmul, IsRV64] +} // Predicates = [HasStdExtMOrZmmul, HasRV64] -let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtM, HasRV64], IsSignExtendingOpW = 1 in { def DIVW : ALUW_rr<0b0000001, 0b100, "divw">, Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>; def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">, @@ -60,7 +60,7 @@ Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>; def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">, Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>; -} // Predicates = [HasStdExtM, IsRV64] +} // Predicates = [HasStdExtM, HasRV64] //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns @@ -81,10 +81,10 @@ } // Predicates = [HasStdExtM] // Select W instructions if only the lower 32-bits of the result are used. -let Predicates = [HasStdExtMOrZmmul, IsRV64] in +let Predicates = [HasStdExtMOrZmmul, HasRV64] in def : PatGprGpr, MULW>; -let Predicates = [HasStdExtM, IsRV64] in { +let Predicates = [HasStdExtM, HasRV64] in { def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; @@ -104,13 +104,13 @@ // produce a result where res[63:32]=0 and res[31]=1. def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))), (REMW GPR:$rs1, GPR:$rs2)>; -} // Predicates = [HasStdExtM, IsRV64] +} // Predicates = [HasStdExtM, HasRV64] -let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in { +let Predicates = [HasStdExtMOrZmmul, HasRV64, NotHasStdExtZba] in { // Special case for calculating the full 64-bit product of a 32x32 unsigned // multiply where the inputs aren't known to be zero extended. We can shift the // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish // zeroing the upper 32 bits. def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))), (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>; -} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] +} // Predicates = [HasStdExtMOrZmmul, HasRV64, NotHasStdExtZba] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1053,10 +1053,10 @@ defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R>; defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R>; } // Predicates = [HasVInstructionsI64] -let Predicates = [IsRV64, HasVInstructionsI64] in { +let Predicates = [HasRV64, HasVInstructionsI64] in { // Vector Indexed Instructions defm "" : VIndexLoadStore<[64]>; -} // [IsRV64, HasVInstructionsI64] +} // [HasRV64, HasVInstructionsI64] let Predicates = [HasVInstructions] in { // Vector Single-Width Integer Add and Subtract @@ -1745,7 +1745,7 @@ VSSSEGSched; } } // Predicates = [HasVInstructionsI64] -let Predicates = [HasVInstructionsI64, IsRV64] in { +let Predicates = [HasVInstructionsI64, HasRV64] in { foreach nf = 2 - 8 in { // Vector Indexed Segment Instructions def VLUXSEG #nf #EI64_V @@ -1765,6 +1765,6 @@ "vsoxseg" #nf #"ei64.v">, VSXSEGSched; } -} // Predicates = [HasVInstructionsI64, IsRV64] +} // Predicates = [HasVInstructionsI64, HasRV64] include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td @@ -14,7 +14,7 @@ // XVentanaCondOps //===----------------------------------------------------------------------===// -let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0, +let Predicates = [HasRV64, HasVendorXVentanaCondOps], hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana" in class VTMaskedMove funct3, string opcodestr> : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd), @@ -28,7 +28,7 @@ def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; -let Predicates = [IsRV64, HasVendorXVentanaCondOps] in { +let Predicates = [HasRV64, HasVendorXVentanaCondOps] in { // Directly use MASKC/MASKCN in case of any of the operands being 0. def : Pat<(select GPR:$rc, GPR:$rs1, (i64 0)), (VT_MASKC $rs1, $rc)>; @@ -107,4 +107,4 @@ (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)), (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>; -} // Predicates = [IsRV64, HasVendorXVentanaCondOps] +} // Predicates = [HasRV64, HasVendorXVentanaCondOps] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -320,7 +320,7 @@ Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>; } // Predicates = [HasStdExtZba] -let Predicates = [HasStdExtZba, IsRV64] in { +let Predicates = [HasStdExtZba, HasRV64] in { def SLLI_UW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[WriteShiftImm32, ReadShiftImm32]>; def ADD_UW : ALUW_rr<0b0000100, 0b000, "add.uw">, @@ -331,7 +331,7 @@ Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>; def SH3ADD_UW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">, Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>; -} // Predicates = [HasStdExtZba, IsRV64] +} // Predicates = [HasStdExtZba, HasRV64] let Predicates = [HasStdExtZbbOrZbkb] in { def ROL : ALU_rr<0b0110000, 0b001, "rol">, @@ -343,7 +343,7 @@ Sched<[WriteRotateImm, ReadRotateImm]>; } // Predicates = [HasStdExtZbbOrZbkb] -let Predicates = [HasStdExtZbbOrZbkb, IsRV64], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZbbOrZbkb, HasRV64], IsSignExtendingOpW = 1 in { def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">, Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; def RORW : ALUW_rr<0b0110000, 0b101, "rorw">, @@ -351,7 +351,7 @@ def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[WriteRotateImm32, ReadRotateImm32]>; -} // Predicates = [HasStdExtZbbOrZbkb, IsRV64] +} // Predicates = [HasStdExtZbbOrZbkb, HasRV64] let Predicates = [HasStdExtZbs] in { def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, @@ -394,14 +394,14 @@ Sched<[WriteCPOP, ReadCPOP]>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZbb, HasRV64], IsSignExtendingOpW = 1 in { def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM_32, "clzw">, Sched<[WriteCLZ32, ReadCLZ32]>; def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM_32, "ctzw">, Sched<[WriteCTZ32, ReadCTZ32]>; def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM_32, "cpopw">, Sched<[WriteCPOP32, ReadCPOP32]>; -} // Predicates = [HasStdExtZbb, IsRV64] +} // Predicates = [HasStdExtZbb, HasRV64] let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in { def SEXT_B : RVBUnary<0b0110000, 0b00100, 0b001, OPC_OP_IMM, "sext.b">, @@ -441,29 +441,29 @@ Sched<[WritePACK, ReadPACK, ReadPACK]>; } // Predicates = [HasStdExtZbkb] -let Predicates = [HasStdExtZbkb, IsRV64], IsSignExtendingOpW = 1 in +let Predicates = [HasStdExtZbkb, HasRV64], IsSignExtendingOpW = 1 in def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[WritePACK32, ReadPACK32, ReadPACK32]>; -let Predicates = [HasStdExtZbb, IsRV32] in { +let Predicates = [HasStdExtZbb, HasRV32] in { def ZEXT_H_RV32 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP, "zext.h">, Sched<[WriteIALU, ReadIALU]>; -} // Predicates = [HasStdExtZbb, IsRV32] +} // Predicates = [HasStdExtZbb, HasRV32] -let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZbb, HasRV64], IsSignExtendingOpW = 1 in { def ZEXT_H_RV64 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP_32, "zext.h">, Sched<[WriteIALU, ReadIALU]>; -} // Predicates = [HasStdExtZbb, IsRV64] +} // Predicates = [HasStdExtZbb, HasRV64] -let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in { +let Predicates = [HasStdExtZbbOrZbkb, HasRV32] in { def REV8_RV32 : RVBUnary<0b0110100, 0b11000, 0b101, OPC_OP_IMM, "rev8">, Sched<[WriteREV8, ReadREV8]>; -} // Predicates = [HasStdExtZbbOrZbkb, IsRV32] +} // Predicates = [HasStdExtZbbOrZbkb, HasRV32] -let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { +let Predicates = [HasStdExtZbbOrZbkb, HasRV64] in { def REV8_RV64 : RVBUnary<0b0110101, 0b11000, 0b101, OPC_OP_IMM, "rev8">, Sched<[WriteREV8, ReadREV8]>; -} // Predicates = [HasStdExtZbbOrZbkb, IsRV64] +} // Predicates = [HasStdExtZbbOrZbkb, HasRV64] let Predicates = [HasStdExtZbb] in { def ORC_B : RVBUnary<0b0010100, 0b00111, 0b101, OPC_OP_IMM, "orc.b">, @@ -474,31 +474,31 @@ def BREV8 : RVBUnary<0b0110100, 0b00111, 0b101, OPC_OP_IMM, "brev8">, Sched<[WriteBREV8, ReadBREV8]>; -let Predicates = [HasStdExtZbkb, IsRV32] in { +let Predicates = [HasStdExtZbkb, HasRV32] in { def ZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b001, OPC_OP_IMM, "zip">, Sched<[WriteZIP, ReadZIP]>; def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">, Sched<[WriteZIP, ReadZIP]>; -} // Predicates = [HasStdExtZbkb, IsRV32] +} // Predicates = [HasStdExtZbkb, HasRV32] //===----------------------------------------------------------------------===// // Pseudo Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZba, IsRV64] in { +let Predicates = [HasStdExtZba, HasRV64] in { def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>; -} // Predicates = [HasStdExtZba, IsRV64] +} // Predicates = [HasStdExtZba, HasRV64] let Predicates = [HasStdExtZbb] in { def : InstAlias<"ror $rd, $rs1, $shamt", (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbb, IsRV64] in { +let Predicates = [HasStdExtZbb, HasRV64] in { def : InstAlias<"rorw $rd, $rs1, $shamt", (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>; -} // Predicates = [HasStdExtZbb, IsRV64] +} // Predicates = [HasStdExtZbb, HasRV64] let Predicates = [HasStdExtZbs] in { def : InstAlias<"bset $rd, $rs1, $shamt", @@ -532,13 +532,13 @@ (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>; } // Predicates = [HasStdExtZbbOrZbkb] -let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { +let Predicates = [HasStdExtZbbOrZbkb, HasRV64] in { def : PatGprGpr, ROLW>; def : PatGprGpr, RORW>; def : PatGprImm; def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2), (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>; -} // Predicates = [HasStdExtZbbOrZbkb, IsRV64] +} // Predicates = [HasStdExtZbbOrZbkb, HasRV64] let Predicates = [HasStdExtZbs] in { def : Pat<(and (not (shiftop 1, GPR:$rs2)), GPR:$rs1), @@ -595,11 +595,11 @@ def : Pat<(riscv_brev8 GPR:$rs1), (BREV8 GPR:$rs1)>; } // Predicates = [HasStdExtZbkb] -let Predicates = [HasStdExtZbkb, IsRV32] in { +let Predicates = [HasStdExtZbkb, HasRV32] in { // We treat zip and unzip as separate instructions, so match it directly. def : Pat<(i32 (riscv_zip GPR:$rs1)), (ZIP_RV32 GPR:$rs1)>; def : Pat<(i32 (riscv_unzip GPR:$rs1)), (UNZIP_RV32 GPR:$rs1)>; -} // Predicates = [HasStdExtZbkb, IsRV32] +} // Predicates = [HasStdExtZbkb, HasRV32] let Predicates = [HasStdExtZbb] in { def : PatGpr; @@ -607,14 +607,14 @@ def : PatGpr; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbb, IsRV64] in { +let Predicates = [HasStdExtZbb, HasRV64] in { def : PatGpr; def : PatGpr; def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>; def : Pat<(i64 (riscv_absw GPR:$rs1)), (MAX GPR:$rs1, (SUBW X0, GPR:$rs1))>; -} // Predicates = [HasStdExtZbb, IsRV64] +} // Predicates = [HasStdExtZbb, HasRV64] let Predicates = [HasStdExtZbb] in { def : Pat<(sext_inreg GPR:$rs1, i8), (SEXT_B GPR:$rs1)>; @@ -628,13 +628,13 @@ def : PatGprGpr; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in { +let Predicates = [HasStdExtZbbOrZbkb, HasRV32] in { def : Pat<(i32 (bswap GPR:$rs1)), (REV8_RV32 GPR:$rs1)>; -} // Predicates = [HasStdExtZbbOrZbkb, IsRV32] +} // Predicates = [HasStdExtZbbOrZbkb, HasRV32] -let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { +let Predicates = [HasStdExtZbbOrZbkb, HasRV64] in { def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>; -} // Predicates = [HasStdExtZbbOrZbkb, IsRV64] +} // Predicates = [HasStdExtZbbOrZbkb, HasRV64] let Predicates = [HasStdExtZbkb] in { def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF), @@ -648,11 +648,11 @@ (PACKH GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbkb] -let Predicates = [HasStdExtZbkb, IsRV32] in +let Predicates = [HasStdExtZbkb, HasRV32] in def : Pat<(i32 (or (zexti16 GPR:$rs1), (shl GPR:$rs2, (i32 16)))), (PACK GPR:$rs1, GPR:$rs2)>; -let Predicates = [HasStdExtZbkb, IsRV64] in { +let Predicates = [HasStdExtZbkb, HasRV64] in { def : Pat<(i64 (or (zexti32 GPR:$rs1), (shl GPR:$rs2, (i64 32)))), (PACK GPR:$rs1, GPR:$rs2)>; @@ -662,11 +662,11 @@ def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32), (zexti16 GPR:$rs1))), (PACKW GPR:$rs1, GPR:$rs2)>; -} // Predicates = [HasStdExtZbkb, IsRV64] +} // Predicates = [HasStdExtZbkb, HasRV64] -let Predicates = [HasStdExtZbb, IsRV32] in +let Predicates = [HasStdExtZbb, HasRV32] in def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>; -let Predicates = [HasStdExtZbb, IsRV64] in +let Predicates = [HasStdExtZbb, HasRV64] in def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>; let Predicates = [HasStdExtZba] in { @@ -745,7 +745,7 @@ (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>; } // Predicates = [HasStdExtZba] -let Predicates = [HasStdExtZba, IsRV64] in { +let Predicates = [HasStdExtZba, HasRV64] in { def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)), (SLLI_UW GPR:$rs1, uimm5:$shamt)>; // Match a shifted 0xffffffff mask. Use SRLI to clear the LSBs and SLLI_UW to @@ -804,7 +804,7 @@ def : Pat<(mul (binop_oneuse GPR:$r, 0xFFFFFFFF), C9LeftShiftUW:$i), (SH3ADD (SLLI_UW GPR:$r, (TrailingZeros C9LeftShiftUW:$i)), (SLLI_UW GPR:$r, (TrailingZeros C9LeftShiftUW:$i)))>; -} // Predicates = [HasStdExtZba, IsRV64] +} // Predicates = [HasStdExtZba, HasRV64] let Predicates = [HasStdExtZbcOrZbkc] in { def : PatGprGpr; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td @@ -47,7 +47,7 @@ // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in +let Predicates = [HasStdExtZcb, HasStdExtZba, HasRV64] in def C_ZEXT_W : RVZcArith_r<0b11100 , "c.zext.w">, Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; @@ -143,10 +143,10 @@ (C_ZEXT_B GPRC:$rs1, GPRC:$rs1)>; } // Predicates = [HasStdExtZcb] -let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{ +let Predicates = [HasStdExtZcb, HasStdExtZba, HasRV64] in{ def : CompressPat<(ADD_UW GPRC:$rs1, GPRC:$rs1, X0), (C_ZEXT_W GPRC:$rs1, GPRC:$rs1)>; -} // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] +} // Predicates = [HasStdExtZcb, HasStdExtZba, HasRV64] let Predicates = [HasStdExtZcb] in{ def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -39,11 +39,11 @@ } def ZfhExt : ExtInfo<0, [HasStdExtZfh]>; -def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>; +def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, HasRV64]>; def ZfhminExt : ExtInfo<0, [HasStdExtZfhOrZfhmin]>; def ZhinxExt : ExtInfo<1, [HasStdExtZhinx]>; def ZhinxminExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>; -def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>; +def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, HasRV64]>; def ZfhminDExt : ExtInfo<0, [HasStdExtZfhOrZfhmin, HasStdExtD]>; def ZhinxminZdinxExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx]>; @@ -260,7 +260,7 @@ /// Float conversion operations -// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so +// [u]int32<->float conversion patterns must be gated on HasRV32 or HasRV64, so // are defined later. /// Float arithmetic operations @@ -367,7 +367,7 @@ def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>; } // Predicates = [HasStdExtZfhOrZfhmin] -let Predicates = [HasStdExtZfh, IsRV32] in { +let Predicates = [HasStdExtZfh, HasRV32] in { // half->[u]int. Round-to-zero must be used. def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>; def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>; @@ -385,9 +385,9 @@ // [u]int->half. Match GCC and default to using dynamic rounding mode. def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>; def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>; -} // Predicates = [HasStdExtZfh, IsRV32] +} // Predicates = [HasStdExtZfh, HasRV32] -let Predicates = [HasStdExtZfh, IsRV64] in { +let Predicates = [HasStdExtZfh, HasRV64] in { // Use target specific isd nodes to help us remember the result is sign // extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be // duplicated if it has another user that didn't need the sign_extend. @@ -415,7 +415,7 @@ def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>; def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>; def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>; -} // Predicates = [HasStdExtZfh, IsRV64] +} // Predicates = [HasStdExtZfh, HasRV64] let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in { /// Float conversion operations @@ -434,7 +434,7 @@ def : Pat<(f16 (fpimmneg0)), (FCVT_H_S (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0)), 0b111)>; } // Predicates = [HasStdExtZfhmin, NoStdExtZfh] -let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV32] in { +let Predicates = [HasStdExtZfhmin, NoStdExtZfh, HasRV32] in { // half->[u]int. Round-to-zero must be used. def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), 0b001)>; def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_S (FCVT_S_H $rs1), 0b001)>; @@ -448,9 +448,9 @@ // [u]int->half. Match GCC and default to using dynamic rounding mode. def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S (FCVT_S_W $rs1, 0b111), 0b111)>; def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S (FCVT_S_WU $rs1, 0b111), 0b111)>; -} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV32] +} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, HasRV32] -let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in { +let Predicates = [HasStdExtZfhmin, NoStdExtZfh, HasRV64] in { // half->[u]int64. Round-to-zero must be used. def : Pat<(i64 (any_fp_to_sint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), 0b001)>; def : Pat<(i64 (any_fp_to_uint FPR16:$rs1)), (FCVT_LU_S (FCVT_S_H $rs1), 0b001)>; @@ -466,4 +466,4 @@ // [u]int->fp. Match GCC and default to using dynamic rounding mode. def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S (FCVT_S_L $rs1, 0b111), 0b111)>; def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S (FCVT_S_LU $rs1, 0b111), 0b111)>; -} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] +} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, HasRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td @@ -68,33 +68,33 @@ //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZknd, IsRV32] in { +let Predicates = [HasStdExtZknd, HasRV32] in { def AES32DSI : RVKByteSelect<0b10101, "aes32dsi">; def AES32DSMI : RVKByteSelect<0b10111, "aes32dsmi">; -} // Predicates = [HasStdExtZknd, IsRV32] +} // Predicates = [HasStdExtZknd, HasRV32] -let Predicates = [HasStdExtZknd, IsRV64] in { +let Predicates = [HasStdExtZknd, HasRV64] in { def AES64DS : ALU_rr<0b0011101, 0b000, "aes64ds">; def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">; def AES64IM : RVKUnary<0b001100000000, 0b001, "aes64im">; -} // Predicates = [HasStdExtZknd, IsRV64] +} // Predicates = [HasStdExtZknd, HasRV64] -let Predicates = [HasStdExtZkndOrZkne, IsRV64] in { +let Predicates = [HasStdExtZkndOrZkne, HasRV64] in { def AES64KS2 : ALU_rr<0b0111111, 0b000, "aes64ks2">; def AES64KS1I : RVKUnary_rnum<0b0011000, 0b001, "aes64ks1i">; -} // Predicates = [HasStdExtZkndOrZkne, IsRV64] +} // Predicates = [HasStdExtZkndOrZkne, HasRV64] -let Predicates = [HasStdExtZkne, IsRV32] in { +let Predicates = [HasStdExtZkne, HasRV32] in { def AES32ESI : RVKByteSelect<0b10001, "aes32esi">; def AES32ESMI : RVKByteSelect<0b10011, "aes32esmi">; -} // Predicates = [HasStdExtZkne, IsRV32] +} // Predicates = [HasStdExtZkne, HasRV32] -let Predicates = [HasStdExtZkne, IsRV64] in { +let Predicates = [HasStdExtZkne, HasRV64] in { def AES64ES : ALU_rr<0b0011001, 0b000, "aes64es">; def AES64ESM : ALU_rr<0b0011011, 0b000, "aes64esm">; -} // Predicates = [HasStdExtZkne, IsRV64] +} // Predicates = [HasStdExtZkne, HasRV64] let Predicates = [HasStdExtZknh], IsSignExtendingOpW = 1 in { def SHA256SIG0 : RVKUnary<0b000100000010, 0b001, "sha256sig0">; @@ -103,21 +103,21 @@ def SHA256SUM1 : RVKUnary<0b000100000001, 0b001, "sha256sum1">; } // Predicates = [HasStdExtZknh] -let Predicates = [HasStdExtZknh, IsRV32] in { +let Predicates = [HasStdExtZknh, HasRV32] in { def SHA512SIG0H : ALU_rr<0b0101110, 0b000, "sha512sig0h">; def SHA512SIG0L : ALU_rr<0b0101010, 0b000, "sha512sig0l">; def SHA512SIG1H : ALU_rr<0b0101111, 0b000, "sha512sig1h">; def SHA512SIG1L : ALU_rr<0b0101011, 0b000, "sha512sig1l">; def SHA512SUM0R : ALU_rr<0b0101000, 0b000, "sha512sum0r">; def SHA512SUM1R : ALU_rr<0b0101001, 0b000, "sha512sum1r">; -} // [HasStdExtZknh, IsRV32] +} // [HasStdExtZknh, HasRV32] -let Predicates = [HasStdExtZknh, IsRV64] in { +let Predicates = [HasStdExtZknh, HasRV64] in { def SHA512SIG0 : RVKUnary<0b000100000110, 0b001, "sha512sig0">; def SHA512SIG1 : RVKUnary<0b000100000111, 0b001, "sha512sig1">; def SHA512SUM0 : RVKUnary<0b000100000100, 0b001, "sha512sum0">; def SHA512SUM1 : RVKUnary<0b000100000101, 0b001, "sha512sum1">; -} // Predicates = [HasStdExtZknh, IsRV64] +} // Predicates = [HasStdExtZknh, HasRV64] let Predicates = [HasStdExtZksed] in { def SM4ED : RVKByteSelect<0b11000, "sm4ed">; @@ -138,33 +138,33 @@ (Inst GPR:$rs1, GPR:$rs2, byteselect:$imm)>; // Zknd -let Predicates = [HasStdExtZknd, IsRV32] in { +let Predicates = [HasStdExtZknd, HasRV32] in { def : PatGprGprByteSelect; def : PatGprGprByteSelect; -} // Predicates = [HasStdExtZknd, IsRV32] +} // Predicates = [HasStdExtZknd, HasRV32] -let Predicates = [HasStdExtZknd, IsRV64] in { +let Predicates = [HasStdExtZknd, HasRV64] in { def : PatGprGpr; def : PatGprGpr; def : PatGpr; -} // Predicates = [HasStdExtZknd, IsRV64] +} // Predicates = [HasStdExtZknd, HasRV64] -let Predicates = [HasStdExtZkndOrZkne, IsRV64] in { +let Predicates = [HasStdExtZkndOrZkne, HasRV64] in { def : PatGprGpr; def : Pat<(int_riscv_aes64ks1i GPR:$rs1, i32:$rnum), (AES64KS1I GPR:$rs1, rnum:$rnum)>; -} // Predicates = [HasStdExtZkndOrZkne, IsRV64] +} // Predicates = [HasStdExtZkndOrZkne, HasRV64] // Zkne -let Predicates = [HasStdExtZkne, IsRV32] in { +let Predicates = [HasStdExtZkne, HasRV32] in { def : PatGprGprByteSelect; def : PatGprGprByteSelect; -} // Predicates = [HasStdExtZkne, IsRV32] +} // Predicates = [HasStdExtZkne, HasRV32] -let Predicates = [HasStdExtZkne, IsRV64] in { +let Predicates = [HasStdExtZkne, HasRV64] in { def : PatGprGpr; def : PatGprGpr; -} // Predicates = [HasStdExtZkne, IsRV64] +} // Predicates = [HasStdExtZkne, HasRV64] // Zknh let Predicates = [HasStdExtZknh] in { @@ -174,21 +174,21 @@ def : PatGpr; } // Predicates = [HasStdExtZknh] -let Predicates = [HasStdExtZknh, IsRV32] in { +let Predicates = [HasStdExtZknh, HasRV32] in { def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; -} // Predicates = [HasStdExtZknh, IsRV32] +} // Predicates = [HasStdExtZknh, HasRV32] -let Predicates = [HasStdExtZknh, IsRV64] in { +let Predicates = [HasStdExtZknh, HasRV64] in { def : PatGpr; def : PatGpr; def : PatGpr; def : PatGpr; -} // Predicates = [HasStdExtZknh, IsRV64] +} // Predicates = [HasStdExtZknh, HasRV64] // Zksed let Predicates = [HasStdExtZksed] in {