diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4550,6 +4550,10 @@ HelpText<"Print supported cpu models for the given target (if target is not specified," " it will print the supported cpus for the default target)">, MarshallingInfoFlag>; +def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">, + Group, Flags<[CC1Option, CoreOption]>, + HelpText<"Print supported extensions for RISC-V">, + MarshallingInfoFlag>; def : Flag<["-"], "mcpu=help">, Alias; def : Flag<["-"], "mtune=help">, Alias; def time : Flag<["-"], "time">, diff --git a/clang/include/clang/Frontend/FrontendOptions.h b/clang/include/clang/Frontend/FrontendOptions.h --- a/clang/include/clang/Frontend/FrontendOptions.h +++ b/clang/include/clang/Frontend/FrontendOptions.h @@ -283,6 +283,9 @@ /// print the supported cpus for the current target unsigned PrintSupportedCPUs : 1; + /// Print the supported extensions for the current target. + unsigned PrintSupportedExtensions : 1; + /// Show the -version text. unsigned ShowVersion : 1; diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -2121,7 +2121,8 @@ if (C.getArgs().hasArg(options::OPT_v) || C.getArgs().hasArg(options::OPT__HASH_HASH_HASH) || - C.getArgs().hasArg(options::OPT_print_supported_cpus)) { + C.getArgs().hasArg(options::OPT_print_supported_cpus) || + C.getArgs().hasArg(options::OPT_print_supported_extensions)) { PrintVersion(C, llvm::errs()); SuppressMissingInputWarning = true; } @@ -4300,16 +4301,31 @@ C.MakeAction(MergerInputs, types::TY_Image)); } - // If --print-supported-cpus, -mcpu=? or -mtune=? is specified, build a custom - // Compile phase that prints out supported cpu models and quits. - if (Arg *A = Args.getLastArg(options::OPT_print_supported_cpus)) { - // Use the -mcpu=? flag as the dummy input to cc1. - Actions.clear(); - Action *InputAc = C.MakeAction(*A, types::TY_C); - Actions.push_back( - C.MakeAction(InputAc, types::TY_Nothing)); - for (auto &I : Inputs) - I.second->claim(); + for (auto Opt : {options::OPT_print_supported_cpus, + options::OPT_print_supported_extensions}) { + // If --print-supported-cpus, -mcpu=? or -mtune=? is specified, build a custom + // Compile phase that prints out supported cpu models and quits. + // + // If --print-supported-extensions is specified, call the helper function + // RISCVMarchHelp in RISCVISAInfo.cpp that prints out supported extensions + // and quits. + if (Arg *A = Args.getLastArg(Opt)) { + if (Opt == options::OPT_print_supported_extensions && + !C.getDefaultToolChain().getTriple().isRISCV()) { + C.getDriver().Diag(diag::err_opt_not_valid_on_target) + << "--print-supported-extensions"; + return; + } + + // Use the -mcpu=? flag as the dummy input to cc1. + Actions.clear(); + Action *InputAc = C.MakeAction(*A, types::TY_C); + Actions.push_back( + C.MakeAction(InputAc, types::TY_Nothing)); + for (auto &I : Inputs) + I.second->claim(); + } + } // Call validator for dxil when -Vd not in Args. diff --git a/clang/test/Driver/print-supported-extensions.c b/clang/test/Driver/print-supported-extensions.c new file mode 100644 --- /dev/null +++ b/clang/test/Driver/print-supported-extensions.c @@ -0,0 +1,122 @@ +/// Test that --print-supported-extensions lists supported extensions. + +// REQUIRES: riscv-registered-target + +// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \ +// RUN: FileCheck --implicit-check-not=warning: --strict-whitespace --match-full-lines %s + +// CHECK:Target: riscv64 +// CHECK:All available -march extensions for RISC-V +// CHECK: Name Version +// CHECK-NEXT: i 2.1 +// CHECK-NEXT: e 2.0 +// CHECK-NEXT: m 2.0 +// CHECK-NEXT: a 2.1 +// CHECK-NEXT: f 2.2 +// CHECK-NEXT: d 2.2 +// CHECK-NEXT: c 2.0 +// CHECK-NEXT: v 1.0 +// CHECK-NEXT: h 1.0 +// CHECK-NEXT: zicbom 1.0 +// CHECK-NEXT: zicbop 1.0 +// CHECK-NEXT: zicboz 1.0 +// CHECK-NEXT: zicntr 1.0 +// CHECK-NEXT: zicsr 2.0 +// CHECK-NEXT: zifencei 2.0 +// CHECK-NEXT: zihintpause 2.0 +// CHECK-NEXT: zihpm 1.0 +// CHECK-NEXT: zmmul 1.0 +// CHECK-NEXT: zawrs 1.0 +// CHECK-NEXT: zfh 1.0 +// CHECK-NEXT: zfhmin 1.0 +// CHECK-NEXT: zfinx 1.0 +// CHECK-NEXT: zdinx 1.0 +// CHECK-NEXT: zca 1.0 +// CHECK-NEXT: zcb 1.0 +// CHECK-NEXT: zcd 1.0 +// CHECK-NEXT: zcf 1.0 +// CHECK-NEXT: zcmp 1.0 +// CHECK-NEXT: zcmt 1.0 +// CHECK-NEXT: zba 1.0 +// CHECK-NEXT: zbb 1.0 +// CHECK-NEXT: zbc 1.0 +// CHECK-NEXT: zbkb 1.0 +// CHECK-NEXT: zbkc 1.0 +// CHECK-NEXT: zbkx 1.0 +// CHECK-NEXT: zbs 1.0 +// CHECK-NEXT: zk 1.0 +// CHECK-NEXT: zkn 1.0 +// CHECK-NEXT: zknd 1.0 +// CHECK-NEXT: zkne 1.0 +// CHECK-NEXT: zknh 1.0 +// CHECK-NEXT: zkr 1.0 +// CHECK-NEXT: zks 1.0 +// CHECK-NEXT: zksed 1.0 +// CHECK-NEXT: zksh 1.0 +// CHECK-NEXT: zkt 1.0 +// CHECK-NEXT: zve32f 1.0 +// CHECK-NEXT: zve32x 1.0 +// CHECK-NEXT: zve64d 1.0 +// CHECK-NEXT: zve64f 1.0 +// CHECK-NEXT: zve64x 1.0 +// CHECK-NEXT: zvl1024b 1.0 +// CHECK-NEXT: zvl128b 1.0 +// CHECK-NEXT: zvl16384b 1.0 +// CHECK-NEXT: zvl2048b 1.0 +// CHECK-NEXT: zvl256b 1.0 +// CHECK-NEXT: zvl32768b 1.0 +// CHECK-NEXT: zvl32b 1.0 +// CHECK-NEXT: zvl4096b 1.0 +// CHECK-NEXT: zvl512b 1.0 +// CHECK-NEXT: zvl64b 1.0 +// CHECK-NEXT: zvl65536b 1.0 +// CHECK-NEXT: zvl8192b 1.0 +// CHECK-NEXT: zhinx 1.0 +// CHECK-NEXT: zhinxmin 1.0 +// CHECK-NEXT: svinval 1.0 +// CHECK-NEXT: svnapot 1.0 +// CHECK-NEXT: svpbmt 1.0 +// CHECK-NEXT: xsfcie 1.0 +// CHECK-NEXT: xsfvcp 1.0 +// CHECK-NEXT: xtheadba 1.0 +// CHECK-NEXT: xtheadbb 1.0 +// CHECK-NEXT: xtheadbs 1.0 +// CHECK-NEXT: xtheadcmo 1.0 +// CHECK-NEXT: xtheadcondmov 1.0 +// CHECK-NEXT: xtheadfmemidx 1.0 +// CHECK-NEXT: xtheadmac 1.0 +// CHECK-NEXT: xtheadmemidx 1.0 +// CHECK-NEXT: xtheadmempair 1.0 +// CHECK-NEXT: xtheadsync 1.0 +// CHECK-NEXT: xtheadvdot 1.0 +// CHECK-NEXT: xventanacondops 1.0 +// +// CHECK:Experimental extensions +// CHECK-NEXT: zicond 1.0 +// CHECK-NEXT: zihintntl 0.2 +// CHECK-NEXT: zfa 0.2 +// CHECK-NEXT: zfbfmin 0.6 +// CHECK-NEXT: ztso 0.1 +// CHECK-NEXT: zvbb 1.0 +// CHECK-NEXT: zvbc 1.0 +// CHECK-NEXT: zvfbfmin 0.6 +// CHECK-NEXT: zvfbfwma 0.6 +// CHECK-NEXT: zvfh 0.1 +// CHECK-NEXT: zvkg 1.0 +// CHECK-NEXT: zvkn 1.0 +// CHECK-NEXT: zvknc 1.0 +// CHECK-NEXT: zvkned 1.0 +// CHECK-NEXT: zvkng 1.0 +// CHECK-NEXT: zvknha 1.0 +// CHECK-NEXT: zvknhb 1.0 +// CHECK-NEXT: zvks 1.0 +// CHECK-NEXT: zvksc 1.0 +// CHECK-NEXT: zvksed 1.0 +// CHECK-NEXT: zvksg 1.0 +// CHECK-NEXT: zvksh 1.0 +// CHECK-NEXT: zvkt 1.0 +// CHECK-NEXT: smaia 1.0 +// CHECK-NEXT: ssaia 1.0 +// +// CHECK:Use -march to specify the target's extension. +// CHECK-NEXT:For example, clang -march=rv32i_v1p0 diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp --- a/clang/tools/driver/cc1_main.cpp +++ b/clang/tools/driver/cc1_main.cpp @@ -38,6 +38,7 @@ #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" +#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/Signals.h" #include "llvm/Support/TargetSelect.h" #include "llvm/Support/TimeProfiler.h" @@ -182,6 +183,12 @@ return 0; } +/// Print supported extensions of the RISCV target. +static void printSupportedExtensions() { + llvm::riscvExtensionsHelp(); +} + + int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) { ensureSufficientStack(); @@ -221,6 +228,10 @@ if (Clang->getFrontendOpts().PrintSupportedCPUs) return PrintSupportedCPUs(Clang->getTargetOpts().Triple); + // --print-supported-extensions takes priority over the actual compilation. + if (Clang->getFrontendOpts().PrintSupportedExtensions) + return printSupportedExtensions(), 0; + // Infer the builtin include path if unspecified. if (Clang->getHeaderSearchOpts().UseBuiltinIncludes && Clang->getHeaderSearchOpts().ResourceDir.empty()) diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -22,6 +22,8 @@ unsigned MinorVersion; }; +void riscvExtensionsHelp(); + class RISCVISAInfo { public: RISCVISAInfo(const RISCVISAInfo &) = delete; diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -198,6 +198,29 @@ #endif } +void llvm::riscvExtensionsHelp() { + outs() << "All available -march extensions for RISC-V\n\n"; + outs() << '\t' << left_justify("Name", 20) << "Version\n"; + + RISCVISAInfo::OrderedExtensionMap ExtMap; + for (const auto &E : SupportedExtensions) + ExtMap[E.Name] = { E.Version.Major, E.Version.Minor }; + for (const auto &E : ExtMap) + outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion, + E.second.MinorVersion); + + outs() << "\nExperimental extensions\n"; + ExtMap.clear(); + for (const auto &E : SupportedExperimentalExtensions) + ExtMap[E.Name] = { E.Version.Major, E.Version.Minor }; + for (const auto &E : ExtMap) + outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion, + E.second.MinorVersion); + + outs() << "\nUse -march to specify the target's extension.\n" + "For example, clang -march=rv32i_v1p0\n"; +} + static bool stripExperimentalPrefix(StringRef &Ext) { return Ext.consume_front("experimental-"); }