Index: llvm/lib/Target/X86/X86InstrCompiler.td =================================================================== --- llvm/lib/Target/X86/X86InstrCompiler.td +++ llvm/lib/Target/X86/X86InstrCompiler.td @@ -896,15 +896,15 @@ multiclass ATOMIC_LOGIC_OP_RM Opc8, string s> { let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, SchedRW = [WriteBitTestSetRegRMW] in { - def 16rm : Ii8("x86_rm_" # s) addr:$src1, GR16:$src2))]>, OpSize16, TB, LOCK; - def 32rm : Ii8("x86_rm_" # s) addr:$src1, GR32:$src2))]>, OpSize32, TB, LOCK; - def 64rm : RIi8("x86_rm_" # s) addr:$src1, GR64:$src2))]>, TB, LOCK; Index: llvm/test/CodeGen/X86/pr61384.ll =================================================================== --- llvm/test/CodeGen/X86/pr61384.ll +++ llvm/test/CodeGen/X86/pr61384.ll @@ -8,7 +8,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: lock btsq %rax, a(%rip) # encoding: [0xf0,0x48,0x0f,0xab,0x05,A,A,A,A] -; CHECK-NEXT: # fixup A - offset: 5, value: a-5, kind: reloc_riprel_4byte +; CHECK-NEXT: # fixup A - offset: 5, value: a-4, kind: reloc_riprel_4byte ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] entry: