[X86][FP16] Combine bitcast(extract_vector_elt vXi16, N) to extract_vector_elt(bitcast(vXi16), N)

[pengfei]

Summary

Found the problem while implementing D145867.

[RKSimon]

LGTM

[skan]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

 
       unsigned NumConcats = 8 / SrcVT.getVectorNumElements();
       SmallVector<SDValue, 4> Ops(NumConcats, DAG.getUNDEF(SrcVT));
       Ops[0] = N0;
       N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
       N0 = DAG.getBitcast(MVT::i8, N0);
       return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
     }
+
+    // Combine bitcast(extract_vector_elt vXi16, N) to
+    //         extract_vector_elt(bitcast(vXi16), N).
+    if (VT == MVT::f16 && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+      SDValue N00 = N0.getOperand(0);
+      EVT NVT = N00.getValueType().changeVectorElementType(MVT::f16);
+      return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f16,
+                         DAG.getBitcast(NVT, N00), N0.getOperand(1));
+    }
   } else {
     // If we're bitcasting from iX to vXi1, see if the integer originally
     // began as a vXi1 and whether we can remove the bitcast entirely.
     if (VT.isVector() && VT.getScalarType() == MVT::i1 &&
         SrcVT.isScalarInteger() && TLI.isTypeLegal(VT)) {
       if (SDValue V =
               combineBitcastToBoolVector(VT, N0, SDLoc(N), DAG, Subtarget))
         return V;

llvm/test/CodeGen/X86/half.ll

 }
 
 declare half @llvm.minnum.f16(half, half)
 
 define half @pr61271(half %0, half %1) #0 {
 ; CHECK-LIBCALL-LABEL: pr61271:
 ; CHECK-LIBCALL:       # %bb.0:
 ; CHECK-LIBCALL-NEXT:    pminsw %xmm1, %xmm0
-; CHECK-LIBCALL-NEXT:    movd %xmm0, %eax
-; CHECK-LIBCALL-NEXT:    pinsrw $0, %eax, %xmm0
 ; CHECK-LIBCALL-NEXT:    retq
 ;
 ; BWON-F16C-LABEL: pr61271:
 ; BWON-F16C:       # %bb.0:
 ; BWON-F16C-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
-; BWON-F16C-NEXT:    vmovd %xmm0, %eax
-; BWON-F16C-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
 ; BWON-F16C-NEXT:    retq
 ;
 ; CHECK-I686-LABEL: pr61271:
 ; CHECK-I686:       # %bb.0:
-; CHECK-I686-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
 ; CHECK-I686-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm1
-; CHECK-I686-NEXT:    pminsw %xmm0, %xmm1
-; CHECK-I686-NEXT:    movd %xmm1, %eax
-; CHECK-I686-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK-I686-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; CHECK-I686-NEXT:    pminsw %xmm1, %xmm0
 ; CHECK-I686-NEXT:    retl
   %3 = call fast half @llvm.minnum.f16(half %0, half %1)
   ret half %3
 }
 
 declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>)
 
 define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 {