diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6731,13 +6731,27 @@ ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset)) return N1; - // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { SDValue N0Op0 = N0.getOperand(0); + EVT SrcVT = N0Op0.getValueType(); + unsigned SrcBitWidth = SrcVT.getScalarSizeInBits(); APInt Mask = ~N1C->getAPIntValue(); - Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits()); + Mask = Mask.trunc(SrcBitWidth); + + // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. if (DAG.MaskedValueIsZero(N0Op0, Mask)) - return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N0.getValueType(), N0Op0); + return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0Op0); + + // fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) if profitable. + if (N1C->getAPIntValue().countLeadingZeros() >= (BitWidth - SrcBitWidth) && + TLI.isTruncateFree(VT, SrcVT) && TLI.isZExtFree(SrcVT, VT) && + TLI.isTypeDesirableForOp(ISD::AND, SrcVT) && + TLI.isNarrowingProfitable(VT, SrcVT)) { + SDLoc DL(N); + return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, + DAG.getNode(ISD::AND, DL, SrcVT, N0Op0, + DAG.getZExtOrTrunc(N1, DL, SrcVT))); + } } // fold (and (ext (and V, c1)), c2) -> (and (ext V), (and c1, (ext c2))) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -4706,7 +4706,7 @@ ; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v4 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3 -; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: s_waitcnt expcnt(0) @@ -4901,7 +4901,7 @@ ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 ; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v6 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3 -; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: s_waitcnt expcnt(0) @@ -5116,7 +5116,7 @@ ; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v4 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3 -; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: s_waitcnt expcnt(0) @@ -5353,7 +5353,7 @@ ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 ; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v4 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 15, v2 -; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 +; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: s_waitcnt expcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll --- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll @@ -5129,27 +5129,27 @@ ; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1 ; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s7, 0xffff -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s7, 16 -; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s6, 0xffff -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7 -; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s5, 0xffff -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s5, s5, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s7, 16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s6, 16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s9, s5, 16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 -; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s4, 0xffff -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6 -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s4, 16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10 +; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32 ; GCN-NOHSA-VI-NEXT: s_nop 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; GCN-NOHSA-VI-NEXT: s_nop 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NOHSA-VI-NEXT: s_endpgm ; @@ -5555,47 +5555,47 @@ ; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1 ; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NOHSA-VI-NEXT: s_and_b32 s19, s9, 0xffff -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s9, s9, 16 -; GCN-NOHSA-VI-NEXT: s_and_b32 s18, s8, 0xffff -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s8, 16 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s19 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9 -; GCN-NOHSA-VI-NEXT: s_and_b32 s17, s11, 0xffff -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s11, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s19, s9, 16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s8, 16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s17, s11, 16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 -; GCN-NOHSA-VI-NEXT: s_and_b32 s16, s10, 0xffff -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8 -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s10, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s10, 16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s18 +; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64 -; GCN-NOHSA-VI-NEXT: s_and_b32 s15, s7, 0xffff -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s17 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11 -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s7, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s15, s7, 16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s17 +; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112 -; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s6, 0xffff -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10 -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s6, 16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s16 +; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96 -; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s5, 0xffff -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s15 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7 -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s5, s5, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s13, s5, 16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15 +; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 -; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s4, 0xffff -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6 -; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s4, 16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14 +; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32 ; GCN-NOHSA-VI-NEXT: s_nop 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s13 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; GCN-NOHSA-VI-NEXT: s_nop 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NOHSA-VI-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll --- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll @@ -6113,20 +6113,20 @@ ; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, v17 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, v17 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, v17 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0) -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v3 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v0 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v3 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v1 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v0 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v2 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v1 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v14, 16, v2 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v2 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16 @@ -6616,49 +6616,48 @@ ; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v28, 0 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v31, 0 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, 0 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v23, 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v25, 0 ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1) -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v3 +; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v0 ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0) -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, 0xffff, v4 -; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v30, 16, v4 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, 0 -; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, 0xffff, v6 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v22, 16, v6 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v3, 0xffff, v5 -; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, 0 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v29, v4 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, 0xffff, v6 +; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v26, 16, v7 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, 0xffff, v7 +; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v6, 16, v4 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v29, 16, v5 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v27, 0xffff, v5 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v0 -; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v0 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v1 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v14, 16, v1 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v2 -; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, 0xffff, v7 -; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v26, 16, v7 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v25, v4 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v21, v4 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, v4 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, v4 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, v4 -; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, v4 -; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:80 -; GCN-NOHSA-VI-NEXT: s_nop 0 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v1 +; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v18, 16, v2 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v2 +; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v3 +; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v3 +; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[27:30], off, s[0:3], 0 offset:80 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, 0 -; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:64 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:112 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:96 -; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48 -; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32 +; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 +; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:32 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:16 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 ; GCN-NOHSA-VI-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -112,53 +112,53 @@ ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 7, v0 +; GFX900-NEXT: v_and_b32_e32 v18, 0xffff8000, v0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0 -; GFX900-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 -; GFX900-NEXT: v_mov_b32_e32 v4, s35 -; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v0 +; GFX900-NEXT: v_mov_b32_e32 v0, s35 +; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v18 +; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2] -; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX900-NEXT: s_movk_i32 s1, 0x2000 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc -; GFX900-NEXT: s_movk_i32 s1, 0x2000 -; GFX900-NEXT: global_load_dwordx2 v[5:6], v[0:1], off -; GFX900-NEXT: global_load_dwordx2 v[7:8], v[0:1], off offset:2048 -; GFX900-NEXT: v_add_co_u32_e32 v9, vcc, s1, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[11:12], v[9:10], off offset:-4096 +; GFX900-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX900-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:2048 +; GFX900-NEXT: v_add_co_u32_e32 v6, vcc, s1, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dwordx2 v[8:9], v[6:7], off offset:-4096 ; GFX900-NEXT: s_movk_i32 s0, 0x1000 -; GFX900-NEXT: v_add_co_u32_e32 v13, vcc, s0, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[15:16], v[13:14], off offset:2048 -; GFX900-NEXT: global_load_dwordx2 v[17:18], v[9:10], off -; GFX900-NEXT: global_load_dwordx2 v[19:20], v[9:10], off offset:2048 +; GFX900-NEXT: v_add_co_u32_e32 v10, vcc, s0, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048 +; GFX900-NEXT: global_load_dwordx2 v[14:15], v[6:7], off +; GFX900-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048 ; GFX900-NEXT: s_movk_i32 s0, 0x3000 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[9:10], v[0:1], off -; GFX900-NEXT: global_load_dwordx2 v[13:14], v[0:1], off offset:2048 +; GFX900-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX900-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 ; GFX900-NEXT: s_waitcnt vmcnt(6) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v7, v5 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v6, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v4, v2 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v3, vcc ; GFX900-NEXT: s_waitcnt vmcnt(5) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v11, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v12, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(4) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v15, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v16, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v12, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v13, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(3) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v17, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v18, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v14, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v15, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(2) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v19, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v20, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v16, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v17, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(1) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v9, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v10, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v6, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v13, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v14, v1, vcc -; GFX900-NEXT: global_store_dwordx2 v[3:4], v[0:1], off +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc +; GFX900-NEXT: global_store_dwordx2 v18, v[0:1], s[34:35] ; GFX900-NEXT: s_endpgm ; ; GFX10-LABEL: clmem_read_simplified: @@ -184,54 +184,54 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 7, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff8000, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] -; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v20 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x1000 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v0, 0x2000 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x1000 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, 0x2000 ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off -; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off offset:-2048 -; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 +; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[12:13], v[4:5], off -; GFX10-NEXT: global_load_dwordx2 v[14:15], v[10:11], off offset:-2048 -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x3000 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: global_load_dwordx2 v[10:11], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[12:13], v[8:9], off offset:-2048 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x3000 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[16:17], v[10:11], off -; GFX10-NEXT: global_load_dwordx2 v[18:19], v[4:5], off offset:-2048 +; GFX10-NEXT: global_load_dwordx2 v[14:15], v[8:9], off +; GFX10-NEXT: global_load_dwordx2 v[16:17], v[2:3], off offset:-2048 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off -; GFX10-NEXT: global_load_dwordx2 v[20:21], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[18:19], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(6) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v6 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v7, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(5) +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo +; GFX10-NEXT: s_waitcnt vmcnt(4) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(4) +; GFX10-NEXT: s_waitcnt vmcnt(3) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(3) +; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v16, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v18, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v20, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v21, v1, vcc_lo -; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v18, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo +; GFX10-NEXT: global_store_dwordx2 v20, v[0:1], s[34:35] ; GFX10-NEXT: s_endpgm ; ; GFX90A-LABEL: clmem_read_simplified: @@ -256,53 +256,53 @@ ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX90A-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX90A-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX90A-NEXT: v_and_b32_e32 v18, 0xffff8000, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, s35 -; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 3, v[2:3] -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc +; GFX90A-NEXT: v_mov_b32_e32 v0, s35 +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s34, v18 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc +; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 3, v[2:3] +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc ; GFX90A-NEXT: s_movk_i32 s1, 0x2000 -; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[2:3], off -; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:2048 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, s1, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[8:9], off offset:-4096 +; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:2048 +; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, s1, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[6:7], off offset:-4096 ; GFX90A-NEXT: s_movk_i32 s0, 0x1000 -; GFX90A-NEXT: v_add_co_u32_e32 v12, vcc, s0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[12:13], off offset:2048 -; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[8:9], off -; GFX90A-NEXT: global_load_dwordx2 v[18:19], v[8:9], off offset:2048 +; GFX90A-NEXT: v_add_co_u32_e32 v10, vcc, s0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048 +; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[6:7], off +; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048 ; GFX90A-NEXT: s_movk_i32 s0, 0x3000 -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[2:3], off -; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[2:3], off offset:2048 +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 ; GFX90A-NEXT: s_waitcnt vmcnt(6) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v6, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v5, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v2 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v3, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(5) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v11, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(4) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v14, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v15, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v12, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v13, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(3) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v16, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v17, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v14, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v15, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(2) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v18, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v19, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v16, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v17, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(1) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v6, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v12, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v13, v3, vcc -; GFX90A-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc +; GFX90A-NEXT: global_store_dwordx2 v18, v[0:1], s[34:35] ; GFX90A-NEXT: s_endpgm ; ; GFX11-LABEL: clmem_read_simplified: @@ -319,61 +319,61 @@ ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 7, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX11-NEXT: v_and_b32_e32 v16, 0xffff8000, v2 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v16 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[4:5], v[0:1], off -; GFX11-NEXT: global_load_b64 v[6:7], v[0:1], off offset:2048 -; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, 0x2000 +; GFX11-NEXT: global_load_b64 v[2:3], v[0:1], off +; GFX11-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2048 +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0x2000 +; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x1000, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[12:13], v[8:9], off offset:-4096 -; GFX11-NEXT: global_load_b64 v[10:11], v[10:11], off offset:2048 -; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, 0x2000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: global_load_b64 v[8:9], v[8:9], off +; GFX11-NEXT: global_load_b64 v[10:11], v[6:7], off offset:-4096 +; GFX11-NEXT: global_load_b64 v[8:9], v[8:9], off offset:2048 +; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, 0x2000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: global_load_b64 v[6:7], v[6:7], off ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x3000, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x2 -; GFX11-NEXT: global_load_b64 v[14:15], v[14:15], off offset:2048 -; GFX11-NEXT: global_load_b64 v[16:17], v[0:1], off +; GFX11-NEXT: global_load_b64 v[12:13], v[12:13], off offset:2048 +; GFX11-NEXT: global_load_b64 v[14:15], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048 ; GFX11-NEXT: s_waitcnt vmcnt(6) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v6, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(5) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v12, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v13, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v10, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v11, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v10, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v8, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v6, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v14, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v15, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v12, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v13, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v16, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v17, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v14, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v15, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo -; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_store_b64 v16, v[0:1], s[34:35] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: @@ -440,7 +440,7 @@ ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX8-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX8-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 -; GFX8-NEXT: v_or_b32_e32 v1, v0, v1 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX8-NEXT: v_mov_b32_e32 v3, s35 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s34, v1 ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, v2, v3, vcc @@ -568,7 +568,7 @@ ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX900-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX900-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 -; GFX900-NEXT: v_or_b32_e32 v1, v0, v1 +; GFX900-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX900-NEXT: v_mov_b32_e32 v3, s35 ; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1 ; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v3, vcc @@ -689,7 +689,7 @@ ; GFX10-NEXT: s_movk_i32 s1, 0x7f ; GFX10-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX10-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 -; GFX10-NEXT: v_or_b32_e32 v1, v0, v1 +; GFX10-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34 ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1 @@ -800,7 +800,7 @@ ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX90A-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 3, v[2:3] -; GFX90A-NEXT: v_or_b32_e32 v1, v0, v2 +; GFX90A-NEXT: v_or_b32_e32 v1, v2, v0 ; GFX90A-NEXT: v_mov_b32_e32 v2, s35 ; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1 ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v2, vcc @@ -910,7 +910,7 @@ ; GFX11-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX11-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_or_b32_e32 v1, v0, v1 +; GFX11-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo @@ -1222,40 +1222,40 @@ ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 7, v0 +; GFX900-NEXT: v_and_b32_e32 v4, 0xffff8000, v0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0 -; GFX900-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 -; GFX900-NEXT: v_mov_b32_e32 v4, s35 -; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v0 +; GFX900-NEXT: v_mov_b32_e32 v0, s35 +; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v4 +; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 2, v[1:2] -; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc ; GFX900-NEXT: s_movk_i32 s0, 0x1000 -; GFX900-NEXT: v_add_co_u32_e32 v5, vcc, s0, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dword v2, v[0:1], off -; GFX900-NEXT: global_load_dword v7, v[0:1], off offset:1024 -; GFX900-NEXT: global_load_dword v8, v[0:1], off offset:2048 -; GFX900-NEXT: global_load_dword v9, v[0:1], off offset:3072 -; GFX900-NEXT: global_load_dword v10, v[5:6], off -; GFX900-NEXT: global_load_dword v11, v[5:6], off offset:1024 -; GFX900-NEXT: global_load_dword v12, v[5:6], off offset:2048 -; GFX900-NEXT: global_load_dword v13, v[5:6], off offset:3072 -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc ; GFX900-NEXT: global_load_dword v5, v[0:1], off ; GFX900-NEXT: global_load_dword v6, v[0:1], off offset:1024 +; GFX900-NEXT: global_load_dword v7, v[0:1], off offset:2048 +; GFX900-NEXT: global_load_dword v8, v[0:1], off offset:3072 +; GFX900-NEXT: global_load_dword v9, v[2:3], off +; GFX900-NEXT: global_load_dword v10, v[2:3], off offset:1024 +; GFX900-NEXT: global_load_dword v11, v[2:3], off offset:2048 +; GFX900-NEXT: global_load_dword v12, v[2:3], off offset:3072 +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dword v2, v[0:1], off +; GFX900-NEXT: global_load_dword v3, v[0:1], off offset:1024 ; GFX900-NEXT: s_waitcnt vmcnt(8) -; GFX900-NEXT: v_add_u32_e32 v0, v7, v2 +; GFX900-NEXT: v_add_u32_e32 v0, v6, v5 ; GFX900-NEXT: s_waitcnt vmcnt(6) -; GFX900-NEXT: v_add3_u32 v0, v8, v0, v9 +; GFX900-NEXT: v_add3_u32 v0, v7, v0, v8 ; GFX900-NEXT: s_waitcnt vmcnt(4) -; GFX900-NEXT: v_add3_u32 v0, v10, v0, v11 +; GFX900-NEXT: v_add3_u32 v0, v9, v0, v10 ; GFX900-NEXT: s_waitcnt vmcnt(2) -; GFX900-NEXT: v_add3_u32 v0, v12, v0, v13 +; GFX900-NEXT: v_add3_u32 v0, v11, v0, v12 ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_add3_u32 v0, v5, v0, v6 -; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: v_add3_u32 v0, v2, v0, v3 +; GFX900-NEXT: global_store_dword v4, v0, s[34:35] ; GFX900-NEXT: s_endpgm ; ; GFX10-LABEL: Address32: @@ -1281,48 +1281,48 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 7, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff8000, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] -; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v8 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x800, v0 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x800, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x1000 ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0x1000 -; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, 0x1000, v0 +; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x1000, v0 ; GFX10-NEXT: s_clause 0x4 -; GFX10-NEXT: global_load_dword v10, v[0:1], off -; GFX10-NEXT: global_load_dword v11, v[0:1], off offset:1024 -; GFX10-NEXT: global_load_dword v12, v[4:5], off offset:1024 -; GFX10-NEXT: global_load_dword v13, v[6:7], off offset:-2048 -; GFX10-NEXT: global_load_dword v14, v[6:7], off -; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x1800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0x2000 +; GFX10-NEXT: global_load_dword v9, v[0:1], off +; GFX10-NEXT: global_load_dword v10, v[0:1], off offset:1024 +; GFX10-NEXT: global_load_dword v11, v[2:3], off offset:1024 +; GFX10-NEXT: global_load_dword v12, v[4:5], off offset:-2048 +; GFX10-NEXT: global_load_dword v13, v[4:5], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x1800, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x2000 +; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dword v15, v[8:9], off offset:1024 -; GFX10-NEXT: global_load_dword v16, v[4:5], off offset:1024 +; GFX10-NEXT: global_load_dword v14, v[6:7], off offset:1024 +; GFX10-NEXT: global_load_dword v15, v[2:3], off offset:1024 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x2 -; GFX10-NEXT: global_load_dword v4, v[6:7], off offset:-2048 -; GFX10-NEXT: global_load_dword v5, v[6:7], off -; GFX10-NEXT: global_load_dword v8, v[0:1], off offset:1024 +; GFX10-NEXT: global_load_dword v2, v[4:5], off offset:-2048 +; GFX10-NEXT: global_load_dword v3, v[4:5], off +; GFX10-NEXT: global_load_dword v6, v[0:1], off offset:1024 ; GFX10-NEXT: s_waitcnt vmcnt(8) -; GFX10-NEXT: v_add_nc_u32_e32 v0, v11, v10 +; GFX10-NEXT: v_add_nc_u32_e32 v0, v10, v9 ; GFX10-NEXT: s_waitcnt vmcnt(6) -; GFX10-NEXT: v_add3_u32 v0, v13, v0, v12 +; GFX10-NEXT: v_add3_u32 v0, v12, v0, v11 ; GFX10-NEXT: s_waitcnt vmcnt(4) -; GFX10-NEXT: v_add3_u32 v0, v14, v0, v15 +; GFX10-NEXT: v_add3_u32 v0, v13, v0, v14 ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_add3_u32 v0, v4, v0, v16 +; GFX10-NEXT: v_add3_u32 v0, v2, v0, v15 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add3_u32 v0, v5, v0, v8 -; GFX10-NEXT: global_store_dword v[2:3], v0, off +; GFX10-NEXT: v_add3_u32 v0, v3, v0, v6 +; GFX10-NEXT: global_store_dword v8, v0, s[34:35] ; GFX10-NEXT: s_endpgm ; ; GFX90A-LABEL: Address32: @@ -1347,40 +1347,40 @@ ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX90A-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX90A-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX90A-NEXT: v_and_b32_e32 v4, 0xffff8000, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, s35 -; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3] -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc +; GFX90A-NEXT: v_mov_b32_e32 v0, s35 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, s34, v4 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v0, vcc +; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 2, v[2:3] +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v5, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v1, vcc ; GFX90A-NEXT: s_movk_i32 s0, 0x1000 -; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dword v6, v[2:3], off -; GFX90A-NEXT: global_load_dword v7, v[2:3], off offset:1024 -; GFX90A-NEXT: global_load_dword v8, v[2:3], off offset:2048 -; GFX90A-NEXT: global_load_dword v9, v[2:3], off offset:3072 -; GFX90A-NEXT: global_load_dword v10, v[4:5], off -; GFX90A-NEXT: global_load_dword v11, v[4:5], off offset:1024 -; GFX90A-NEXT: global_load_dword v12, v[4:5], off offset:2048 -; GFX90A-NEXT: global_load_dword v13, v[4:5], off offset:3072 -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x2000, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dword v4, v[2:3], off -; GFX90A-NEXT: global_load_dword v5, v[2:3], off offset:1024 +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dword v5, v[0:1], off +; GFX90A-NEXT: global_load_dword v6, v[0:1], off offset:1024 +; GFX90A-NEXT: global_load_dword v7, v[0:1], off offset:2048 +; GFX90A-NEXT: global_load_dword v8, v[0:1], off offset:3072 +; GFX90A-NEXT: global_load_dword v9, v[2:3], off +; GFX90A-NEXT: global_load_dword v10, v[2:3], off offset:1024 +; GFX90A-NEXT: global_load_dword v11, v[2:3], off offset:2048 +; GFX90A-NEXT: global_load_dword v12, v[2:3], off offset:3072 +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dword v2, v[0:1], off +; GFX90A-NEXT: global_load_dword v3, v[0:1], off offset:1024 ; GFX90A-NEXT: s_waitcnt vmcnt(8) -; GFX90A-NEXT: v_add_u32_e32 v2, v7, v6 +; GFX90A-NEXT: v_add_u32_e32 v0, v6, v5 ; GFX90A-NEXT: s_waitcnt vmcnt(6) -; GFX90A-NEXT: v_add3_u32 v2, v8, v2, v9 +; GFX90A-NEXT: v_add3_u32 v0, v7, v0, v8 ; GFX90A-NEXT: s_waitcnt vmcnt(4) -; GFX90A-NEXT: v_add3_u32 v2, v10, v2, v11 +; GFX90A-NEXT: v_add3_u32 v0, v9, v0, v10 ; GFX90A-NEXT: s_waitcnt vmcnt(2) -; GFX90A-NEXT: v_add3_u32 v2, v12, v2, v13 +; GFX90A-NEXT: v_add3_u32 v0, v11, v0, v12 ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_add3_u32 v2, v4, v2, v5 -; GFX90A-NEXT: global_store_dword v[0:1], v2, off +; GFX90A-NEXT: v_add3_u32 v0, v2, v0, v3 +; GFX90A-NEXT: global_store_dword v4, v0, s[34:35] ; GFX90A-NEXT: s_endpgm ; ; GFX11-LABEL: Address32: @@ -1397,46 +1397,46 @@ ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 7, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff8000, v2 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v6 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b32 v8, v[0:1], off -; GFX11-NEXT: global_load_b32 v9, v[0:1], off offset:1024 -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x1000, v0 +; GFX11-NEXT: global_load_b32 v7, v[0:1], off +; GFX11-NEXT: global_load_b32 v8, v[0:1], off offset:1024 +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x1000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x2000 ; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0x2000 -; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x5 -; GFX11-NEXT: global_load_b32 v10, v[0:1], off offset:2048 -; GFX11-NEXT: global_load_b32 v11, v[0:1], off offset:3072 -; GFX11-NEXT: global_load_b32 v12, v[6:7], off offset:-4096 -; GFX11-NEXT: global_load_b32 v13, v[4:5], off offset:1024 -; GFX11-NEXT: global_load_b32 v14, v[4:5], off offset:2048 -; GFX11-NEXT: global_load_b32 v4, v[4:5], off offset:3072 +; GFX11-NEXT: global_load_b32 v9, v[0:1], off offset:2048 +; GFX11-NEXT: global_load_b32 v10, v[0:1], off offset:3072 +; GFX11-NEXT: global_load_b32 v11, v[4:5], off offset:-4096 +; GFX11-NEXT: global_load_b32 v12, v[2:3], off offset:1024 +; GFX11-NEXT: global_load_b32 v13, v[2:3], off offset:2048 +; GFX11-NEXT: global_load_b32 v2, v[2:3], off offset:3072 ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b32 v5, v[6:7], off +; GFX11-NEXT: global_load_b32 v3, v[4:5], off ; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:1024 ; GFX11-NEXT: s_waitcnt vmcnt(8) -; GFX11-NEXT: v_add_nc_u32_e32 v1, v9, v8 +; GFX11-NEXT: v_add_nc_u32_e32 v1, v8, v7 ; GFX11-NEXT: s_waitcnt vmcnt(6) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v1, v10, v1, v11 +; GFX11-NEXT: v_add3_u32 v1, v9, v1, v10 ; GFX11-NEXT: s_waitcnt vmcnt(4) -; GFX11-NEXT: v_add3_u32 v1, v12, v1, v13 +; GFX11-NEXT: v_add3_u32 v1, v11, v1, v12 ; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v1, v14, v1, v4 +; GFX11-NEXT: v_add3_u32 v1, v13, v1, v2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_add3_u32 v0, v5, v1, v0 -; GFX11-NEXT: global_store_b32 v[2:3], v0, off +; GFX11-NEXT: v_add3_u32 v0, v3, v1, v0 +; GFX11-NEXT: global_store_b32 v6, v0, s[34:35] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: @@ -1566,32 +1566,32 @@ ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 7, v0 +; GFX900-NEXT: v_and_b32_e32 v12, 0xffff8000, v0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0 -; GFX900-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 -; GFX900-NEXT: v_mov_b32_e32 v4, s35 -; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v0 +; GFX900-NEXT: v_mov_b32_e32 v0, s35 +; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v12 +; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2] -; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX900-NEXT: s_movk_i32 s0, 0xf000 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc -; GFX900-NEXT: v_add_co_u32_e32 v7, vcc, 0, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v8, vcc, 1, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[5:6], v[0:1], off -; GFX900-NEXT: global_load_dwordx2 v[9:10], v[7:8], off offset:-4096 -; GFX900-NEXT: s_movk_i32 s0, 0xf000 +; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, 0, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 1, v1, vcc +; GFX900-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX900-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:-4096 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[11:12], v[7:8], off -; GFX900-NEXT: global_load_dwordx2 v[13:14], v[0:1], off offset:2048 +; GFX900-NEXT: global_load_dwordx2 v[8:9], v[4:5], off +; GFX900-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 ; GFX900-NEXT: s_waitcnt vmcnt(2) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v9, v5 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v10, v6, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v3, vcc ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v13, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v14, v1, vcc -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v11, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v12, v1, vcc -; GFX900-NEXT: global_store_dwordx2 v[3:4], v[0:1], off +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc +; GFX900-NEXT: global_store_dwordx2 v12, v[0:1], s[34:35] ; GFX900-NEXT: s_endpgm ; ; GFX10-LABEL: Offset64: @@ -1617,32 +1617,32 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 7, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff8000, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] -; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v12 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0xfffff800 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0xfffff800 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off -; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off offset:-2048 +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 1, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off -; GFX10-NEXT: global_load_dwordx2 v[12:13], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[10:11], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v6 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v7, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo -; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off +; GFX10-NEXT: global_store_dwordx2 v12, v[0:1], s[34:35] ; GFX10-NEXT: s_endpgm ; ; GFX90A-LABEL: Offset64: @@ -1667,32 +1667,32 @@ ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX90A-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX90A-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX90A-NEXT: v_and_b32_e32 v12, 0xffff8000, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, s35 -; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 3, v[2:3] -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, 0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 1, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[2:3], off -; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[6:7], off offset:-4096 +; GFX90A-NEXT: v_mov_b32_e32 v0, s35 +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s34, v12 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc +; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 3, v[2:3] +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 1, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:-4096 ; GFX90A-NEXT: s_movk_i32 s0, 0xf000 -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[6:7], off -; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[2:3], off offset:2048 +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[4:5], off +; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 ; GFX90A-NEXT: s_waitcnt vmcnt(2) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v8, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v5, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v3, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v12, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v13, v3, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v11, v3, vcc -; GFX90A-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc +; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[34:35] ; GFX90A-NEXT: s_endpgm ; ; GFX11-LABEL: Offset64: @@ -1709,35 +1709,35 @@ ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 7, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff8000, v2 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v8 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 1, v1, vcc_lo -; GFX11-NEXT: global_load_b64 v[4:5], v[0:1], off +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 1, v1, vcc_lo +; GFX11-NEXT: global_load_b64 v[2:3], v[0:1], off ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x2 -; GFX11-NEXT: global_load_b64 v[8:9], v[6:7], off offset:-4096 -; GFX11-NEXT: global_load_b64 v[6:7], v[6:7], off +; GFX11-NEXT: global_load_b64 v[6:7], v[4:5], off offset:-4096 +; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v8, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v6, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo -; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo +; GFX11-NEXT: global_store_b64 v8, v[0:1], s[34:35] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: @@ -1843,27 +1843,27 @@ ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 7, v0 +; GFX900-NEXT: v_and_b32_e32 v6, 0xffff8000, v0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0 -; GFX900-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 -; GFX900-NEXT: v_mov_b32_e32 v4, s35 -; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v0 +; GFX900-NEXT: v_mov_b32_e32 v0, s35 +; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v6 +; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 2, v[1:2] -; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc -; GFX900-NEXT: v_add_co_u32_e32 v5, vcc, 0x7ffff000, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc -; GFX900-NEXT: v_add_co_u32_e32 v7, vcc, 0x80000000, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dword v2, v[0:1], off -; GFX900-NEXT: global_load_dword v9, v[5:6], off offset:2048 -; GFX900-NEXT: global_load_dword v10, v[5:6], off offset:3072 -; GFX900-NEXT: global_load_dword v11, v[7:8], off +; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, 0x7ffff000, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, 0x80000000, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dword v7, v[0:1], off +; GFX900-NEXT: global_load_dword v8, v[2:3], off offset:2048 +; GFX900-NEXT: global_load_dword v9, v[2:3], off offset:3072 +; GFX900-NEXT: global_load_dword v10, v[4:5], off ; GFX900-NEXT: s_waitcnt vmcnt(2) -; GFX900-NEXT: v_add_u32_e32 v0, v9, v2 +; GFX900-NEXT: v_add_u32_e32 v0, v8, v7 ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_add3_u32 v0, v10, v0, v11 -; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: v_add3_u32 v0, v9, v0, v10 +; GFX900-NEXT: global_store_dword v6, v0, s[34:35] ; GFX900-NEXT: s_endpgm ; ; GFX10-LABEL: p32Offset64: @@ -1889,26 +1889,26 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 7, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff8000, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] -; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x80000000 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: global_load_dword v6, v[0:1], off +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x80000000 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: global_load_dword v5, v[0:1], off ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ffff800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x2 -; GFX10-NEXT: global_load_dword v7, v[4:5], off offset:-2048 -; GFX10-NEXT: global_load_dword v8, v[4:5], off -; GFX10-NEXT: global_load_dword v9, v[0:1], off offset:1024 +; GFX10-NEXT: global_load_dword v6, v[2:3], off offset:-2048 +; GFX10-NEXT: global_load_dword v7, v[2:3], off +; GFX10-NEXT: global_load_dword v8, v[0:1], off offset:1024 ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_add_nc_u32_e32 v0, v7, v6 +; GFX10-NEXT: v_add_nc_u32_e32 v0, v6, v5 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add3_u32 v0, v9, v0, v8 -; GFX10-NEXT: global_store_dword v[2:3], v0, off +; GFX10-NEXT: v_add3_u32 v0, v8, v0, v7 +; GFX10-NEXT: global_store_dword v4, v0, s[34:35] ; GFX10-NEXT: s_endpgm ; ; GFX90A-LABEL: p32Offset64: @@ -1933,27 +1933,27 @@ ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX90A-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX90A-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX90A-NEXT: v_and_b32_e32 v6, 0xffff8000, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, s35 -; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3] -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x7ffff000, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v3, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, 0x80000000, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dword v8, v[2:3], off -; GFX90A-NEXT: global_load_dword v9, v[4:5], off offset:2048 -; GFX90A-NEXT: global_load_dword v10, v[4:5], off offset:3072 -; GFX90A-NEXT: global_load_dword v11, v[6:7], off +; GFX90A-NEXT: v_mov_b32_e32 v0, s35 +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s34, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc +; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 2, v[2:3] +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x7ffff000, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x80000000, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dword v7, v[0:1], off +; GFX90A-NEXT: global_load_dword v8, v[2:3], off offset:2048 +; GFX90A-NEXT: global_load_dword v9, v[2:3], off offset:3072 +; GFX90A-NEXT: global_load_dword v10, v[4:5], off ; GFX90A-NEXT: s_waitcnt vmcnt(2) -; GFX90A-NEXT: v_add_u32_e32 v2, v9, v8 +; GFX90A-NEXT: v_add_u32_e32 v0, v8, v7 ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_add3_u32 v2, v10, v2, v11 -; GFX90A-NEXT: global_store_dword v[0:1], v2, off +; GFX90A-NEXT: v_add3_u32 v0, v9, v0, v10 +; GFX90A-NEXT: global_store_dword v6, v0, s[34:35] ; GFX90A-NEXT: s_endpgm ; ; GFX11-LABEL: p32Offset64: @@ -1970,30 +1970,30 @@ ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 7, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff8000, v2 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v6 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x7ffff000, v0 +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x7ffff000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x80000000, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, 0x80000000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off -; GFX11-NEXT: global_load_b32 v1, v[4:5], off offset:2048 -; GFX11-NEXT: global_load_b32 v4, v[4:5], off offset:3072 -; GFX11-NEXT: global_load_b32 v5, v[6:7], off +; GFX11-NEXT: global_load_b32 v1, v[2:3], off offset:2048 +; GFX11-NEXT: global_load_b32 v2, v[2:3], off offset:3072 +; GFX11-NEXT: global_load_b32 v3, v[4:5], off ; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: v_add_nc_u32_e32 v0, v1, v0 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add3_u32 v0, v4, v0, v5 -; GFX11-NEXT: global_store_b32 v[2:3], v0, off +; GFX11-NEXT: v_add3_u32 v0, v2, v0, v3 +; GFX11-NEXT: global_store_b32 v6, v0, s[34:35] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: @@ -2053,28 +2053,22 @@ ; GFX8-NEXT: v_mov_b32_e32 v3, s39 ; GFX8-NEXT: v_add_u32_e32 v12, vcc, s38, v2 ; GFX8-NEXT: v_addc_u32_e32 v13, vcc, 0, v3, vcc -; GFX8-NEXT: s_movk_i32 s0, 0x1000 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v0 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x1000, v0 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc -; GFX8-NEXT: s_movk_i32 s0, 0x1800 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, s0, v0 +; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x1800, v0 ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc -; GFX8-NEXT: s_movk_i32 s0, 0x2000 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, s0, v0 +; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x2000, v0 ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc -; GFX8-NEXT: s_movk_i32 s0, 0x2800 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, s0, v12 +; GFX8-NEXT: v_add_u32_e32 v8, vcc, 0x2800, v12 ; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3] ; GFX8-NEXT: flat_load_dwordx2 v[4:5], v[4:5] ; GFX8-NEXT: flat_load_dwordx2 v[6:7], v[6:7] ; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v13, vcc -; GFX8-NEXT: s_movk_i32 s0, 0x3000 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, s0, v12 +; GFX8-NEXT: v_add_u32_e32 v10, vcc, 0x3000, v12 ; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v13, vcc -; GFX8-NEXT: s_movk_i32 s0, 0x3800 ; GFX8-NEXT: flat_load_dwordx2 v[8:9], v[8:9] ; GFX8-NEXT: flat_load_dwordx2 v[10:11], v[10:11] -; GFX8-NEXT: v_add_u32_e32 v12, vcc, s0, v12 +; GFX8-NEXT: v_add_u32_e32 v12, vcc, 0x3800, v12 ; GFX8-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc ; GFX8-NEXT: flat_load_dwordx2 v[12:13], v[12:13] ; GFX8-NEXT: s_waitcnt vmcnt(4) @@ -2115,42 +2109,42 @@ ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff8000, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, s37 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s36, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v3, s39 -; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, s38, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v3, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0x2000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc -; GFX9-NEXT: global_load_dwordx2 v[6:7], v[2:3], off -; GFX9-NEXT: global_load_dwordx2 v[8:9], v[2:3], off offset:2048 -; GFX9-NEXT: global_load_dwordx2 v[10:11], v[4:5], off -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0x2000, v12 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v13, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0x3000, v12 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v13, vcc -; GFX9-NEXT: global_load_dwordx2 v[12:13], v[2:3], off offset:2048 -; GFX9-NEXT: global_load_dwordx2 v[14:15], v[4:5], off -; GFX9-NEXT: global_load_dwordx2 v[16:17], v[4:5], off offset:2048 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff8000, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s37 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s36, v16 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v0, s39 +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, s38, v16 +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0x2000, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off +; GFX9-NEXT: global_load_dwordx2 v[6:7], v[0:1], off offset:2048 +; GFX9-NEXT: global_load_dwordx2 v[8:9], v[2:3], off +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0x3000, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v11, vcc +; GFX9-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 +; GFX9-NEXT: global_load_dwordx2 v[12:13], v[2:3], off +; GFX9-NEXT: global_load_dwordx2 v[14:15], v[2:3], off offset:2048 ; GFX9-NEXT: s_waitcnt vmcnt(4) -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v5, vcc ; GFX9-NEXT: s_waitcnt vmcnt(3) -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v11, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc ; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v14, v12 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v15, v13, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v12, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v13, v11, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v16, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v17, v5, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc -; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v14, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v15, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_store_dwordx2 v16, v[0:1], s[36:37] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: DiffBase: @@ -2174,42 +2168,42 @@ ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v0 -; GFX10-NEXT: v_add_co_u32 v0, s0, s36, v2 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s37, 0, s0 -; GFX10-NEXT: v_add_co_u32 v14, s0, s38, v2 -; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, s39, 0, s0 -; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x1800 -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v14, 0x3000 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v15, vcc_lo +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff8000, v0 +; GFX10-NEXT: v_add_co_u32 v8, s0, s36, v16 +; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s0, s37, 0, s0 +; GFX10-NEXT: v_add_co_u32 v12, s0, s38, v16 +; GFX10-NEXT: v_add_co_ci_u32_e64 v13, s0, s39, 0, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, 0x1800 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v12, 0x3000 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v13, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 -; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off -; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:-2048 +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v8 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:-2048 -; GFX10-NEXT: global_load_dwordx2 v[12:13], v[4:5], off -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x3800, v14 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v15, vcc_lo +; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off offset:-2048 +; GFX10-NEXT: global_load_dwordx2 v[10:11], v[2:3], off +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x3800, v12 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v13, vcc_lo +; GFX10-NEXT: global_load_dwordx2 v[12:13], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[14:15], v[2:3], off -; GFX10-NEXT: global_load_dwordx2 v[16:17], v[4:5], off ; GFX10-NEXT: s_waitcnt vmcnt(4) -; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v8, v6 -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v7, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v12, v10 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v13, v11, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v10, v8 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v11, v9, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v14, v2 ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v15, v3, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v16, v4 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v17, v5, vcc_lo -; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo -; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_store_dwordx2 v16, v[0:1], s[36:37] ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: DiffBase: @@ -2225,44 +2219,44 @@ ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 7, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v0 -; GFX11-NEXT: v_add_co_u32 v0, s0, s36, v2 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff8000, v0 +; GFX11-NEXT: v_add_co_u32 v2, s0, s36, v12 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s37, 0, s0 -; GFX11-NEXT: v_add_co_u32 v10, s0, s38, v2 -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x1000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s37, 0, s0 +; GFX11-NEXT: v_add_co_u32 v8, s0, s38, v12 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, s39, 0, s0 -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x2000 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, 0x2000, v10 -; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo -; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, 0x3000, v10 -; GFX11-NEXT: global_load_b64 v[8:9], v[4:5], off offset:-4096 -; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo -; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off offset:2048 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, s39, 0, s0 +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0x2000 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x2000, v8 +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x3000, v8 +; GFX11-NEXT: global_load_b64 v[6:7], v[2:3], off offset:-4096 +; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048 ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[6:7], v[6:7], off offset:2048 -; GFX11-NEXT: global_load_b64 v[12:13], v[10:11], off -; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off -; GFX11-NEXT: global_load_b64 v[10:11], v[10:11], off offset:2048 +; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off offset:2048 +; GFX11-NEXT: global_load_b64 v[10:11], v[8:9], off +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off +; GFX11-NEXT: global_load_b64 v[8:9], v[8:9], off offset:2048 ; GFX11-NEXT: s_waitcnt vmcnt(4) -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v8 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v9, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v6 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v12, v6 -; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v13, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v10, v4 +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v10, v6 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v11, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v8, v4 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v5, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo -; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_store_b64 v12, v[0:1], s[36:37] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ptr addrspace(1) %buffer2) { @@ -2406,52 +2400,52 @@ ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 7, v0 +; GFX900-NEXT: v_and_b32_e32 v22, 0xffff8000, v0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0 -; GFX900-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 -; GFX900-NEXT: v_mov_b32_e32 v4, s35 -; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v0 +; GFX900-NEXT: v_mov_b32_e32 v0, s35 +; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v22 +; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2] -; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX900-NEXT: s_movk_i32 s0, 0x3000 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc -; GFX900-NEXT: s_movk_i32 s0, 0x3000 -; GFX900-NEXT: v_add_co_u32_e32 v7, vcc, s0, v0 -; GFX900-NEXT: global_load_dwordx2 v[5:6], v[0:1], off -; GFX900-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[9:10], v[7:8], off offset:2048 -; GFX900-NEXT: global_load_dwordx2 v[11:12], v[7:8], off +; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0 +; GFX900-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:2048 +; GFX900-NEXT: global_load_dwordx2 v[8:9], v[4:5], off ; GFX900-NEXT: s_movk_i32 s0, 0x2000 -; GFX900-NEXT: v_add_co_u32_e32 v7, vcc, s0, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[13:14], v[7:8], off offset:2048 +; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:2048 ; GFX900-NEXT: s_movk_i32 s0, 0x1000 -; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, s0, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v1, vcc -; GFX900-NEXT: global_load_dwordx2 v[17:18], v[15:16], off -; GFX900-NEXT: global_load_dwordx2 v[19:20], v[7:8], off -; GFX900-NEXT: global_load_dwordx2 v[21:22], v[15:16], off offset:2048 -; GFX900-NEXT: global_load_dwordx2 v[23:24], v[0:1], off offset:2048 +; GFX900-NEXT: v_add_co_u32_e32 v12, vcc, s0, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc +; GFX900-NEXT: global_load_dwordx2 v[14:15], v[12:13], off +; GFX900-NEXT: global_load_dwordx2 v[16:17], v[4:5], off +; GFX900-NEXT: global_load_dwordx2 v[18:19], v[12:13], off offset:2048 +; GFX900-NEXT: global_load_dwordx2 v[20:21], v[0:1], off offset:2048 ; GFX900-NEXT: s_waitcnt vmcnt(6) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v9, v5 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v10, v6, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v3, vcc ; GFX900-NEXT: s_waitcnt vmcnt(5) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v11, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v12, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(4) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v13, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v14, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(2) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v19, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v20, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v16, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v17, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(1) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v21, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v22, v1, vcc -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v17, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v18, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v18, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v19, v1, vcc +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v14, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v15, v1, vcc ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v23, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v24, v1, vcc -; GFX900-NEXT: global_store_dwordx2 v[3:4], v[0:1], off +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v20, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v21, v1, vcc +; GFX900-NEXT: global_store_dwordx2 v22, v[0:1], s[34:35] ; GFX900-NEXT: s_endpgm ; ; GFX10-LABEL: ReverseOrder: @@ -2477,58 +2471,58 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 7, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff8000, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] -; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v20 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x3800, v0 +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x3800, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x3000, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x3000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[8:9], v[0:1], off -; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x2800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v14, vcc_lo, 0x1800, v0 +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x2800, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, 0x2000, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, 0x1800, v0 ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[6:7], off -; GFX10-NEXT: global_load_dwordx2 v[12:13], v[12:13], off +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[4:5], off +; GFX10-NEXT: global_load_dwordx2 v[10:11], v[10:11], off +; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v14, vcc_lo, 0x1000, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v16, vcc_lo, 0x1000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[14:15], v[14:15], off -; GFX10-NEXT: global_load_dwordx2 v[4:5], v[4:5], off +; GFX10-NEXT: global_load_dwordx2 v[12:13], v[12:13], off +; GFX10-NEXT: global_load_dwordx2 v[2:3], v[2:3], off ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[18:19], v[16:17], off -; GFX10-NEXT: global_load_dwordx2 v[20:21], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[16:17], v[14:15], off +; GFX10-NEXT: global_load_dwordx2 v[18:19], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(6) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v8 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v9, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v6 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v7, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(5) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo +; GFX10-NEXT: s_waitcnt vmcnt(2) +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v16, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v18, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v20, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v21, v1, vcc_lo -; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off +; GFX10-NEXT: global_store_dwordx2 v20, v[0:1], s[34:35] ; GFX10-NEXT: s_endpgm ; ; GFX90A-LABEL: ReverseOrder: @@ -2553,52 +2547,52 @@ ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX90A-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX90A-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX90A-NEXT: v_and_b32_e32 v22, 0xffff8000, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, s35 -; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 3, v[2:3] -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc +; GFX90A-NEXT: v_mov_b32_e32 v0, s35 +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s34, v22 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc +; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 3, v[2:3] +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc ; GFX90A-NEXT: s_movk_i32 s0, 0x3000 -; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, s0, v2 -; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[2:3], off -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[6:7], off offset:2048 -; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[6:7], off +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0 +; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:2048 +; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[4:5], off ; GFX90A-NEXT: s_movk_i32 s0, 0x2000 -; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, s0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[6:7], off offset:2048 +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:2048 ; GFX90A-NEXT: s_movk_i32 s0, 0x1000 -; GFX90A-NEXT: v_add_co_u32_e32 v14, vcc, s0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v3, vcc -; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[14:15], off -; GFX90A-NEXT: global_load_dwordx2 v[18:19], v[6:7], off -; GFX90A-NEXT: global_load_dwordx2 v[20:21], v[14:15], off offset:2048 -; GFX90A-NEXT: global_load_dwordx2 v[22:23], v[2:3], off offset:2048 +; GFX90A-NEXT: v_add_co_u32_e32 v12, vcc, s0, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc +; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[12:13], off +; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[4:5], off +; GFX90A-NEXT: global_load_dwordx2 v[18:19], v[12:13], off offset:2048 +; GFX90A-NEXT: global_load_dwordx2 v[20:21], v[0:1], off offset:2048 ; GFX90A-NEXT: s_waitcnt vmcnt(6) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v8, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v5, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v3, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(5) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v11, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(4) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v12, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v13, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(2) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v18, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v19, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v16, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v17, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(1) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v20, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v21, v3, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v16, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v17, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v18, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v19, v1, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v14, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v15, v1, vcc ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v22, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v23, v3, vcc -; GFX90A-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v20, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v21, v1, vcc +; GFX90A-NEXT: global_store_dwordx2 v22, v[0:1], s[34:35] ; GFX90A-NEXT: s_endpgm ; ; GFX11-LABEL: ReverseOrder: @@ -2615,58 +2609,58 @@ ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 7, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX11-NEXT: v_and_b32_e32 v16, 0xffff8000, v2 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v16 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x3000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, 0x2000, v0 +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x3000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x2000, v0 ; GFX11-NEXT: s_clause 0x2 -; GFX11-NEXT: global_load_b64 v[6:7], v[0:1], off -; GFX11-NEXT: global_load_b64 v[8:9], v[4:5], off offset:2048 -; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off +; GFX11-NEXT: global_load_b64 v[4:5], v[0:1], off +; GFX11-NEXT: global_load_b64 v[6:7], v[2:3], off offset:2048 +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off +; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, 0x1000, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x4 -; GFX11-NEXT: global_load_b64 v[14:15], v[10:11], off offset:2048 -; GFX11-NEXT: global_load_b64 v[16:17], v[12:13], off -; GFX11-NEXT: global_load_b64 v[10:11], v[10:11], off -; GFX11-NEXT: global_load_b64 v[12:13], v[12:13], off offset:2048 +; GFX11-NEXT: global_load_b64 v[12:13], v[8:9], off offset:2048 +; GFX11-NEXT: global_load_b64 v[14:15], v[10:11], off +; GFX11-NEXT: global_load_b64 v[8:9], v[8:9], off +; GFX11-NEXT: global_load_b64 v[10:11], v[10:11], off offset:2048 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048 ; GFX11-NEXT: s_waitcnt vmcnt(6) -; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v8, v6 -; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v6, v4 +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(5) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v6 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v14, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v15, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v12, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v13, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v10, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v12, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v13, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v10, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v11, v3, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v16, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v17, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v14, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v15, v3, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo -; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_store_b64 v16, v[0:1], s[34:35] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: @@ -2777,25 +2771,25 @@ ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 7, v0 +; GFX900-NEXT: v_and_b32_e32 v8, 0xffff8000, v0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0 -; GFX900-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 -; GFX900-NEXT: v_mov_b32_e32 v4, s35 -; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v0 +; GFX900-NEXT: v_mov_b32_e32 v0, s35 +; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v8 +; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2] -; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc -; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v3, v0 -; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, v4, v1, vcc ; GFX900-NEXT: s_movk_i32 s0, 0x1000 +; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v3, v0 +; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v1, vcc ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v6, vcc -; GFX900-NEXT: v_add_co_u32_e32 v5, vcc, 0, v2 -; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, -1, v6, vcc -; GFX900-NEXT: global_load_dwordx2 v[7:8], v[0:1], off offset:-2048 -; GFX900-NEXT: global_load_dwordx2 v[9:10], v[5:6], off +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc +; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2 +; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc +; GFX900-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:-2048 +; GFX900-NEXT: global_load_dwordx2 v[6:7], v[2:3], off ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v9, v7 -; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v10, v8, vcc -; GFX900-NEXT: global_store_dwordx2 v[3:4], v[0:1], off +; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v6, v4 +; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v5, vcc +; GFX900-NEXT: global_store_dwordx2 v8, v[0:1], s[34:35] ; GFX900-NEXT: s_endpgm ; ; GFX10-LABEL: negativeoffset: @@ -2821,23 +2815,23 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 7, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff8000, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] -; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v8 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v2, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v3, v1, vcc_lo -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v4 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v5, vcc_lo -; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0, v4 -; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, -1, v5, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v3, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off -; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v6 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v7, vcc_lo -; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo +; GFX10-NEXT: global_store_dwordx2 v8, v[0:1], s[34:35] ; GFX10-NEXT: s_endpgm ; ; GFX90A-LABEL: negativeoffset: @@ -2862,25 +2856,25 @@ ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX90A-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 7, v0 -; GFX90A-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX90A-NEXT: v_and_b32_e32 v8, 0xffff8000, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, s35 -; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 3, v[2:3] -; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc +; GFX90A-NEXT: v_mov_b32_e32 v0, s35 +; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s34, v8 +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc +; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 3, v[2:3] +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v4, v0 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v1, vcc ; GFX90A-NEXT: s_movk_i32 s0, 0x1000 -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v5, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, -1, v5, vcc -; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 -; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[4:5], off +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc +; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:-2048 +; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[2:3], off ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v8, v6 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v7, vcc -; GFX90A-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v6, v4 +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v5, vcc +; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[34:35] ; GFX90A-NEXT: s_endpgm ; ; GFX11-LABEL: negativeoffset: @@ -2897,26 +2891,26 @@ ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 7, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 +; GFX11-NEXT: v_and_b32_e32 v4, 0xffff8000, v2 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v2 +; GFX11-NEXT: v_add_co_u32 v2, s0, s34, v4 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v2, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v3, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v5, vcc_lo -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0, v4 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, -1, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:-2048 -; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo -; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo +; GFX11-NEXT: global_store_b64 v4, v[0:1], s[34:35] ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: diff --git a/llvm/test/CodeGen/X86/3addr-or.ll b/llvm/test/CodeGen/X86/3addr-or.ll --- a/llvm/test/CodeGen/X86/3addr-or.ll +++ b/llvm/test/CodeGen/X86/3addr-or.ll @@ -20,7 +20,6 @@ define i64 @test2(i8 %A, i8 %B) nounwind { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: shll $4, %edi ; CHECK-NEXT: andl $48, %edi diff --git a/llvm/test/CodeGen/X86/abdu.ll b/llvm/test/CodeGen/X86/abdu.ll --- a/llvm/test/CodeGen/X86/abdu.ll +++ b/llvm/test/CodeGen/X86/abdu.ll @@ -20,8 +20,6 @@ ; ; X64-LABEL: abd_ext_i8: ; X64: # %bb.0: -; X64-NEXT: # kill: def $esi killed $esi def $rsi -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzbl %dil, %ecx ; X64-NEXT: movzbl %sil, %eax ; X64-NEXT: subq %rax, %rcx @@ -52,8 +50,6 @@ ; ; X64-LABEL: abd_ext_i8_undef: ; X64: # %bb.0: -; X64-NEXT: # kill: def $esi killed $esi def $rsi -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzbl %dil, %ecx ; X64-NEXT: movzbl %sil, %eax ; X64-NEXT: subq %rax, %rcx @@ -84,8 +80,6 @@ ; ; X64-LABEL: abd_ext_i16: ; X64: # %bb.0: -; X64-NEXT: # kill: def $esi killed $esi def $rsi -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzwl %di, %ecx ; X64-NEXT: movzwl %si, %eax ; X64-NEXT: subq %rax, %rcx @@ -116,8 +110,6 @@ ; ; X64-LABEL: abd_ext_i16_undef: ; X64: # %bb.0: -; X64-NEXT: # kill: def $esi killed $esi def $rsi -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzwl %di, %ecx ; X64-NEXT: movzwl %si, %eax ; X64-NEXT: subq %rax, %rcx diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll --- a/llvm/test/CodeGen/X86/addcarry.ll +++ b/llvm/test/CodeGen/X86/addcarry.ll @@ -683,7 +683,6 @@ define { i64, i1 } @addcarry_carry_not_i1(i64 %a, i64 %b, i8 %carryin) nounwind { ; CHECK-LABEL: addcarry_carry_not_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $edx killed $edx def $rdx ; CHECK-NEXT: addq %rsi, %rdi ; CHECK-NEXT: setb %cl ; CHECK-NEXT: movzbl %dl, %eax diff --git a/llvm/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll --- a/llvm/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll @@ -181,7 +181,6 @@ ; ; X64-LABEL: test_x86_broadcastmb_512: ; X64: # %bb.0: -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: vpbroadcastq %rax, %zmm0 ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll --- a/llvm/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll @@ -183,7 +183,6 @@ ; ; X64-LABEL: test_x86_broadcastmb_256: ; X64: # %bb.0: -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: vpbroadcastq %rax, %ymm0 ; X64-NEXT: retq @@ -202,7 +201,6 @@ ; ; X64-LABEL: test_x86_broadcastmb_128: ; X64: # %bb.0: -; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: vpbroadcastq %rax, %xmm0 ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/avx512fp16-mov.ll b/llvm/test/CodeGen/X86/avx512fp16-mov.ll --- a/llvm/test/CodeGen/X86/avx512fp16-mov.ll +++ b/llvm/test/CodeGen/X86/avx512fp16-mov.ll @@ -2130,9 +2130,8 @@ define <8 x i16> @pr59628_xmm(i16 %arg) { ; X64-LABEL: pr59628_xmm: ; X64: # %bb.0: -; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; X64-NEXT: vmovw %edi, %xmm0 ; X64-NEXT: vpbroadcastw %edi, %xmm1 -; X64-NEXT: vmovsh %xmm1, %xmm0, %xmm0 ; X64-NEXT: vpcmpneqw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1 ; X64-NEXT: vmovdqu16 %xmm0, %xmm0 {%k1} {z} ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/cmp-concat.ll b/llvm/test/CodeGen/X86/cmp-concat.ll --- a/llvm/test/CodeGen/X86/cmp-concat.ll +++ b/llvm/test/CodeGen/X86/cmp-concat.ll @@ -33,8 +33,6 @@ define i1 @cmp_anybits_concat_shl_shl_i16(i16 %x, i16 %y) { ; CHECK-LABEL: cmp_anybits_concat_shl_shl_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $esi killed $esi def $rsi -; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: movzwl %di, %eax ; CHECK-NEXT: movzwl %si, %ecx ; CHECK-NEXT: shlq $8, %rcx @@ -53,8 +51,6 @@ define i1 @cmp_anybits_concat_shl_shl_i16_commute(i16 %x, i16 %y) { ; CHECK-LABEL: cmp_anybits_concat_shl_shl_i16_commute: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $esi killed $esi def $rsi -; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: movzwl %di, %eax ; CHECK-NEXT: movzwl %si, %ecx ; CHECK-NEXT: shlq $8, %rcx diff --git a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll --- a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll +++ b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll @@ -116,9 +116,8 @@ ; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: movq x1@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl (%rax), %ebx -; CHECK-NEXT: movl %ebx, %r9d -; CHECK-NEXT: andl $511, %r9d # imm = 0x1FF -; CHECK-NEXT: leaq 1(%r9), %rax +; CHECK-NEXT: andl $511, %ebx # imm = 0x1FF +; CHECK-NEXT: leaq 1(%rbx), %rax ; CHECK-NEXT: movq x4@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movl %eax, (%rcx) ; CHECK-NEXT: movq x3@GOTPCREL(%rip), %rcx @@ -135,12 +134,11 @@ ; CHECK-NEXT: addq %rsi, %rdi ; CHECK-NEXT: movq x2@GOTPCREL(%rip), %r8 ; CHECK-NEXT: movl (%r8), %edx -; CHECK-NEXT: leal 8(,%r9,8), %eax +; CHECK-NEXT: leal 8(,%rbx,8), %eax ; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: leaq 8(%rsi), %rax ; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: leaq 32(%rsi), %r11 -; CHECK-NEXT: andl $511, %ebx # imm = 0x1FF ; CHECK-NEXT: leaq 8(,%rbx,8), %rbx ; CHECK-NEXT: xorl %r14d, %r14d ; CHECK-NEXT: movq x0@GOTPCREL(%rip), %r15 diff --git a/llvm/test/CodeGen/X86/is_fpclass-fp80.ll b/llvm/test/CodeGen/X86/is_fpclass-fp80.ll --- a/llvm/test/CodeGen/X86/is_fpclass-fp80.ll +++ b/llvm/test/CodeGen/X86/is_fpclass-fp80.ll @@ -267,10 +267,10 @@ ; CHECK-64: # %bb.0: # %entry ; CHECK-64-NEXT: movl {{[0-9]+}}(%rsp), %eax ; CHECK-64-NEXT: notl %eax -; CHECK-64-NEXT: andl $32767, %eax # imm = 0x7FFF ; CHECK-64-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000 ; CHECK-64-NEXT: xorq {{[0-9]+}}(%rsp), %rcx -; CHECK-64-NEXT: orq %rax, %rcx +; CHECK-64-NEXT: andl $32767, %eax # imm = 0x7FFF +; CHECK-64-NEXT: orq %rcx, %rax ; CHECK-64-NEXT: sete %al ; CHECK-64-NEXT: retq entry: @@ -318,12 +318,11 @@ ; ; CHECK-64-LABEL: is_neginf_f80: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: movl {{[0-9]+}}(%rsp), %eax -; CHECK-64-NEXT: notl %eax -; CHECK-64-NEXT: movzwl %ax, %eax +; CHECK-64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-64-NEXT: xorl $65535, %eax # imm = 0xFFFF ; CHECK-64-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000 ; CHECK-64-NEXT: xorq {{[0-9]+}}(%rsp), %rcx -; CHECK-64-NEXT: orq %rax, %rcx +; CHECK-64-NEXT: orq %rcx, %rax ; CHECK-64-NEXT: sete %al ; CHECK-64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/memset-inline.ll b/llvm/test/CodeGen/X86/memset-inline.ll --- a/llvm/test/CodeGen/X86/memset-inline.ll +++ b/llvm/test/CodeGen/X86/memset-inline.ll @@ -44,7 +44,6 @@ define void @memset_8(ptr %a, i8 %value) nounwind { ; GPR-LABEL: memset_8: ; GPR: # %bb.0: -; GPR-NEXT: # kill: def $esi killed $esi def $rsi ; GPR-NEXT: movzbl %sil, %eax ; GPR-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; GPR-NEXT: imulq %rax, %rcx @@ -57,7 +56,6 @@ define void @memset_16(ptr %a, i8 %value) nounwind { ; SSE2-LABEL: memset_16: ; SSE2: # %bb.0: -; SSE2-NEXT: # kill: def $esi killed $esi def $rsi ; SSE2-NEXT: movzbl %sil, %eax ; SSE2-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE2-NEXT: imulq %rax, %rcx @@ -94,7 +92,6 @@ define void @memset_32(ptr %a, i8 %value) nounwind { ; SSE2-LABEL: memset_32: ; SSE2: # %bb.0: -; SSE2-NEXT: # kill: def $esi killed $esi def $rsi ; SSE2-NEXT: movzbl %sil, %eax ; SSE2-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE2-NEXT: imulq %rax, %rcx @@ -136,7 +133,6 @@ define void @memset_64(ptr %a, i8 %value) nounwind { ; SSE2-LABEL: memset_64: ; SSE2: # %bb.0: -; SSE2-NEXT: # kill: def $esi killed $esi def $rsi ; SSE2-NEXT: movzbl %sil, %eax ; SSE2-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE2-NEXT: imulq %rax, %rcx diff --git a/llvm/test/CodeGen/X86/memset-nonzero.ll b/llvm/test/CodeGen/X86/memset-nonzero.ll --- a/llvm/test/CodeGen/X86/memset-nonzero.ll +++ b/llvm/test/CodeGen/X86/memset-nonzero.ll @@ -279,7 +279,6 @@ define void @memset_16_nonconst_bytes(ptr %x, i8 %c) { ; SSE-LABEL: memset_16_nonconst_bytes: ; SSE: # %bb.0: -; SSE-NEXT: # kill: def $esi killed $esi def $rsi ; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: imulq %rax, %rcx @@ -324,7 +323,6 @@ define void @memset_32_nonconst_bytes(ptr %x, i8 %c) { ; SSE-LABEL: memset_32_nonconst_bytes: ; SSE: # %bb.0: -; SSE-NEXT: # kill: def $esi killed $esi def $rsi ; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: imulq %rax, %rcx @@ -375,7 +373,6 @@ define void @memset_64_nonconst_bytes(ptr %x, i8 %c) { ; SSE-LABEL: memset_64_nonconst_bytes: ; SSE: # %bb.0: -; SSE-NEXT: # kill: def $esi killed $esi def $rsi ; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: imulq %rax, %rcx @@ -443,7 +440,6 @@ define void @memset_128_nonconst_bytes(ptr %x, i8 %c) { ; SSE-LABEL: memset_128_nonconst_bytes: ; SSE: # %bb.0: -; SSE-NEXT: # kill: def $esi killed $esi def $rsi ; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: imulq %rax, %rcx diff --git a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll --- a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll +++ b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll @@ -7,7 +7,6 @@ define void @test1(ptr %a, i8 %value) nounwind { ; CHECK-LABEL: test1: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; CHECK-NEXT: imulq %rax, %rcx @@ -29,7 +28,6 @@ define void @inlined_set_doesnt_call_external_function(ptr %a, i8 %value) nounwind { ; CHECK-LABEL: inlined_set_doesnt_call_external_function: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: movzbl %sil, %ecx ; CHECK-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101 ; CHECK-NEXT: imulq %rcx, %rax diff --git a/llvm/test/CodeGen/X86/narrow-shl-cst.ll b/llvm/test/CodeGen/X86/narrow-shl-cst.ll --- a/llvm/test/CodeGen/X86/narrow-shl-cst.ll +++ b/llvm/test/CodeGen/X86/narrow-shl-cst.ll @@ -212,7 +212,7 @@ ; CHECK-LABEL: test18: ; CHECK: # %bb.0: ; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: shlq $10, %rax +; CHECK-NEXT: shll $10, %eax ; CHECK-NEXT: retq %and = shl i64 %x, 10 %shl = and i64 %and, 261120 @@ -234,7 +234,7 @@ ; CHECK-LABEL: test20: ; CHECK: # %bb.0: ; CHECK-NEXT: movzwl %di, %eax -; CHECK-NEXT: shlq $10, %rax +; CHECK-NEXT: shll $10, %eax ; CHECK-NEXT: retq %and = shl i64 %x, 10 %shl = and i64 %and, 67107840 diff --git a/llvm/test/CodeGen/X86/pr30562.ll b/llvm/test/CodeGen/X86/pr30562.ll --- a/llvm/test/CodeGen/X86/pr30562.ll +++ b/llvm/test/CodeGen/X86/pr30562.ll @@ -20,7 +20,6 @@ ; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: # %bb.2: # %exit -; CHECK-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-NEXT: retq entry: br label %body diff --git a/llvm/test/CodeGen/X86/pr35763.ll b/llvm/test/CodeGen/X86/pr35763.ll --- a/llvm/test/CodeGen/X86/pr35763.ll +++ b/llvm/test/CodeGen/X86/pr35763.ll @@ -10,10 +10,10 @@ define dso_local void @PR35763() { ; CHECK-LABEL: PR35763: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movl z(%rip), %eax -; CHECK-NEXT: orl z+2(%rip), %eax -; CHECK-NEXT: movzwl %ax, %eax -; CHECK-NEXT: movq %rax, tf_3_var_136(%rip) +; CHECK-NEXT: movzwl z(%rip), %eax +; CHECK-NEXT: movzwl z+2(%rip), %ecx +; CHECK-NEXT: orl %eax, %ecx +; CHECK-NEXT: movq %rcx, tf_3_var_136(%rip) ; CHECK-NEXT: movl z+6(%rip), %eax ; CHECK-NEXT: movzbl z+10(%rip), %ecx ; CHECK-NEXT: shlq $32, %rcx diff --git a/llvm/test/CodeGen/X86/subcarry.ll b/llvm/test/CodeGen/X86/subcarry.ll --- a/llvm/test/CodeGen/X86/subcarry.ll +++ b/llvm/test/CodeGen/X86/subcarry.ll @@ -392,7 +392,6 @@ define { i64, i1 } @subcarry_carry_not_i1(i64 %a, i64 %b, i8 %carryin) { ; CHECK-LABEL: subcarry_carry_not_i1: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $edx killed $edx def $rdx ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: subq %rsi, %rax ; CHECK-NEXT: setb %cl diff --git a/llvm/test/CodeGen/X86/switch-phi-const.ll b/llvm/test/CodeGen/X86/switch-phi-const.ll --- a/llvm/test/CodeGen/X86/switch-phi-const.ll +++ b/llvm/test/CodeGen/X86/switch-phi-const.ll @@ -91,13 +91,11 @@ define void @switch_trunc_phi_const(i32 %x) { ; CHECK-LABEL: switch_trunc_phi_const: ; CHECK: # %bb.0: # %bb0 -; CHECK-NEXT: # kill: def $edi killed $edi def $rdi -; CHECK-NEXT: movzbl %dil, %ecx -; CHECK-NEXT: decl %ecx +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: leal -1(%rax), %ecx ; CHECK-NEXT: cmpl $54, %ecx ; CHECK-NEXT: ja .LBB1_8 ; CHECK-NEXT: # %bb.1: # %bb0 -; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: movl $3895, %edx # imm = 0xF37 ; CHECK-NEXT: jmpq *.LJTI1_0(,%rcx,8) ; CHECK-NEXT: .LBB1_8: # %default diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll --- a/llvm/test/CodeGen/X86/switch.ll +++ b/llvm/test/CodeGen/X86/switch.ll @@ -1416,7 +1416,6 @@ define void @int_max_table_cluster(i8 %x) { ; CHECK-LABEL: int_max_table_cluster: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: cmpb $-9, %dil ; CHECK-NEXT: ja .LBB15_4 ; CHECK-NEXT: # %bb.1: # %entry