Index: llvm/trunk/include/llvm/Support/ARMTargetParser.def
===================================================================
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def
@@ -70,9 +70,7 @@
           FK_VFPV2, AEK_DSP)
 ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
           FK_NONE, AEK_DSP)
-ARM_ARCH("armv6z", AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ,
-          FK_VFPV2, (AEK_SEC | AEK_DSP))
-ARM_ARCH("armv6zk", AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ,
+ARM_ARCH("armv6kz", AK_ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ,
           FK_VFPV2, (AEK_SEC | AEK_DSP))
 ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
           FK_NONE, AEK_NONE)
@@ -171,13 +169,11 @@
 ARM_CPU_NAME("arm1022e", AK_ARMV5TE, FK_NONE, true, AEK_NONE)
 ARM_CPU_NAME("arm926ej-s", AK_ARMV5TEJ, FK_NONE, true, AEK_NONE)
 ARM_CPU_NAME("arm1136jf-s", AK_ARMV6, FK_VFPV2, true, AEK_NONE)
-ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, false, AEK_NONE)
-ARM_CPU_NAME("arm1176jz-s", AK_ARMV6K, FK_NONE, false, AEK_NONE)
+ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, true, AEK_NONE)
+ARM_CPU_NAME("arm1176jz-s", AK_ARMV6KZ, FK_NONE, false, AEK_NONE)
 ARM_CPU_NAME("mpcore", AK_ARMV6K, FK_VFPV2, false, AEK_NONE)
 ARM_CPU_NAME("mpcorenovfp", AK_ARMV6K, FK_NONE, false, AEK_NONE)
-ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6K, FK_VFPV2, true, AEK_NONE)
-ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6Z, FK_VFPV2, true, AEK_NONE)
-ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6ZK, FK_VFPV2, true, AEK_NONE)
+ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6KZ, FK_VFPV2, true, AEK_NONE)
 ARM_CPU_NAME("arm1156t2-s", AK_ARMV6T2, FK_NONE, true, AEK_NONE)
 ARM_CPU_NAME("arm1156t2f-s", AK_ARMV6T2, FK_VFPV2, false, AEK_NONE)
 ARM_CPU_NAME("cortex-m0", AK_ARMV6M, FK_NONE, true, AEK_NONE)
Index: llvm/trunk/lib/Support/TargetParser.cpp
===================================================================
--- llvm/trunk/lib/Support/TargetParser.cpp
+++ llvm/trunk/lib/Support/TargetParser.cpp
@@ -382,6 +382,7 @@
       .Case("v5e", "v5te")
       .Case("v6hl", "v6k")
       .Cases("v6m", "v6sm", "v6s-m", "v6-m")
+      .Cases("v6z", "v6zk", "v6kz")
       .Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
       .Case("v7r", "v7-r")
       .Case("v7m", "v7-m")
@@ -561,8 +562,7 @@
   case ARM::AK_ARMV6J:
   case ARM::AK_ARMV6K:
   case ARM::AK_ARMV6T2:
-  case ARM::AK_ARMV6Z:
-  case ARM::AK_ARMV6ZK:
+  case ARM::AK_ARMV6KZ:
   case ARM::AK_ARMV6M:
     return 6;
   case ARM::AK_ARMV7A:
Index: llvm/trunk/lib/Support/Triple.cpp
===================================================================
--- llvm/trunk/lib/Support/Triple.cpp
+++ llvm/trunk/lib/Support/Triple.cpp
@@ -497,10 +497,9 @@
     return Triple::ARMSubArch_v5te;
   case ARM::AK_ARMV6:
   case ARM::AK_ARMV6J:
-  case ARM::AK_ARMV6Z:
     return Triple::ARMSubArch_v6;
   case ARM::AK_ARMV6K:
-  case ARM::AK_ARMV6ZK:
+  case ARM::AK_ARMV6KZ:
     return Triple::ARMSubArch_v6k;
   case ARM::AK_ARMV6T2:
     return Triple::ARMSubArch_v6t2;
Index: llvm/trunk/lib/Target/ARM/ARM.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td
+++ llvm/trunk/lib/Target/ARM/ARM.td
@@ -289,7 +289,7 @@
 
 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 
-def ARMv6z    : Architecture<"armv6z",    "ARMv6z",   [HasV6KOps,
+def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
                                                        FeatureTrustZone]>;
 
 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
@@ -413,8 +413,8 @@
 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 
-def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6z]>;
-def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6z,
+def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
+def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
                                                          FeatureVFP2,
                                                          FeatureHasSlowFPVMLx]>;
 
Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h
@@ -51,7 +51,7 @@
   };
   enum ARMArchEnum {
     ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
-    ARMv5tej, ARMv6, ARMv6k, ARMv6z, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
+    ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
     ARMv7m, ARMv7em, ARMv8a, ARMv81a
   };
 
Index: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -719,8 +719,7 @@
     break;
 
   case ARM::AK_ARMV6K:
-  case ARM::AK_ARMV6Z:
-  case ARM::AK_ARMV6ZK:
+  case ARM::AK_ARMV6KZ:
     setAttributeItem(ARM_ISA_use, Allowed, false);
     setAttributeItem(THUMB_ISA_use, Allowed, false);
     setAttributeItem(Virtualization_use, AllowTZ, false);
Index: llvm/trunk/test/MC/ARM/directive-arch-armv6z.s
===================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv6z.s
+++ llvm/trunk/test/MC/ARM/directive-arch-armv6z.s
@@ -11,12 +11,12 @@
 	.syntax	unified
 	.arch	armv6z
 
-@ CHECK-ASM: 	.arch	armv6z
+@ CHECK-ASM: 	.arch	armv6kz
 
 @ CHECK-ATTR: FileAttributes {
 @ CHECK-ATTR:   Attribute {
 @ CHECK-ATTR:     TagName: CPU_name
-@ CHECK-ATTR:     Value: 6Z
+@ CHECK-ATTR:     Value: 6KZ
 @ CHECK-ATTR:   }
 @ CHECK-ATTR:   Attribute {
 @ CHECK-ATTR:     TagName: CPU_arch
Index: llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s
===================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s
+++ llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s
@@ -1,38 +0,0 @@
-@ Test the .arch directive for armv6zk
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv6zk architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN:   | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
-
-	.syntax	unified
-	.arch	armv6zk
-
-@ CHECK-ASM: 	.arch	armv6zk
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_name
-@ CHECK-ATTR:     Value: 6ZK
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_arch
-@ CHECK-ATTR:     Description: ARM v6KZ
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: ARM_ISA_use
-@ CHECK-ATTR:     Description: Permitted
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: THUMB_ISA_use
-@ CHECK-ATTR:     Description: Thumb-1
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: Virtualization_use
-@ CHECK-ATTR:     Description: TrustZone
-@ CHECK-ATTR:   }
-@ CHECK-ATTR: }
-
Index: llvm/trunk/unittests/ADT/TripleTest.cpp
===================================================================
--- llvm/trunk/unittests/ADT/TripleTest.cpp
+++ llvm/trunk/unittests/ADT/TripleTest.cpp
@@ -856,6 +856,10 @@
   }
   {
     llvm::Triple Triple("armv6k-unknown-eabi");
+    EXPECT_EQ("arm1176j-s", Triple.getARMCPUForArch());
+  }
+  {
+    llvm::Triple Triple("armv6kz-unknown-eabi");
     EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
   }
   {