diff --git a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll --- a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll @@ -4,7 +4,7 @@ declare i32 @printf(ptr nocapture, ...) nounwind -define i32 @main() nounwind { +define i32 @main(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10) nounwind { entry: br label %bb.i1.i @@ -12,10 +12,10 @@ br label %bb.i.i.i bb.i.i.i: ; preds = %bb.i.i.i, %bb.i1.i - br i1 undef, label %Cos.exit.i.i, label %bb.i.i.i + br i1 %c0, label %Cos.exit.i.i, label %bb.i.i.i Cos.exit.i.i: ; preds = %bb.i.i.i - br i1 undef, label %bb2.i.i, label %bb.i1.i + br i1 %c1, label %bb2.i.i, label %bb.i1.i bb2.i.i: ; preds = %Cos.exit.i.i br label %bb3.i.i @@ -24,13 +24,13 @@ br label %bb4.i.i bb4.i.i: ; preds = %bb4.i.i, %bb3.i.i - br i1 undef, label %bb5.i.i, label %bb4.i.i + br i1 %c2, label %bb5.i.i, label %bb4.i.i bb5.i.i: ; preds = %bb4.i.i - br i1 undef, label %bb.i, label %bb3.i.i + br i1 %c3, label %bb.i, label %bb3.i.i bb.i: ; preds = %bb.i, %bb5.i.i - br i1 undef, label %bb1.outer2.i.i.outer, label %bb.i + br i1 %c4, label %bb1.outer2.i.i.outer, label %bb.i bb1.outer2.i.i.outer: ; preds = %Fft.exit.i, %bb5.i12.i, %bb.i br label %bb1.outer2.i.i @@ -39,22 +39,22 @@ br label %bb1.i.i bb1.i.i: ; preds = %bb1.i.i, %bb1.outer2.i.i - br i1 undef, label %bb2.i9.i, label %bb1.i.i + br i1 %c5, label %bb2.i9.i, label %bb1.i.i bb2.i9.i: ; preds = %bb1.i.i - br i1 undef, label %bb4.i11.i, label %bb1.outer2.i.i + br i1 %c6, label %bb4.i11.i, label %bb1.outer2.i.i bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i - br i1 undef, label %bb5.i12.i, label %bb4.i11.i + br i1 %c7, label %bb5.i12.i, label %bb4.i11.i bb5.i12.i: ; preds = %bb4.i11.i - br i1 undef, label %bb7.i.i, label %bb1.outer2.i.i.outer + br i1 %c8, label %bb7.i.i, label %bb1.outer2.i.i.outer bb7.i.i: ; preds = %bb7.i.i, %bb5.i12.i - br i1 undef, label %Fft.exit.i, label %bb7.i.i + br i1 %c9, label %Fft.exit.i, label %bb7.i.i Fft.exit.i: ; preds = %bb7.i.i - br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer + br i1 %c10, label %bb5.i, label %bb1.outer2.i.i.outer bb5.i: ; preds = %Fft.exit.i %0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", double undef, double undef) nounwind ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll --- a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll +++ b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll @@ -10,18 +10,18 @@ declare fastcc i32 @qtm_read_input(ptr nocapture) nounwind -define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes) nounwind { +define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22, i1 %c23, i1 %c24, i1 %c25, i1 %c26, i1 %c27, i1 %c28, i1 %c29, i1 %c30, i1 %c31, i1 %c32, i1 %c33, i1 %c34, i1 %c35, i1 %c36, i1 %c37, i1 %c38, i1 %c39) nounwind { entry: - br i1 undef, label %bb245, label %bb3 + br i1 %c0, label %bb245, label %bb3 bb3: ; preds = %entry - br i1 undef, label %bb5, label %bb4 + br i1 %c1, label %bb5, label %bb4 bb4: ; preds = %bb3 ret i32 undef bb5: ; preds = %bb3 - br i1 undef, label %bb245, label %bb14 + br i1 %c2, label %bb245, label %bb14 bb14: ; preds = %bb5 br label %bb238 @@ -30,34 +30,34 @@ br label %bb31 bb29: ; preds = %bb31 - br i1 undef, label %bb31, label %bb32 + br i1 %c3, label %bb31, label %bb32 bb31: ; preds = %bb29, %bb28 - br i1 undef, label %bb29, label %bb32 + br i1 %c4, label %bb29, label %bb32 bb32: ; preds = %bb31, %bb29 br label %bb33 bb33: ; preds = %bb33, %bb32 - br i1 undef, label %bb34, label %bb33 + br i1 %c5, label %bb34, label %bb33 bb34: ; preds = %bb33 - br i1 undef, label %bb35, label %bb36 + br i1 %c6, label %bb35, label %bb36 bb35: ; preds = %bb34 br label %bb36 bb36: ; preds = %bb46, %bb35, %bb34 - br i1 undef, label %bb40, label %bb37 + br i1 %c7, label %bb40, label %bb37 bb37: ; preds = %bb36 - br i1 undef, label %bb77, label %bb60 + br i1 %c8, label %bb77, label %bb60 bb40: ; preds = %bb36 - br i1 undef, label %bb46, label %bb41 + br i1 %c9, label %bb46, label %bb41 bb41: ; preds = %bb40 - br i1 undef, label %bb45, label %bb42 + br i1 %c10, label %bb45, label %bb42 bb42: ; preds = %bb41 ret i32 undef @@ -81,25 +81,25 @@ br label %bb111 bb109: ; preds = %bb111 - br i1 undef, label %bb111, label %bb112 + br i1 %c11, label %bb111, label %bb112 bb111: ; preds = %bb109, %bb108 - br i1 undef, label %bb109, label %bb112 + br i1 %c12, label %bb109, label %bb112 bb112: ; preds = %bb111, %bb109 br label %bb113 bb113: ; preds = %bb113, %bb112 - br i1 undef, label %bb114, label %bb113 + br i1 %c13, label %bb114, label %bb113 bb114: ; preds = %bb113 - br i1 undef, label %bb115, label %bb116 + br i1 %c14, label %bb115, label %bb116 bb115: ; preds = %bb114 br label %bb116 bb116: ; preds = %bb115, %bb114 - br i1 undef, label %bb120, label %bb117 + br i1 %c15, label %bb120, label %bb117 bb117: ; preds = %bb116 br label %bb136 @@ -108,13 +108,13 @@ ret i32 undef bb128: ; preds = %bb136 - br i1 undef, label %bb134, label %bb129 + br i1 %c16, label %bb134, label %bb129 bb129: ; preds = %bb128 - br i1 undef, label %bb133, label %bb130 + br i1 %c17, label %bb133, label %bb130 bb130: ; preds = %bb129 - br i1 undef, label %bb132, label %bb131 + br i1 %c18, label %bb132, label %bb131 bb131: ; preds = %bb130 ret i32 undef @@ -129,7 +129,7 @@ br label %bb136 bb136: ; preds = %bb134, %bb117 - br i1 undef, label %bb198, label %bb128 + br i1 %c19, label %bb198, label %bb128 bb138: ; preds = %bb77 %0 = trunc i32 undef to i16 ; [#uses=1] @@ -141,34 +141,34 @@ br i1 %1, label %bb141, label %bb142 bb141: ; preds = %bb139, %bb138 - br i1 undef, label %bb139, label %bb142 + br i1 %c20, label %bb139, label %bb142 bb142: ; preds = %bb141, %bb139 br label %bb143 bb143: ; preds = %bb143, %bb142 - br i1 undef, label %bb144, label %bb143 + br i1 %c21, label %bb144, label %bb143 bb144: ; preds = %bb143 - br i1 undef, label %bb145, label %bb146 + br i1 %c22, label %bb145, label %bb146 bb145: ; preds = %bb144 unreachable bb146: ; preds = %bb156, %bb144 - br i1 undef, label %bb150, label %bb147 + br i1 %c23, label %bb150, label %bb147 bb147: ; preds = %bb146 - br i1 undef, label %bb157, label %bb148 + br i1 %c24, label %bb157, label %bb148 bb148: ; preds = %bb147 - br i1 undef, label %bb149, label %bb157 + br i1 %c25, label %bb149, label %bb157 bb149: ; preds = %bb148 br label %bb150 bb150: ; preds = %bb149, %bb146 - br i1 undef, label %bb156, label %bb152 + br i1 %c26, label %bb156, label %bb152 bb152: ; preds = %bb150 unreachable @@ -177,7 +177,7 @@ br label %bb146 bb157: ; preds = %bb148, %bb147 - br i1 undef, label %bb167, label %bb160 + br i1 %c27, label %bb167, label %bb160 bb160: ; preds = %bb157 ret i32 undef @@ -186,31 +186,31 @@ br label %bb170 bb168: ; preds = %bb170 - br i1 undef, label %bb170, label %bb171 + br i1 %c28, label %bb170, label %bb171 bb170: ; preds = %bb168, %bb167 - br i1 undef, label %bb168, label %bb171 + br i1 %c29, label %bb168, label %bb171 bb171: ; preds = %bb170, %bb168 br label %bb172 bb172: ; preds = %bb172, %bb171 - br i1 undef, label %bb173, label %bb172 + br i1 %c30, label %bb173, label %bb172 bb173: ; preds = %bb172 - br i1 undef, label %bb174, label %bb175 + br i1 %c31, label %bb174, label %bb175 bb174: ; preds = %bb173 unreachable bb175: ; preds = %bb179, %bb173 - br i1 undef, label %bb179, label %bb176 + br i1 %c32, label %bb179, label %bb176 bb176: ; preds = %bb175 - br i1 undef, label %bb186, label %bb177 + br i1 %c33, label %bb186, label %bb177 bb177: ; preds = %bb176 - br i1 undef, label %bb178, label %bb186 + br i1 %c34, label %bb178, label %bb186 bb178: ; preds = %bb177 br label %bb179 @@ -222,7 +222,7 @@ br label %bb195 bb187: ; preds = %bb195 - br i1 undef, label %bb193, label %bb189 + br i1 %c35, label %bb193, label %bb189 bb189: ; preds = %bb187 %2 = tail call fastcc i32 @qtm_read_input(ptr %qtm) nounwind ; [#uses=0] @@ -232,25 +232,25 @@ br label %bb195 bb195: ; preds = %bb193, %bb186 - br i1 undef, label %bb198, label %bb187 + br i1 %c36, label %bb198, label %bb187 bb197: ; preds = %bb77 ret i32 -124 bb198: ; preds = %bb195, %bb136 - br i1 undef, label %bb211.preheader, label %bb214 + br i1 %c37, label %bb211.preheader, label %bb214 bb211.preheader: ; preds = %bb198 br label %bb211 bb211: ; preds = %bb211, %bb211.preheader - br i1 undef, label %bb214, label %bb211 + br i1 %c38, label %bb214, label %bb211 bb214: ; preds = %bb211, %bb198 br label %bb215 bb215: ; preds = %bb238, %bb214 - br i1 undef, label %bb28, label %bb216 + br i1 %c39, label %bb28, label %bb216 bb216: ; preds = %bb215 br label %bb238 diff --git a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll @@ -4,9 +4,9 @@ declare fastcc ptr @memory_Malloc(i32) nounwind -define fastcc ptr @t1() nounwind { +define fastcc ptr @t1(i1 %c0) nounwind { entry: - br i1 undef, label %bb, label %bb1 + br i1 %c0, label %bb, label %bb1 bb: ; preds = %entry ret ptr undef @@ -18,12 +18,12 @@ } -define i32 @t2(i32 %argc, ptr nocapture %argv) nounwind { +define i32 @t2(i32 %argc, ptr nocapture %argv, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22, i1 %c23, i1 %c24, i1 %c25, i1 %c26, i1 %c27, i1 %c28, i1 %c29, i1 %c30, i1 %c31, i1 %c32, i1 %c33, i1 %c34, i1 %c35, i1 %c36, i1 %c37, i1 %c38, i1 %c39, i1 %c40, i1 %c41, i1 %c42, i1 %c43, i1 %c44, i1 %c45, i1 %c46, i1 %c47, i1 %c48, i1 %c49, i1 %c50, i1 %c51, i1 %c52, i1 %c53, i1 %c54, i1 %c55) nounwind { entry: br label %bb6.i8 bb6.i8: ; preds = %memory_CalculateRealBlockSize1374.exit.i, %entry - br i1 undef, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9 + br i1 %c0, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9 bb.i.i9: ; preds = %bb6.i8 br label %memory_CalculateRealBlockSize1374.exit.i @@ -34,40 +34,40 @@ %1 = urem i32 8184, %0 ; [#uses=1] %2 = sub i32 8188, %1 ; [#uses=1] store i32 %2, ptr undef, align 4 - br i1 undef, label %memory_Init.exit, label %bb6.i8 + br i1 %c1, label %memory_Init.exit, label %bb6.i8 memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i br label %bb.i.i bb.i.i: ; preds = %bb.i.i, %memory_Init.exit - br i1 undef, label %symbol_Init.exit, label %bb.i.i + br i1 %c2, label %symbol_Init.exit, label %bb.i.i symbol_Init.exit: ; preds = %bb.i.i br label %bb.i.i67 bb.i.i67: ; preds = %bb.i.i67, %symbol_Init.exit - br i1 undef, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67 + br i1 %c3, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67 symbol_CreatePrecedence3522.exit: ; preds = %bb.i.i67 br label %bb.i.i8.i bb.i.i8.i: ; preds = %bb.i.i8.i, %symbol_CreatePrecedence3522.exit - br i1 undef, label %cont_Create.exit9.i, label %bb.i.i8.i + br i1 %c4, label %cont_Create.exit9.i, label %bb.i.i8.i cont_Create.exit9.i: ; preds = %bb.i.i8.i br label %bb.i.i.i72 bb.i.i.i72: ; preds = %bb.i.i.i72, %cont_Create.exit9.i - br i1 undef, label %cont_Init.exit, label %bb.i.i.i72 + br i1 %c5, label %cont_Init.exit, label %bb.i.i.i72 cont_Init.exit: ; preds = %bb.i.i.i72 br label %bb.i103 bb.i103: ; preds = %bb.i103, %cont_Init.exit - br i1 undef, label %subs_Init.exit, label %bb.i103 + br i1 %c6, label %subs_Init.exit, label %bb.i103 subs_Init.exit: ; preds = %bb.i103 - br i1 undef, label %bb1.i.i.i80, label %cc_Init.exit + br i1 %c7, label %bb1.i.i.i80, label %cc_Init.exit bb1.i.i.i80: ; preds = %subs_Init.exit unreachable @@ -76,22 +76,22 @@ br label %bb.i.i375 bb.i.i375: ; preds = %bb.i.i375, %cc_Init.exit - br i1 undef, label %bb.i439, label %bb.i.i375 + br i1 %c8, label %bb.i439, label %bb.i.i375 bb.i439: ; preds = %bb.i439, %bb.i.i375 - br i1 undef, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439 + br i1 %c9, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439 opts_DeclareSPASSFlagsAsOptions.exit: ; preds = %bb.i439 - br i1 undef, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82 + br i1 %c10, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82 bb.i.i82: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit unreachable opts_TranslateShortOptDeclarations.exit.i: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit - br i1 undef, label %list_Length.exit.i.thread.i, label %bb.i.i4.i + br i1 %c11, label %list_Length.exit.i.thread.i, label %bb.i.i4.i list_Length.exit.i.thread.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i - br i1 undef, label %bb18.i.i.i, label %bb26.i.i.i + br i1 %c12, label %bb18.i.i.i, label %bb26.i.i.i bb.i.i4.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i unreachable @@ -100,7 +100,7 @@ unreachable bb26.i.i.i: ; preds = %list_Length.exit.i.thread.i - br i1 undef, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i + br i1 %c13, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i opts_GetOptLongOnly.exit.thread97.i: ; preds = %bb26.i.i.i br label %bb27.i142 @@ -109,49 +109,49 @@ br label %bb1.i3.i bb1.i3.i: ; preds = %bb1.i3.i, %bb27.i142 - br i1 undef, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i + br i1 %c14, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i opts_FreeLongOptsArray.exit.i: ; preds = %bb1.i3.i br label %bb.i443 bb.i443: ; preds = %bb.i443, %opts_FreeLongOptsArray.exit.i - br i1 undef, label %flag_InitStoreByDefaults3542.exit, label %bb.i443 + br i1 %c15, label %flag_InitStoreByDefaults3542.exit, label %bb.i443 flag_InitStoreByDefaults3542.exit: ; preds = %bb.i443 - br i1 undef, label %bb6.i449, label %bb.i503 + br i1 %c16, label %bb6.i449, label %bb.i503 bb6.i449: ; preds = %flag_InitStoreByDefaults3542.exit unreachable bb.i503: ; preds = %bb.i503, %flag_InitStoreByDefaults3542.exit - br i1 undef, label %flag_CleanStore3464.exit, label %bb.i503 + br i1 %c17, label %flag_CleanStore3464.exit, label %bb.i503 flag_CleanStore3464.exit: ; preds = %bb.i503 - br i1 undef, label %bb1.i81.i.preheader, label %bb.i173 + br i1 %c18, label %bb1.i81.i.preheader, label %bb.i173 bb.i173: ; preds = %flag_CleanStore3464.exit unreachable bb1.i81.i.preheader: ; preds = %flag_CleanStore3464.exit - br i1 undef, label %bb1.i64.i.preheader, label %bb5.i179 + br i1 %c19, label %bb1.i64.i.preheader, label %bb5.i179 bb5.i179: ; preds = %bb1.i81.i.preheader unreachable bb1.i64.i.preheader: ; preds = %bb1.i81.i.preheader - br i1 undef, label %dfg_DeleteProofList.exit.i, label %bb.i9.i + br i1 %c20, label %dfg_DeleteProofList.exit.i, label %bb.i9.i bb.i9.i: ; preds = %bb1.i64.i.preheader unreachable dfg_DeleteProofList.exit.i: ; preds = %bb1.i64.i.preheader - br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i + br i1 %c21, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i bb.i.i62.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i - br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i + br i1 %c22, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i term_DeleteTermList621.exit.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i - br i1 undef, label %dfg_DFGParser.exit, label %bb.i.i211 + br i1 %c23, label %dfg_DFGParser.exit, label %bb.i.i211 bb.i.i211: ; preds = %term_DeleteTermList621.exit.i unreachable @@ -160,34 +160,34 @@ br label %bb.i513 bb.i513: ; preds = %bb2.i516, %dfg_DFGParser.exit - br i1 undef, label %bb2.i516, label %bb1.i514 + br i1 %c24, label %bb2.i516, label %bb1.i514 bb1.i514: ; preds = %bb.i513 unreachable bb2.i516: ; preds = %bb.i513 - br i1 undef, label %bb.i509, label %bb.i513 + br i1 %c25, label %bb.i509, label %bb.i513 bb.i509: ; preds = %bb.i509, %bb2.i516 - br i1 undef, label %symbol_TransferPrecedence3468.exit511, label %bb.i509 + br i1 %c26, label %symbol_TransferPrecedence3468.exit511, label %bb.i509 symbol_TransferPrecedence3468.exit511: ; preds = %bb.i509 - br i1 undef, label %bb20, label %bb21 + br i1 %c27, label %bb20, label %bb21 bb20: ; preds = %symbol_TransferPrecedence3468.exit511 unreachable bb21: ; preds = %symbol_TransferPrecedence3468.exit511 - br i1 undef, label %cnf_Init.exit, label %bb.i498 + br i1 %c28, label %cnf_Init.exit, label %bb.i498 bb.i498: ; preds = %bb21 unreachable cnf_Init.exit: ; preds = %bb21 - br i1 undef, label %bb23, label %bb22 + br i1 %c29, label %bb23, label %bb22 bb22: ; preds = %cnf_Init.exit - br i1 undef, label %bb2.i.i496, label %bb.i.i494 + br i1 %c30, label %bb2.i.i496, label %bb.i.i494 bb.i.i494: ; preds = %bb22 unreachable @@ -196,49 +196,49 @@ unreachable bb23: ; preds = %cnf_Init.exit - br i1 undef, label %bb28, label %bb24 + br i1 %c31, label %bb28, label %bb24 bb24: ; preds = %bb23 unreachable bb28: ; preds = %bb23 - br i1 undef, label %bb31, label %bb29 + br i1 %c32, label %bb31, label %bb29 bb29: ; preds = %bb28 unreachable bb31: ; preds = %bb28 - br i1 undef, label %bb34, label %bb32 + br i1 %c33, label %bb34, label %bb32 bb32: ; preds = %bb31 unreachable bb34: ; preds = %bb31 - br i1 undef, label %bb83, label %bb66 + br i1 %c34, label %bb83, label %bb66 bb66: ; preds = %bb34 unreachable bb83: ; preds = %bb34 - br i1 undef, label %bb2.i1668, label %bb.i1667 + br i1 %c35, label %bb2.i1668, label %bb.i1667 bb.i1667: ; preds = %bb83 unreachable bb2.i1668: ; preds = %bb83 - br i1 undef, label %bb5.i205, label %bb3.i204 + br i1 %c36, label %bb5.i205, label %bb3.i204 bb3.i204: ; preds = %bb2.i1668 unreachable bb5.i205: ; preds = %bb2.i1668 - br i1 undef, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i + br i1 %c37, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i bb.i206.i: ; preds = %bb5.i205 - br i1 undef, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i + br i1 %c38, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i bb1.i207.i: ; preds = %bb.i206.i - br i1 undef, label %bb25.i1801.thread, label %bb.i1688 + br i1 %c39, label %bb25.i1801.thread, label %bb.i1688 bb.i1688: ; preds = %bb1.i207.i unreachable @@ -247,10 +247,10 @@ unreachable ana_AnalyzeSortStructure.exit.i: ; preds = %bb.i206.i, %bb5.i205 - br i1 undef, label %bb7.i207, label %bb.i1806 + br i1 %c40, label %bb7.i207, label %bb.i1806 bb.i1806: ; preds = %ana_AnalyzeSortStructure.exit.i - br i1 undef, label %bb2.i.i.i1811, label %bb.i.i.i1809 + br i1 %c41, label %bb2.i.i.i1811, label %bb.i.i.i1809 bb.i.i.i1809: ; preds = %bb.i1806 unreachable @@ -259,58 +259,58 @@ unreachable bb7.i207: ; preds = %ana_AnalyzeSortStructure.exit.i - br i1 undef, label %bb9.i, label %bb8.i + br i1 %c42, label %bb9.i, label %bb8.i bb8.i: ; preds = %bb7.i207 unreachable bb9.i: ; preds = %bb7.i207 - br i1 undef, label %bb23.i, label %bb26.i + br i1 %c43, label %bb23.i, label %bb26.i bb23.i: ; preds = %bb9.i - br i1 undef, label %bb25.i, label %bb24.i + br i1 %c44, label %bb25.i, label %bb24.i bb24.i: ; preds = %bb23.i - br i1 undef, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093 + br i1 %c45, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093 bb.i2093: ; preds = %bb.i2093, %bb24.i br label %bb.i2093 sort_SortTheoryIsTrivial.exit.i: ; preds = %bb24.i - br i1 undef, label %bb3.i2141, label %bb4.i2143 + br i1 %c46, label %bb3.i2141, label %bb4.i2143 bb3.i2141: ; preds = %sort_SortTheoryIsTrivial.exit.i unreachable bb4.i2143: ; preds = %sort_SortTheoryIsTrivial.exit.i - br i1 undef, label %bb8.i2178, label %bb5.i2144 + br i1 %c47, label %bb8.i2178, label %bb5.i2144 bb5.i2144: ; preds = %bb4.i2143 - br i1 undef, label %bb7.i2177, label %bb1.i28.i + br i1 %c48, label %bb7.i2177, label %bb1.i28.i bb1.i28.i: ; preds = %bb5.i2144 - br i1 undef, label %bb4.i43.i, label %bb2.i.i2153 + br i1 %c49, label %bb4.i43.i, label %bb2.i.i2153 bb2.i.i2153: ; preds = %bb1.i28.i - br i1 undef, label %bb4.i.i33.i, label %bb.i.i30.i + br i1 %c50, label %bb4.i.i33.i, label %bb.i.i30.i bb.i.i30.i: ; preds = %bb2.i.i2153 unreachable bb4.i.i33.i: ; preds = %bb2.i.i2153 - br i1 undef, label %bb9.i.i36.i, label %bb5.i.i34.i + br i1 %c51, label %bb9.i.i36.i, label %bb5.i.i34.i bb5.i.i34.i: ; preds = %bb4.i.i33.i unreachable bb9.i.i36.i: ; preds = %bb4.i.i33.i - br i1 undef, label %bb14.i.i.i2163, label %bb10.i.i37.i + br i1 %c52, label %bb14.i.i.i2163, label %bb10.i.i37.i bb10.i.i37.i: ; preds = %bb9.i.i36.i unreachable bb14.i.i.i2163: ; preds = %bb9.i.i36.i - br i1 undef, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164 + br i1 %c53, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164 bb15.i.i.i2164: ; preds = %bb14.i.i.i2163 unreachable @@ -325,13 +325,13 @@ unreachable bb8.i2178: ; preds = %bb4.i2143 - br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader + br i1 %c54, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader bb.i5.i2185.preheader: ; preds = %bb8.i2178 br label %bb.i5.i2185 bb.i5.i2185: ; preds = %bb.i5.i2185, %bb.i5.i2185.preheader - br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185 + br i1 %c55, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185 sort_ApproxStaticSortTheory.exit: ; preds = %bb.i5.i2185, %bb8.i2178 br label %bb25.i diff --git a/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll @@ -1,21 +1,21 @@ ; RUN: llc < %s -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard ; PR4419 -define float @__ieee754_acosf(float %x) nounwind { +define float @__ieee754_acosf(float %x, i1 %c0, i1 %c1, i1 %c2) nounwind { entry: - br i1 undef, label %bb, label %bb4 + br i1 %c0, label %bb, label %bb4 bb: ; preds = %entry ret float undef bb4: ; preds = %entry - br i1 undef, label %bb5, label %bb6 + br i1 %c1, label %bb5, label %bb6 bb5: ; preds = %bb4 ret float undef bb6: ; preds = %bb4 - br i1 undef, label %bb11, label %bb12 + br i1 %c2, label %bb11, label %bb12 bb11: ; preds = %bb6 %0 = tail call float @__ieee754_sqrtf(float undef) nounwind ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll --- a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -3,7 +3,7 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define void @simplify_unary_real(ptr nocapture %p) nounwind { +define void @simplify_unary_real(ptr nocapture %p, i1 %c0) nounwind { entry: %tmp121 = load i64, ptr null, align 4 ; [#uses=1] %0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] @@ -25,7 +25,7 @@ ret void bb21: ; preds = %entry - br i1 undef, label %bb82, label %bb29 + br i1 %c0, label %bb82, label %bb29 bb29: ; preds = %bb21 %tmp18.i = and i192 %3, 1208907372870555465154560 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -12,24 +12,24 @@ declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %c0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %c1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %c2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %c3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable @@ -55,67 +55,67 @@ %11 = sub i32 %10, %9 ; [#uses=1] %12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; [#uses=0] %13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] - br i1 undef, label %bb15, label %bb12 + br i1 %c4, label %bb15, label %bb12 bb12: ; preds = %bb11 br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %c5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %c6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %c7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %c8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %c9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i bb158.i: ; preds = %bb218.i, %bb.nph.i98 - br i1 undef, label %bb168.i, label %bb160.i + br i1 %c10, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %c11, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %c12, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %c13, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i - br i1 undef, label %bb211.i, label %bb218.i + br i1 %c14, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %c15, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - br i1 undef, label %bb221.i, label %bb228.i + br i1 %c16, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %c17, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %c18, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -10,24 +10,24 @@ declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %c0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %c1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %c2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %c3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable @@ -46,70 +46,70 @@ %6 = load i32, ptr @no_mis, align 4 ; [#uses=1] %7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; [#uses=0] %8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] - br i1 undef, label %bb15, label %bb12 + br i1 %c4, label %bb15, label %bb12 bb12: ; preds = %bb11 br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %c5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %c6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %c7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %c8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %c9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i bb158.i: ; preds = %bb218.i, %bb.nph.i98 - br i1 undef, label %bb168.i, label %bb160.i + br i1 %c10, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %c11, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %c12, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %c13, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i - br i1 undef, label %bb211.i, label %bb218.i + br i1 %c14, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %c15, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - br i1 undef, label %bb221.i, label %bb228.i + br i1 %c16, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %c17, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 %indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; [#uses=2] %tmp13 = add i32 %indvar11, 1 ; [#uses=2] %count.0 = sub i32 undef, %indvar11 ; [#uses=0] - br i1 undef, label %return, label %bb9 + br i1 %c18, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -2,47 +2,47 @@ @JJ = external global ptr ; [#uses=1] -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %c0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %c1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %c2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %c3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - br i1 undef, label %bb15, label %bb12 + br i1 %c4, label %bb15, label %bb12 bb12: ; preds = %bb11 %0 = load ptr, ptr @JJ, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %c5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i %cflag.0.i = phi i16 [ 0, %bb228.i ], [ 0, %bb74.i ], [ 1, %bb138.i ] ; [#uses=1] - br i1 undef, label %bb146.i, label %bb151.i + br i1 %c6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %c7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i %.not297 = icmp ne i16 %cflag.0.i, 0 ; [#uses=1] @@ -50,7 +50,7 @@ br i1 %or.cond298, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %c8, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -65,13 +65,13 @@ %i.121.i = sub i32 undef, undef ; [#uses=3] %tmp105.i = sub i32 undef, undef ; [#uses=1] %1 = sub i32 %c.1020.i, undef ; [#uses=0] - br i1 undef, label %bb168.i, label %bb160.i + br i1 %c9, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %c10, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %c11, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i %2 = icmp slt i32 %fj.515.i, undef ; [#uses=1] @@ -100,7 +100,7 @@ store i32 %ci.12.i, ptr %scevgep88.i, align 4 store i32 %cj.11.i100, ptr %scevgep89.i, align 4 store i32 %4, ptr undef, align 4 - br i1 undef, label %bb211.i, label %bb218.i + br i1 %c12, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i @@ -112,16 +112,16 @@ bb220.i: ; preds = %bb218.i, %bb153.i %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; [#uses=0] - br i1 undef, label %bb221.i, label %bb228.i + br i1 %c13, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %c14, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %c15, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -8,25 +8,25 @@ declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %c0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %c1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %c2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 %0 = load ptr, ptr @name1, align 4 ; [#uses=0] br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %c3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable @@ -36,7 +36,7 @@ %1 = getelementptr i8, ptr %A, i32 0 ; [#uses=1] %2 = getelementptr i8, ptr %B, i32 0 ; [#uses=1] tail call void @diff(ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind - br i1 undef, label %bb15, label %bb12 + br i1 %c4, label %bb15, label %bb12 bb12: ; preds = %bb11 %3 = load ptr, ptr @II, align 4 ; [#uses=1] @@ -45,23 +45,23 @@ br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %c5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %c6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %c7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %c8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i %6 = add i32 undef, -1 ; [#uses=3] - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %c9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -80,13 +80,13 @@ br i1 %9, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %c10, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %c11, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %c12, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i @@ -101,27 +101,27 @@ %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] %10 = load i32, ptr %scevgep88.i, align 4 ; [#uses=1] - br i1 undef, label %bb211.i, label %bb218.i + br i1 %c13, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %c14, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i %11 = getelementptr i32, ptr null, i32 %6 ; [#uses=1] store i32 undef, ptr %11, align 4 - br i1 undef, label %bb221.i, label %bb228.i + br i1 %c15, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %c16, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %c17, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -2,52 +2,52 @@ @XX = external global ptr ; [#uses=1] -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %c0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %c1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %c2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %c3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - br i1 undef, label %bb15, label %bb12 + br i1 %c4, label %bb15, label %bb12 bb12: ; preds = %bb11 %0 = load ptr, ptr @XX, align 4 ; [#uses=0] br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %c5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %c6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %c7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %c8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %c9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -55,16 +55,16 @@ bb158.i: ; preds = %bb218.i, %bb.nph.i98 %1 = sub i32 undef, undef ; [#uses=4] %2 = sub i32 undef, undef ; [#uses=1] - br i1 undef, label %bb168.i, label %bb160.i + br i1 %c10, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %c11, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %c12, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %c13, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i @@ -74,25 +74,25 @@ %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] store i32 %c.14.i, ptr undef, align 4 store i32 undef, ptr null, align 4 - br i1 undef, label %bb211.i, label %bb218.i + br i1 %c14, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %c15, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - br i1 undef, label %bb221.i, label %bb228.i + br i1 %c16, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %c17, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %c18, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll --- a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -4,30 +4,30 @@ @II = external global ptr ; [#uses=1] @JJ = external global ptr ; [#uses=1] -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %c0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %c1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %c2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %c3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - br i1 undef, label %bb15, label %bb12 + br i1 %c4, label %bb15, label %bb12 bb12: ; preds = %bb11 %0 = load ptr, ptr @II, align 4 ; [#uses=1] @@ -36,17 +36,17 @@ br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %c5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i %cflag.0.i = phi i16 [ %cflag.1.i, %bb228.i ], [ %cflag.1.i, %bb74.i ], [ 1, %bb138.i ] ; [#uses=2] - br i1 undef, label %bb146.i, label %bb151.i + br i1 %c6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %c7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i %.not297 = icmp ne i16 %cflag.0.i, 0 ; [#uses=1] @@ -54,7 +54,7 @@ br i1 %or.cond298, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %c8, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -75,13 +75,13 @@ br i1 %5, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %c9, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %c10, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %c11, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i @@ -101,7 +101,7 @@ %7 = load i32, ptr %scevgep89.i, align 4 ; [#uses=1] store i32 %ci.12.i, ptr %scevgep88.i, align 4 store i32 %cj.11.i100, ptr %scevgep89.i, align 4 - br i1 undef, label %bb211.i, label %bb218.i + br i1 %c12, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i @@ -113,7 +113,7 @@ bb220.i: ; preds = %bb218.i, %bb153.i %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; [#uses=2] - br i1 undef, label %bb221.i, label %bb228.i + br i1 %c13, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i diff --git a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -8,34 +8,34 @@ declare i32 @strlen(ptr nocapture) nounwind readonly -define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12) nounwind { entry: - br i1 undef, label %bb126, label %bb1 + br i1 %c0, label %bb126, label %bb1 bb1: ; preds = %entry - br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit + br i1 %c1, label %cli_calloc.exit.thread, label %cli_calloc.exit cli_calloc.exit.thread: ; preds = %bb1 ret i32 -114 cli_calloc.exit: ; preds = %bb1 store i16 %parts, ptr undef, align 4 - br i1 undef, label %bb52, label %bb4 + br i1 %c2, label %bb52, label %bb4 bb4: ; preds = %cli_calloc.exit - br i1 undef, label %bb.i, label %bb1.i3 + br i1 %c3, label %bb.i, label %bb1.i3 bb.i: ; preds = %bb4 unreachable bb1.i3: ; preds = %bb4 - br i1 undef, label %bb2.i4, label %cli_strdup.exit + br i1 %c4, label %bb2.i4, label %cli_strdup.exit bb2.i4: ; preds = %bb1.i3 ret i32 -114 cli_strdup.exit: ; preds = %bb1.i3 - br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 + br i1 %c5, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 cli_calloc.exit54.thread: ; preds = %cli_strdup.exit ret i32 -114 @@ -47,31 +47,31 @@ unreachable cli_calloc.exit70: ; preds = %bb45 - br i1 undef, label %bb.i83, label %bb1.i84 + br i1 %c6, label %bb.i83, label %bb1.i84 bb.i83: ; preds = %cli_calloc.exit70 unreachable bb1.i84: ; preds = %cli_calloc.exit70 - br i1 undef, label %bb2.i85, label %bb17 + br i1 %c7, label %bb2.i85, label %bb17 bb2.i85: ; preds = %bb1.i84 unreachable bb17: ; preds = %bb1.i84 - br i1 undef, label %bb22, label %bb.nph + br i1 %c8, label %bb22, label %bb.nph bb.nph: ; preds = %bb17 br label %bb18 bb18: ; preds = %bb18, %bb.nph - br i1 undef, label %bb18, label %bb22 + br i1 %c9, label %bb18, label %bb22 bb22: ; preds = %bb18, %bb17 - br i1 undef, label %bb25, label %bb43.preheader + br i1 %c10, label %bb25, label %bb43.preheader bb43.preheader: ; preds = %bb22 - br i1 undef, label %bb28, label %bb45 + br i1 %c11, label %bb28, label %bb45 bb25: ; preds = %bb22 unreachable @@ -80,7 +80,7 @@ unreachable bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 - br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 + br i1 %c12, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit %0 = load i16, ptr undef, align 4 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -6,33 +6,33 @@ %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 } %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 } -define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11) nounwind { entry: - br i1 undef, label %bb126, label %bb1 + br i1 %c0, label %bb126, label %bb1 bb1: ; preds = %entry - br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit + br i1 %c1, label %cli_calloc.exit.thread, label %cli_calloc.exit cli_calloc.exit.thread: ; preds = %bb1 ret i32 -114 cli_calloc.exit: ; preds = %bb1 - br i1 undef, label %bb52, label %bb4 + br i1 %c2, label %bb52, label %bb4 bb4: ; preds = %cli_calloc.exit - br i1 undef, label %bb.i, label %bb1.i3 + br i1 %c3, label %bb.i, label %bb1.i3 bb.i: ; preds = %bb4 unreachable bb1.i3: ; preds = %bb4 - br i1 undef, label %bb2.i4, label %cli_strdup.exit + br i1 %c4, label %bb2.i4, label %cli_strdup.exit bb2.i4: ; preds = %bb1.i3 ret i32 -114 cli_strdup.exit: ; preds = %bb1.i3 - br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 + br i1 %c5, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 cli_calloc.exit54.thread: ; preds = %cli_strdup.exit ret i32 -114 @@ -44,25 +44,25 @@ unreachable cli_calloc.exit70: ; preds = %bb45 - br i1 undef, label %bb.i83, label %bb1.i84 + br i1 %c6, label %bb.i83, label %bb1.i84 bb.i83: ; preds = %cli_calloc.exit70 unreachable bb1.i84: ; preds = %cli_calloc.exit70 - br i1 undef, label %bb2.i85, label %bb17 + br i1 %c7, label %bb2.i85, label %bb17 bb2.i85: ; preds = %bb1.i84 unreachable bb17: ; preds = %bb1.i84 - br i1 undef, label %bb22, label %bb.nph + br i1 %c8, label %bb22, label %bb.nph bb.nph: ; preds = %bb17 br label %bb18 bb18: ; preds = %bb18, %bb.nph - br i1 undef, label %bb18, label %bb22 + br i1 %c9, label %bb18, label %bb22 bb22: ; preds = %bb18, %bb17 %0 = getelementptr i8, ptr null, i32 10 ; [#uses=1] @@ -75,7 +75,7 @@ br i1 %6, label %bb25, label %bb43.preheader bb43.preheader: ; preds = %bb22 - br i1 undef, label %bb28, label %bb45 + br i1 %c10, label %bb28, label %bb45 bb25: ; preds = %bb22 unreachable @@ -84,7 +84,7 @@ unreachable bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 - br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 + br i1 %c11, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit unreachable diff --git a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll --- a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -4,17 +4,17 @@ declare double @llvm.exp.f64(double) nounwind readonly -define void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind { +define void @findratio(ptr nocapture %res1, ptr nocapture %res2, i1 %c0, i1 %c1, i1 %c2) nounwind { entry: br label %bb bb: ; preds = %bb, %entry - br i1 undef, label %bb28, label %bb + br i1 %c0, label %bb28, label %bb bb28: ; preds = %bb %0 = load double, ptr @a, align 4 ; [#uses=2] %1 = fadd double %0, undef ; [#uses=2] - br i1 undef, label %bb59, label %bb60 + br i1 %c1, label %bb59, label %bb60 bb59: ; preds = %bb28 %2 = fsub double -0.000000e+00, undef ; [#uses=2] @@ -94,7 +94,7 @@ %.pn2 = fadd double %.pn6, %.pn7 ; [#uses=1] %N1.0 = fsub double %.pn4, undef ; [#uses=1] %D1.0 = fsub double %.pn2, undef ; [#uses=2] - br i1 undef, label %bb62, label %bb64 + br i1 %c2, label %bb62, label %bb64 bb62: ; preds = %bb61 %7 = fadd double %D1.0, undef ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll --- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll +++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll @@ -4,9 +4,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-elf" -define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size, i1 %c0, i1 %c1, i1 %c2) nounwind optsize { entry: - br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i + br i1 %c0, label %fault_in_pages_writeable.exit, label %bb5.i bb5.i: ; preds = %entry %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; [#uses=1] @@ -14,13 +14,13 @@ br i1 %0, label %bb6.i, label %fault_in_pages_writeable.exit bb6.i: ; preds = %bb5.i - br i1 undef, label %fault_in_pages_writeable.exit, label %bb7.i + br i1 %c1, label %fault_in_pages_writeable.exit, label %bb7.i bb7.i: ; preds = %bb6.i unreachable fault_in_pages_writeable.exit: ; preds = %bb6.i, %bb5.i, %entry - br i1 undef, label %bb2, label %bb3 + br i1 %c2, label %bb2, label %bb3 bb2: ; preds = %fault_in_pages_writeable.exit unreachable diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 -define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size, i1 %c0) nounwind optsize { entry: - br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i + br i1 %c0, label %fault_in_pages_writeable.exit, label %bb5.i bb5.i: ; preds = %entry %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll --- a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -6,12 +6,12 @@ %struct.device_dma_parameters = type { i32, i32 } %struct.iovec = type { ptr, i32 } -define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags) nounwind optsize { +define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags, i1 %c0, i1 %c1) nounwind optsize { entry: br label %bb8 bb: ; preds = %bb8 - br i1 undef, label %bb10, label %bb2 + br i1 %c0, label %bb10, label %bb2 bb2: ; preds = %bb %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1] @@ -20,7 +20,7 @@ br i1 %0, label %bb7, label %bb4 bb4: ; preds = %bb2 - br i1 undef, label %bb10, label %bb9 + br i1 %c1, label %bb10, label %bb9 bb7: ; preds = %bb2 %1 = add i32 %2, 1 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -7,10 +7,10 @@ %struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr } @g = common global ptr null -define ptr @tsp(ptr %t, i32 %nproc) nounwind { +define ptr @tsp(ptr %t, i32 %nproc, i1 %c0, i1 %c1) nounwind { entry: %t.idx51.val.i = load double, ptr null ; [#uses=1] - br i1 undef, label %bb4.i, label %bb.i + br i1 %c0, label %bb4.i, label %bb.i bb.i: ; preds = %entry unreachable @@ -27,7 +27,7 @@ %4 = fmul double %3, %3 ; [#uses=1] %5 = fadd double %2, %4 ; [#uses=1] %6 = tail call double @llvm.sqrt.f64(double %5) nounwind ; [#uses=1] - br i1 undef, label %bb7.i4, label %bb6.i + br i1 %c1, label %bb7.i4, label %bb6.i bb6.i: ; preds = %bb4.i br label %bb7.i4 diff --git a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll --- a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll +++ b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll @@ -9,9 +9,9 @@ %quux = type { ptr, ptr, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define void @aaaa(ptr %this, ptr %block) { +define void @aaaa(ptr %this, ptr %block, i1 %c0, i1 %c1) { entry: - br i1 undef, label %bb.nph269, label %bb201 + br i1 %c0, label %bb.nph269, label %bb201 bb.nph269: br label %bb12 @@ -21,7 +21,7 @@ %1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> zeroinitializer %3 = fadd <4 x float> undef, %2 - br i1 undef, label %bb194, label %bb186 + br i1 %c1, label %bb194, label %bb186 bb186: br label %bb194 diff --git a/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll --- a/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll +++ b/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define void @foo() nounwind { +define void @foo(i1 %c0) nounwind { entry: %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; [#uses=1] @@ -13,7 +13,7 @@ unreachable bb7: ; preds = %entry - br i1 undef, label %bb8, label %bb9 + br i1 %c0, label %bb8, label %bb9 bb8: ; preds = %bb7 unreachable diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll @@ -11,7 +11,7 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone -define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind { +define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box, i1 %c0) nounwind { entry: %val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1] %val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1] @@ -51,7 +51,7 @@ br i1 %26, label %bb41, label %bb33 bb33: ; preds = %bb, %entry - br i1 undef, label %bb34, label %bb + br i1 %c0, label %bb34, label %bb bb34: ; preds = %bb33 ret i8 undef diff --git a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll --- a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll @@ -2,9 +2,9 @@ ; PR4986 -define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems, i1 %c0, i1 %c1) nounwind { entry: - br i1 undef, label %return, label %bb.preheader + br i1 %c0, label %return, label %bb.preheader bb.preheader: ; preds = %entry br label %bb @@ -17,7 +17,7 @@ %4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1] %5 = extractelement <4 x float> %4, i32 3 ; [#uses=1] store float %5, ptr undef, align 4 - br i1 undef, label %return, label %bb + br i1 %c1, label %return, label %bb return: ; preds = %bb, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll --- a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll @@ -9,9 +9,9 @@ declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind -define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems, i1 %c0) nounwind { entry: - br i1 undef, label %return, label %bb.nph + br i1 %c0, label %return, label %bb.nph bb.nph: ; preds = %entry %0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll --- a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s ; PR5367 -define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems, i1 %c0, i1 %c1) nounwind { entry: - br i1 undef, label %return, label %bb + br i1 %c0, label %return, label %bb bb: ; preds = %bb, %entry %0 = load float, ptr undef, align 4 ; [#uses=1] @@ -54,7 +54,7 @@ store float 0.000000e+00, ptr null, align 4 %44 = extractelement <4 x float> %43, i32 1 ; [#uses=1] store float %44, ptr undef, align 4 - br i1 undef, label %return, label %bb + br i1 %c1, label %return, label %bb return: ; preds = %bb, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll --- a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -2,9 +2,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" -define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems, i1 %c0, i1 %c1) nounwind { entry: - br i1 undef, label %return, label %bb + br i1 %c0, label %return, label %bb bb: ; preds = %bb, %entry ; CHECK: vld1.16 {d16[], d17[]} @@ -14,7 +14,7 @@ %3 = mul <8 x i16> %2, %2 %4 = extractelement <8 x i16> %3, i32 2 store i16 %4, ptr undef, align 2 - br i1 undef, label %return, label %bb + br i1 %c1, label %return, label %bb return: ; preds = %bb, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll @@ -5,9 +5,9 @@ %pln = type { %vec, float } %vec = type { [4 x float] } -define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint) { +define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint, i1 %c0) { entry: - br i1 undef, label %bb81, label %bb48 + br i1 %c0, label %bb81, label %bb48 bb48: ; preds = %entry %0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll @@ -8,9 +8,9 @@ %quux = type { %quad, %quad } %quuz = type { [4 x ptr], [4 x float], i32 } -define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %c0) { entry: - br i1 undef, label %bb85, label %bb + br i1 %c0, label %bb85, label %bb bb: ; preds = %entry %0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; [#uses=2] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll @@ -8,12 +8,12 @@ %quux = type { [4 x ptr], [4 x float], i32 } %quuz = type { %quad, %quad } -define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %c0, i1 %c1) { entry: - br i1 undef, label %bb85, label %bb + br i1 %c0, label %bb85, label %bb bb: ; preds = %entry - br i1 undef, label %bb3.i, label %bb2.i + br i1 %c1, label %bb3.i, label %bb2.i bb2.i: ; preds = %bb br label %bb3.i diff --git a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll @@ -9,13 +9,13 @@ %quux = type { [4 x ptr], [4 x float], i32 } %quuz = type { %quad, %quad } -define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %c0) { entry: %0 = load ptr, ptr undef, align 4 ; [#uses=2] br i1 false, label %bb85, label %bb bb: ; preds = %entry - br i1 undef, label %bb3.i, label %bb2.i + br i1 %c0, label %bb3.i, label %bb2.i bb2.i: ; preds = %bb br label %bb3.i diff --git a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll --- a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { +define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) { %1 = load i32, ptr undef ; [#uses=1] %2 = sub i32 %1, 48 ; [#uses=1] - br i1 undef, label %stack_overflow, label %no_overflow + br i1 %c0, label %stack_overflow, label %no_overflow stack_overflow: ; preds = %0 unreachable @@ -16,13 +16,13 @@ %6 = load ptr, ptr %5 ; [#uses=1] %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; [#uses=1] %8 = load i32, ptr %7 ; [#uses=1] - br i1 undef, label %bci_13, label %bci_4 + br i1 %c1, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow - br i1 undef, label %bci_30, label %bci_21 + br i1 %c2, label %bci_30, label %bci_21 bci_30: ; preds = %bci_13 - br i1 undef, label %bci_46, label %bci_35 + br i1 %c3, label %bci_46, label %bci_35 bci_46: ; preds = %bci_30 %9 = sub i32 %4, %3 ; [#uses=1] @@ -42,7 +42,7 @@ store i32 %16, ptr undef store ptr %6, ptr undef call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread) - br i1 undef, label %no_exception, label %exception + br i1 %c4, label %no_exception, label %exception exception: ; preds = %bci_46 ret void diff --git a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll --- a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null -define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { +define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread, i1 %c0, i1 %c1, i1 %c2) { %1 = sub i32 undef, 48 ; [#uses=1] - br i1 undef, label %stack_overflow, label %no_overflow + br i1 %c0, label %stack_overflow, label %no_overflow stack_overflow: ; preds = %0 unreachable @@ -13,10 +13,10 @@ %3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; [#uses=1] %4 = load i32, ptr %3 ; [#uses=2] %5 = load ptr, ptr undef ; [#uses=2] - br i1 undef, label %bci_13, label %bci_4 + br i1 %c1, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow - br i1 undef, label %bci_30, label %bci_21 + br i1 %c2, label %bci_30, label %bci_21 bci_30: ; preds = %bci_13 %6 = icmp sle i32 %2, %4 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll --- a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values. -define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction, i1 %c0) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] @@ -12,7 +12,7 @@ %5 = fadd <4 x float> undef, %4 ; <<4 x float>> [#uses=1] %6 = fadd <4 x float> undef, %5 ; <<4 x float>> [#uses=1] %7 = fadd <4 x float> undef, %6 ; <<4 x float>> [#uses=1] - br i1 undef, label %bb4, label %bb3 + br i1 %c0, label %bb4, label %bb3 bb3: ; preds = %entry %8 = shufflevector <4 x float> undef, <4 x float> %7, <4 x i32> ; <<4 x float>> [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll --- a/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll +++ b/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=arm1136jf-s %s -o /dev/null ; Radar 7854640 -define void @test() nounwind { +define void @test(i1 %c0) nounwind { bb: - br i1 undef, label %bb9, label %bb10 + br i1 %c0, label %bb9, label %bb10 bb9: %tmp63 = bitcast <4 x float> zeroinitializer to i128 diff --git a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll --- a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll @@ -14,7 +14,7 @@ declare fastcc i32 @FirstOne() -define fastcc void @Evaluate() { +define fastcc void @Evaluate(i1 %c0) { entry: br i1 false, label %cond_false186, label %cond_true @@ -94,7 +94,7 @@ %tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1] %tmp1599 = load i32, ptr %tmp1598 ; [#uses=1] %tmp1602 = sub i32 0, %tmp1599 ; [#uses=1] - br i1 undef, label %cond_next1637, label %cond_true1607 + br i1 %c0, label %cond_next1637, label %cond_true1607 cond_true1607: ; preds = %bb1567 ret void diff --git a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll --- a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -10,7 +10,7 @@ @.str = external constant [1 x i8] ; [#uses=1] -define void @yy(ptr %qq) nounwind { +define void @yy(ptr %qq, i1 %c0) nounwind { entry: %vla6 = alloca i8, i32 undef, align 1 ; [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; [#uses=1] @@ -20,7 +20,7 @@ %0 = mul i32 1, %tmp21 ; [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] call void (...) @zz(ptr @.str, i32 2, i32 1) - br i1 undef, label %if.then, label %if.end36 + br i1 %c0, label %if.then, label %if.end36 if.then: ; preds = %entry %call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll --- a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -10,7 +10,7 @@ @.str2708 = external constant [14 x i8], align 4 ; [#uses=1] -define void @TW_oldinput(ptr nocapture %fp) nounwind { +define void @TW_oldinput(ptr nocapture %fp, i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind { entry: %xcenter = alloca i32, align 4 ; [#uses=2] %0 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; [#uses=1] @@ -26,7 +26,7 @@ br i1 %5, label %bb10, label %bb445 bb10: ; preds = %bb - br i1 undef, label %bb11, label %bb445 + br i1 %c0, label %bb11, label %bb445 bb11: ; preds = %bb10 %6 = load ptr, ptr undef, align 4 ; [#uses=3] @@ -48,7 +48,7 @@ %15 = fptosi double %14 to i32 ; [#uses=1] %iftmp.41.0.in = add i32 0, %15 ; [#uses=1] %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; [#uses=3] - br i1 undef, label %bb43.loopexit, label %bb21 + br i1 %c1, label %bb43.loopexit, label %bb21 bb21: ; preds = %bb13 %16 = fptosi double undef to i32 ; [#uses=1] @@ -98,7 +98,7 @@ br i1 %43, label %bb52.loopexit, label %bb36 bb43.loopexit: ; preds = %bb21, %bb13 - br i1 undef, label %bb52.loopexit, label %bb36 + br i1 %c2, label %bb52.loopexit, label %bb36 bb52.loopexit: ; preds = %bb43.loopexit, %bb36 %44 = icmp eq i32 %4, 0 ; [#uses=1] @@ -134,7 +134,7 @@ unreachable bb322: ; preds = %bb248 - br i1 undef, label %bb248, label %bb445 + br i1 %c3, label %bb248, label %bb445 bb445: ; preds = %bb322, %bb10, %bb %49 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll --- a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll +++ b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll @@ -2,9 +2,9 @@ declare noalias ptr @malloc(i32) nounwind -define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels) nounwind { +define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7) nounwind { entry: - br i1 undef, label %bb3.i, label %bb3 + br i1 %c0, label %bb3.i, label %bb3 bb3.i: ; preds = %entry unreachable @@ -19,7 +19,7 @@ br label %bb5 bb5: ; preds = %bb4, %bb3 - br i1 undef, label %bb19, label %bb22 + br i1 %c1, label %bb19, label %bb22 bb19: ; preds = %bb5 switch i32 %type, label %bb3.i6.i [ @@ -35,13 +35,13 @@ unreachable bb1.i13: ; preds = %bb9.i.i6, %bb19, %bb19 - br i1 undef, label %bb3.i17, label %bb2.i16 + br i1 %c2, label %bb3.i17, label %bb2.i16 bb2.i16: ; preds = %bb1.i13 unreachable bb3.i17: ; preds = %bb1.i13 - br i1 undef, label %bb4.i18, label %bb23.i + br i1 %c3, label %bb4.i18, label %bb23.i bb4.i18: ; preds = %bb3.i17 %0 = mul nsw i32 %height, %width @@ -50,13 +50,13 @@ %2 = zext i1 %not..i to i32 %storemerge2.i = add i32 0, %2 %3 = call noalias ptr @malloc(i32 %storemerge2.i) nounwind - br i1 undef, label %bb3.i9, label %bb9.i + br i1 %c4, label %bb3.i9, label %bb9.i bb9.i: ; preds = %bb4.i18 - br i1 undef, label %bb13.i19, label %bb.i24.i + br i1 %c5, label %bb13.i19, label %bb.i24.i bb13.i19: ; preds = %bb9.i - br i1 undef, label %bb14.i20, label %bb15.i + br i1 %c6, label %bb14.i20, label %bb15.i bb14.i20: ; preds = %bb13.i19 unreachable @@ -77,7 +77,7 @@ unreachable bb22: ; preds = %bb.i24.i, %bb5 - br i1 undef, label %gl_error.exit, label %bb23 + br i1 %c7, label %gl_error.exit, label %bb23 bb23: ; preds = %bb22 ret void diff --git a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll --- a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -13,24 +13,24 @@ %0 = type { i32, i32 } -define void @foo(ptr %in) nounwind { +define void @foo(ptr %in, i1 %c0, i1 %c1, i1 %c2) nounwind { entry: br label %bb.i bb.i: ; preds = %bb.i, %entry - br i1 undef, label %bb10.preheader.i, label %bb.i + br i1 %c0, label %bb10.preheader.i, label %bb.i bb10.preheader.i: ; preds = %bb.i br label %bb10.i bb10.i: ; preds = %bb10.i, %bb10.preheader.i - br i1 undef, label %bb27.i, label %bb10.i + br i1 %c1, label %bb27.i, label %bb10.i bb27.i: ; preds = %bb10.i br label %bb28.i bb28.i: ; preds = %bb28.i, %bb27.i - br i1 undef, label %presymmetry.exit, label %bb28.i + br i1 %c2, label %presymmetry.exit, label %bb28.i presymmetry.exit: ; preds = %bb28.i %tmp175387 = or i32 undef, 12 diff --git a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll --- a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll +++ b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll @@ -6,13 +6,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" target triple = "armv5e-none-linux-gnueabi" -define hidden fastcc void @storeAtts() nounwind { +define hidden fastcc void @storeAtts(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8) nounwind { entry: %.SV116 = alloca ptr - br i1 undef, label %meshBB520, label %meshBB464 + br i1 %c0, label %meshBB520, label %meshBB464 bb15: ; preds = %meshBB424 - br i1 undef, label %bb216, label %meshBB396 + br i1 %c1, label %bb216, label %meshBB396 bb22: ; preds = %meshBB396 br label %cBB564 @@ -27,13 +27,13 @@ unreachable bb129: ; preds = %meshBB540 - br i1 undef, label %bb131.loopexit, label %meshBB540 + br i1 %c2, label %bb131.loopexit, label %meshBB540 bb131.loopexit: ; preds = %bb129 br label %bb131 bb131: ; preds = %bb135, %bb131.loopexit - br i1 undef, label %bb134, label %meshBB396 + br i1 %c3, label %bb134, label %meshBB396 bb134: ; preds = %bb131 unreachable @@ -64,16 +64,16 @@ ret void meshBB396: ; preds = %bb131, %bb15 - br i1 undef, label %bb135, label %bb22 + br i1 %c4, label %bb135, label %bb22 meshBB412: ; preds = %meshBB464 - br i1 undef, label %meshBB504, label %bb78 + br i1 %c5, label %meshBB504, label %bb78 meshBB424: ; preds = %meshBB464 - br i1 undef, label %poolStoreString.exit.thread, label %bb15 + br i1 %c6, label %poolStoreString.exit.thread, label %bb15 meshBB464: ; preds = %entry - br i1 undef, label %meshBB424, label %meshBB412 + br i1 %c7, label %meshBB424, label %meshBB412 meshBB472: ; preds = %meshBB504, %bb135 unreachable @@ -85,5 +85,5 @@ br label %meshBB540 meshBB540: ; preds = %meshBB520, %bb129 - br i1 undef, label %bb212, label %bb129 + br i1 %c8, label %bb212, label %bb129 } diff --git a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll --- a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll +++ b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll @@ -7,9 +7,9 @@ %struct.ui = type { ptr, ptr, i32, ptr, ptr, i64, ptr, ptr, ptr } -define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize) nounwind { +define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize, i1 %c0, i1 %c1, i1 %c2) nounwind { entry: - br i1 undef, label %bb1, label %bb + br i1 %c0, label %bb1, label %bb bb: ; preds = %entry unreachable @@ -21,13 +21,13 @@ %1 = getelementptr inbounds %struct.ui, ptr %0, i32 0, i32 5 %2 = load i64, ptr %1, align 4 %3 = call i32 @mo_create_nnm(ptr undef, i64 %2, ptr undef) nounwind - br i1 undef, label %bb3, label %bb2 + br i1 %c1, label %bb3, label %bb2 bb2: ; preds = %bb1 unreachable bb3: ; preds = %bb1 - br i1 undef, label %bb4, label %bb6 + br i1 %c2, label %bb4, label %bb6 bb4: ; preds = %bb3 %4 = call i32 @vn_size(ptr %vp, ptr %1, ptr undef) nounwind diff --git a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll --- a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll +++ b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll @@ -9,15 +9,15 @@ %struct.hc = type { i32, i32, i32, i32 } -define i32 @t(i32 %type) optsize { +define i32 @t(i32 %type, i1 %c0, i1 %c1, i1 %c2, i1 %c3) optsize { entry: - br i1 undef, label %if.then, label %if.else + br i1 %c0, label %if.then, label %if.else if.then: unreachable if.else: - br i1 undef, label %if.then15, label %if.else18 + br i1 %c1, label %if.then15, label %if.else18 if.then15: unreachable @@ -29,7 +29,7 @@ ] if.then102: - br i1 undef, label %cond.true10.i, label %t.exit + br i1 %c2, label %cond.true10.i, label %t.exit cond.true10.i: br label %t.exit @@ -38,7 +38,7 @@ unreachable if.then115: - br i1 undef, label %if.else163, label %if.else145 + br i1 %c3, label %if.else163, label %if.else145 if.else145: %call150 = call fastcc ptr @foo(ptr undef, i32 34865152) optsize diff --git a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll --- a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll +++ b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -2,10 +2,10 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" -define void @compdecomp() nounwind { +define void @compdecomp(i1 %c0) nounwind { entry: %heap = alloca [256 x i32], align 4 - br i1 undef, label %bb25.lr.ph, label %bb17 + br i1 %c0, label %bb25.lr.ph, label %bb17 bb17: ; preds = %bb17, %entry br label %bb17 diff --git a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll --- a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll +++ b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll @@ -10,7 +10,7 @@ declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind -define hidden fastcc i32 @sqlite3VdbeExec(ptr %p) nounwind { +define hidden fastcc i32 @sqlite3VdbeExec(ptr %p, i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind { entry: br label %sqlite3VarintLen.exit7424 @@ -18,21 +18,21 @@ br label %do.body.i do.body.i: ; preds = %do.body.i, %sqlite3VarintLen.exit7424 - br i1 undef, label %do.body.i, label %sqlite3VarintLen.exit + br i1 %c0, label %do.body.i, label %sqlite3VarintLen.exit sqlite3VarintLen.exit: ; preds = %do.body.i %sub2322 = add i64 undef, undef - br i1 undef, label %too_big, label %if.end2327 + br i1 %c1, label %too_big, label %if.end2327 if.end2327: ; preds = %sqlite3VarintLen.exit - br i1 undef, label %if.end2341, label %no_mem + br i1 %c2, label %if.end2341, label %no_mem if.end2341: ; preds = %if.end2327 br label %for.body2355 for.body2355: ; preds = %for.body2355, %if.end2341 %add2366 = add nsw i32 undef, undef - br i1 undef, label %for.body2377, label %for.body2355 + br i1 %c3, label %for.body2377, label %for.body2355 for.body2377: ; preds = %for.body2355 %conv23836154 = zext i32 %add2366 to i64 diff --git a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll --- a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -5,7 +5,7 @@ target triple = "thumbv7-apple-ios4.0.0" ; STATS-NOT: machine-sink -define i32 @foo(i32 %h, i32 %arg1) nounwind readonly ssp { +define i32 @foo(i32 %h, i32 %arg1, i1 %c0) nounwind readonly ssp { entry: br label %for.cond @@ -31,7 +31,7 @@ %abs = select i1 %cmp112, i32 %sub115, i32 %sub111 %add95 = add i32 %v.5, %v.8 %add117 = add i32 %add95, %abs - br i1 undef, label %for.cond, label %if.end299 + br i1 %c0, label %for.cond, label %if.end299 if.end299: ; preds = %for.body, %for.cond %s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ] diff --git a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll --- a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -3,9 +3,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target triple = "armv7-none-linux-gnueabi" -define arm_aapcs_vfpcc void @foo(ptr nocapture %arg) nounwind uwtable align 2 { +define arm_aapcs_vfpcc void @foo(ptr nocapture %arg, i1 %c0) nounwind uwtable align 2 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %c0, label %bb1, label %bb2 bb1: ; preds = %bb unreachable diff --git a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll --- a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -38,9 +38,9 @@ ret void } -define arm_aapcs_vfpcc void @foo2() nounwind uwtable { +define arm_aapcs_vfpcc void @foo2(i1 %c0) nounwind uwtable { entry: - br i1 undef, label %for.end, label %cond.end295 + br i1 %c0, label %for.end, label %cond.end295 cond.end295: ; preds = %entry %shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll --- a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -6,15 +6,15 @@ ; This test case exercises the MachineCopyPropagation pass by disabling the ; RegisterCoalescer. -define arm_aapcs_vfpcc void @foo(ptr %arg) nounwind uwtable align 2 { +define arm_aapcs_vfpcc void @foo(ptr %arg, i1 %c0, i1 %c1) nounwind uwtable align 2 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %c0, label %bb1, label %bb2 bb1: ; preds = %bb unreachable bb2: ; preds = %bb - br i1 undef, label %bb92, label %bb3 + br i1 %c1, label %bb92, label %bb3 bb3: ; preds = %bb2 %tmp = or <4 x i32> undef, undef diff --git a/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll b/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll --- a/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll +++ b/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll @@ -3,17 +3,17 @@ target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:32" target triple = "arm-none-linux" -define hidden void @_strtod_r() nounwind { - br i1 undef, label %1, label %2 +define hidden void @_strtod_r(i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind { + br i1 %c0, label %1, label %2 ;