[llvm/Target] Add Windows COFF support for RISC-V

[luojia]

Summary

RISC-V UEFI development requires to write output assembly into a PE/COFF object. This patch would allow RISC-V PE/COFF development when supplied Target requires binary format as COFF.

Although it's possible to llvm-objcopy from ELF to COFF, it will be more convenient to build directly into COFF files by selecting build targets, especially in languages like Rust where it would require amounts of work on more compilation steps in system development.

[jrtc27]

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

And please upload diffs with full context as per https://llvm.org/docs/DeveloperPolicy.html#making-and-submitting-a-patch

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

670

Isn't this available from the parent class's STI?

688

Can be after the if

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

97

Unnecessary churn

llvm/lib/Target/RISCV/MCTargetDesc/RISCVWinCOFFObjectWriter.cpp

33

static

39

Don't think this adds value... the backend would need extensive changes for RV128

53

This isn't actionable unless Microsoft gain an interest in Windows on RISC-V, so I don't think this is something we want to have a comment for as it's not possible to fix

55

This doesn't print its error message in NDEBUG builds, it's just __builtin_unreachable. I think you want report_fatal_error.

[luojia]

Update full-context diff.

[luojia]

Applied suggestions from @jrtc27.

[luojia]

In D145539#4176791, @jrtc27 wrote:

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration, or it will require following building steps (in this case, a objcopy step) where complex build frameworks like xtask would have to be used; it would also sometimes result in difference of output file paths where automatic tests (e.g. build a list of UEFI apps to test UEFI implementation) would be complex to develop.

And please upload diffs with full context as per https://llvm.org/docs/DeveloperPolicy.html#making-and-submitting-a-patch

Thanks! I'll do that.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

670

Thanks! I'll make STI protected in super class and use STI.getTargetTriple() on createObjectTargetWriter function.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

97

Thanks! Will remove.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVWinCOFFObjectWriter.cpp

33

modified to static unsigned

39

Yes. It's a note that future RV128 developers may need to change this part when they are adapting LLVM to RV128.

53

I'll modify comments to show that this is unlikely to happen.

55

Changed to report_fatal_error.

[jrtc27]

In D145539#4176824, @luojia wrote:

In D145539#4176791, @jrtc27 wrote:

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration

And how are you going to do that without a full PE/COFF specification for RISC-V?

[luojia]

In D145539#4176831, @jrtc27 wrote:

In D145539#4176824, @luojia wrote:

In D145539#4176791, @jrtc27 wrote:

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration

And how are you going to do that without a full PE/COFF specification for RISC-V?

Thanks for mentioning! If I am correct, PE/COFF specification has definitions of machine architecture in headers. In this part PE/COFF included RISC-V architecture types. It does not provide relocation types on RISC-V, so for now PE/COFF specification allows us to emit RISC-V COFF binaries without any relocations. This could be a use case for RISC-V UEFI applications where it's mainly statically linked without any relocations. If there are more demands on RISC-V PE/COFF which need relocations, the current PE/COFF specification will not support them and LLVM (after this patch) would raise fatal error instead.

I have limited information about RISC-V PE/COFF support as well; I don't know if other reviewers have different opinion about this part.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

688

Thanks! Modified.

[jrtc27]

In D145539#4176834, @luojia wrote:

In D145539#4176831, @jrtc27 wrote:

In D145539#4176824, @luojia wrote:

In D145539#4176791, @jrtc27 wrote:

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration

And how are you going to do that without a full PE/COFF specification for RISC-V?

Thanks for mentioning! If I am correct, PE/COFF specification has definitions of machine architecture in headers. In this part PE/COFF included RISC-V architecture types. It does not provide relocation types on RISC-V, so for now PE/COFF specification allows us to emit RISC-V COFF binaries without any relocations. This could be a use case for RISC-V UEFI applications where it's mainly statically linked without any relocations. If there are more demands on RISC-V PE/COFF which need relocations, the current PE/COFF specification will not support them and LLVM (after this patch) would raise fatal error instead.

I have limited information about RISC-V PE/COFF support as well; I don't know if other reviewers have different opinion about this part.

Well, you can't produce intermediate object files without relocations, and LLD can't read in an ELF and produce a PE/COFF, so I'm still not sure how static linking helps avoid the need for llvm-objcopy...

[MaskRay]

Although it's possible to llvm-objcopy from ELF to COFF

llvm-objcopy doesn't support this. GNU objcopy can convert an ELF file to a PE/COFF file, but the semantics are poorly defined.

[philipc]

In D145539#4176834, @luojia wrote:

If I am correct, PE/COFF specification has definitions of machine architecture in headers. In this part PE/COFF included RISC-V architecture types. It does not provide relocation types on RISC-V, so for now PE/COFF specification allows us to emit RISC-V COFF binaries without any relocations. This could be a use case for RISC-V UEFI applications where it's mainly statically linked without any relocations.

It's not true that the resulting UEFI application has no relocations. For example, when compiling to ELF and converting to PE/COFF, I had to convert a number of ELF relocations into PE base relocations: https://github.com/gimli-rs/object/blob/39e1bb37c613fd360a3b9b91c31d2d305945a5c4/crates/examples/src/bin/elftoefi.rs#L230-L268.

In D145539#4176837, @jrtc27 wrote:

Well, you can't produce intermediate object files without relocations, and LLD can't read in an ELF and produce a PE/COFF, so I'm still not sure how static linking helps avoid the need for llvm-objcopy...

What they are trying to do is add a RISCV UEFI target to the rust compiler that compiles to COFF intermediate object files and links to a PE/COFF UEFI application, similar to existing x86 and aarch64 UEFI targets, but this can't currently work because it would require defining RISCV relocations for the COFF intermediate object files.

llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMRISCVDesc
   RISCVAsmBackend.cpp
   RISCVBaseInfo.cpp
   RISCVELFObjectWriter.cpp
   RISCVInstPrinter.cpp
   RISCVMCAsmInfo.cpp
   RISCVMCCodeEmitter.cpp
   RISCVMCExpr.cpp
   RISCVMCObjectFileInfo.cpp
   RISCVMCTargetDesc.cpp
   RISCVMatInt.cpp
   RISCVTargetStreamer.cpp
   RISCVELFStreamer.cpp
+  RISCVWinCOFFObjectWriter.cpp
 
   LINK_COMPONENTS
   MC
   RISCVInfo
   Support
   TargetParser
 
   ADD_TO_COMPONENT
   RISCV
 )

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace llvm {
 class MCAssembler;
 class MCObjectTargetWriter;
 class raw_ostream;
 
 class RISCVAsmBackend : public MCAsmBackend {
-  const MCSubtargetInfo &STI;
-  uint8_t OSABI;
-  bool Is64Bit;
   bool ForceRelocs = false;
   const MCTargetOptions &TargetOptions;
 
+protected:
+  const MCSubtargetInfo &STI;
+
 public:
-  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
-                  const MCTargetOptions &Options)
-      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
-        TargetOptions(Options) {
+  RISCVAsmBackend(const MCSubtargetInfo &STI, const MCTargetOptions &Options)
+      : MCAsmBackend(support::little), TargetOptions(Options), STI(STI) {
     RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
   }
   ~RISCVAsmBackend() override = default;
 
   void setForceRelocs() { ForceRelocs = true; }
 
   // Return Size with extra Nop Bytes for alignment directive in code section.
   bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout,
                            const MCValue &Target, uint64_t &Value,
                            bool &WasForced) override;
 
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
 
-  std::unique_ptr<MCObjectTargetWriter>
-  createObjectTargetWriter() const override;
-
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
   }
public:
   bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout,
                           bool &WasRelaxed) const override;
   bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout,
                      bool &WasRelaxed) const override;
 
   bool writeNopData(raw_ostream &OS, uint64_t Count,
                     const MCSubtargetInfo *STI) const override;
 
   const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
 };
 }
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
   MCValue NopBytes = MCValue::get(Count);
 
   Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
                                    FixedValue);
 
   return true;
 }
 
+class ELFRISCVAsmBackend : public RISCVAsmBackend {
+  uint8_t OSABI;
+  bool Is64Bit;
+
+public:
+  ELFRISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
+                     const MCTargetOptions &Options)
+      : RISCVAsmBackend(STI, Options), OSABI(OSABI), Is64Bit(Is64Bit) {}
+
   std::unique_ptr<MCObjectTargetWriter>
-RISCVAsmBackend::createObjectTargetWriter() const {
+  createObjectTargetWriter() const override {
     return createRISCVELFObjectWriter(OSABI, Is64Bit);
   }
+};
+
+class COFFRISCVAsmBackend : public RISCVAsmBackend {
+public:
+  COFFRISCVAsmBackend(const MCSubtargetInfo &STI,
+                      const MCTargetOptions &Options)
+      : RISCVAsmBackend(STI, Options) {}
+
+  std::unique_ptr<MCObjectTargetWriter>
+  createObjectTargetWriter() const override {
+    return createRISCVWinCOFFObjectWriter(STI.getTargetTriple());
+  }
+};
 
 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   const Triple &TT = STI.getTargetTriple();
+
+  if (TT.isOSBinFormatCOFF())
+    return new COFFRISCVAsmBackend(STI, Options);
+
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
+
+  return new ELFRISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h

 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectTargetWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
+class Triple;
 
 MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                         MCContext &Ctx);
 
 MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
                                     const MCRegisterInfo &MRI,
                                     const MCTargetOptions &Options);
 
 std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
                                                                  bool Is64Bit);
+
+std::unique_ptr<MCObjectTargetWriter>
+createRISCVWinCOFFObjectWriter(const Triple &TheTriple);
 }
 
 // Defines symbolic names for RISC-V registers.
 #define GET_REGINFO_ENUM
 #include "RISCVGenRegisterInfo.inc"
 
 // Defines symbolic names for RISC-V instructions.
 #define GET_INSTRINFO_ENUM
 #define GET_INSTRINFO_MC_HELPER_DECLS
 #include "RISCVGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_ENUM
 #include "RISCVGenSubtargetInfo.inc"
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVWinCOFFObjectWriter.cpp

+//===-- RISCVWinCOFFObjectWriter.cpp - RISC-V Windows COFF Writer --------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "RISCVMCTargetDesc.h"
+#include "llvm/BinaryFormat/COFF.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/MC/MCWinCOFFObjectWriter.h"
+#include "llvm/Support/ErrorHandling.h"
+
+using namespace llvm;
+
+class RISCVWinCOFFObjectWriter : public MCWinCOFFObjectTargetWriter {
+public:
+  RISCVWinCOFFObjectWriter(const Triple &TheTriple);
+  ~RISCVWinCOFFObjectWriter() override = default;
+
+  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
+                        const MCFixup &Fixup, bool IsCrossSection,
+                        const MCAsmBackend &MAB) const override;
+};
+
+static unsigned RISCVWinCOFFMachineFromTriple(const Triple &TheTriple) {
+  if (TheTriple.isRISCV32()) {
+    return COFF::IMAGE_FILE_MACHINE_RISCV32;
+  } else if (TheTriple.isRISCV64()) {
+    return COFF::IMAGE_FILE_MACHINE_RISCV64;
+  } else {
+    // FIXME: once TheTriple.isRISCV128() is implemented,
+    // map it to COFF::IMAGE_FILE_MACHINE_RISCV128
+    llvm_unreachable("Unsupported triple for RISCVWinCOFFObjectWriter");
+  }
+}
+
+RISCVWinCOFFObjectWriter::RISCVWinCOFFObjectWriter(const Triple &TheTriple)
+    : MCWinCOFFObjectTargetWriter(RISCVWinCOFFMachineFromTriple(TheTriple)) {}
+
+unsigned RISCVWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
+                                                const MCValue &Target,
+                                                const MCFixup &Fixup,
+                                                bool IsCrossSection,
+                                                const MCAsmBackend &MAB) const {
+  // RISCV does not have Windows COFF relocation type definitions yet;
+  // Add getRelocType functions here once those types have a chance to be
+  // declared.
+  report_fatal_error(
+      "RISCV does not have Windows COFF relocation type definitions yet");
+}
+
+std::unique_ptr<MCObjectTargetWriter>
+llvm::createRISCVWinCOFFObjectWriter(const Triple &TheTriple) {
+  return std::make_unique<RISCVWinCOFFObjectWriter>(TheTriple);
+}

llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn

sources = [
     "RISCVInstPrinter.cpp",
     "RISCVMCAsmInfo.cpp",
     "RISCVMCCodeEmitter.cpp",
     "RISCVMCExpr.cpp",
     "RISCVMCObjectFileInfo.cpp",
     "RISCVMCTargetDesc.cpp",
     "RISCVMatInt.cpp",
     "RISCVTargetStreamer.cpp",
+    "RISCVWinCOFFObjectWriter.cpp",
   ]
 }