diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -942,13 +942,13 @@
 
 multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_UpperBound,
-                  ReadVRGatherVV_UpperBound, ReadVMask]>;
+           Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_data_UpperBound,
+                  ReadVRGatherVV_index_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVRGatherVX_UpperBound, ReadVRGatherVV_UpperBound,
+           Sched<[WriteVRGatherVX_UpperBound, ReadVRGatherVV_data_UpperBound,
                   ReadVRGatherVX_UpperBound, ReadVMask]>;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
-           Sched<[WriteVRGatherVI_UpperBound, ReadVRGatherVV_UpperBound,
+           Sched<[WriteVRGatherVI_UpperBound, ReadVRGatherVV_data_UpperBound,
                   ReadVMask]>;
 }
 
@@ -1662,8 +1662,8 @@
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>;
 def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
-                      Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_UpperBound,
-                             ReadVRGatherVV_UpperBound]>;
+                      Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_data_UpperBound,
+                             ReadVRGatherVV_index_UpperBound]>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
 
 // Vector Compress Instruction
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1988,7 +1988,8 @@
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
-    defvar ReadVRGatherVV_MX = !cast<SchedRead>("ReadVRGatherVV_" # mx);
+    defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
+    defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
 
     foreach sew = EEWList in {
       defvar octuple_lmul = m.octuple;
@@ -1998,8 +1999,8 @@
         defvar emulMX = octuple_to_str<octuple_emul>.ret;
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
         defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint>,
-                   Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_MX,
-                          ReadVRGatherVV_MX]>;
+                   Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
+                          ReadVRGatherVV_index_MX]>;
       }
     }
   }
@@ -2398,17 +2399,18 @@
     defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
     defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
     defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
-    defvar ReadVRGatherVV_MX = !cast<SchedRead>("ReadVRGatherVV_" # mx);
+    defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
+    defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
     defvar ReadVRGatherVX_MX = !cast<SchedRead>("ReadVRGatherVX_" # mx);
 
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_MX,
-                     ReadVRGatherVV_MX, ReadVMask]>;
+              Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
+                     ReadVRGatherVV_index_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVRGatherVX_MX, ReadVRGatherVV_MX,
+              Sched<[WriteVRGatherVX_MX, ReadVRGatherVV_data_MX,
                      ReadVRGatherVX_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVRGatherVI_MX, ReadVRGatherVV_MX, ReadVMask]>;
+              Sched<[WriteVRGatherVI_MX, ReadVRGatherVV_data_MX, ReadVMask]>;
   }
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -529,7 +529,8 @@
 defm "" : LMULSchedReads<"ReadVFSlideV">;
 defm "" : LMULSchedReads<"ReadVFSlideF">;
 // 16.4. Vector Register Gather Instructions
-defm "" : LMULSchedReads<"ReadVRGatherVV">;
+defm "" : LMULSchedReads<"ReadVRGatherVV_data">;
+defm "" : LMULSchedReads<"ReadVRGatherVV_index">;
 defm "" : LMULSchedReads<"ReadVRGatherVX">;
 // 16.5. Vector Compress Instruction
 defm "" : LMULSchedReads<"ReadVCompressV">;
@@ -879,7 +880,8 @@
 defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
 defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
 defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
-defm "" : LMULReadAdvance<"ReadVRGatherVV", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVV_index", 0>;
 defm "" : LMULReadAdvance<"ReadVRGatherVX", 0>;
 defm "" : LMULReadAdvance<"ReadVCompressV", 0>;
 // These are already LMUL aware