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[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV/FMA for scalable vector types.
Changes PlannedPublic

Authored by fakepaper56 on Mar 6 2023, 7:15 AM.

Details

Summary

It makes RISC-V serve llvm.experimental.constrained.*.

Diff Detail

Event Timeline

fakepaper56 created this revision.Mar 6 2023, 7:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 6 2023, 7:15 AM
fakepaper56 requested review of this revision.Mar 6 2023, 7:15 AM
craig.topper added inline comments.Mar 6 2023, 9:23 AM
llvm/test/CodeGen/RISCV/rvv/vfwadd-constrained-sdnode.ll
15

Shouldn't these be constrained.fpext?

17

Please use "fpexcept.strict"

fakepaper56 added inline comments.Mar 6 2023, 5:07 PM
llvm/test/CodeGen/RISCV/rvv/vfwadd-constrained-sdnode.ll
15

I think you are right. I misunderstand it.

fakepaper56 planned changes to this revision.Mar 6 2023, 6:12 PM