diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -1179,6 +1179,8 @@
 
     // Get the incoming value from the loop latch and check if the value has
     // the add form with the required increment.
+    if (CurrentPHINode->getBasicBlockIndex(LatchBB) < 0)
+      continue;
     if (Instruction *I = dyn_cast<Instruction>(
             CurrentPHINode->getIncomingValueForBlock(LatchBB))) {
       Value *StrippedBaseI = I;
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local void @test_no_inc(ptr nocapture noundef nonnull readnone align 1 dereferenceable(1) %this, ptr noundef nonnull align 1 dereferenceable(1) %j) local_unnamed_addr #0 align 2 {
+; CHECK-LABEL: test_no_inc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    stwu 1, -48(1)
+; CHECK-NEXT:    stw 0, 52(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    .cfi_offset lr, 4
+; CHECK-NEXT:    .cfi_offset r26, -24
+; CHECK-NEXT:    .cfi_offset r27, -20
+; CHECK-NEXT:    .cfi_offset r28, -16
+; CHECK-NEXT:    .cfi_offset r29, -12
+; CHECK-NEXT:    .cfi_offset r30, -8
+; CHECK-NEXT:    mfcr 12
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    stw 26, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 27, 28(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 28, 32(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 29, 36(1) # 4-byte Folded Spill
+; CHECK-NEXT:    mr 29, 4
+; CHECK-NEXT:    stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 12, 20(1)
+; CHECK-NEXT:    bl _ZN1e1fEv
+; CHECK-NEXT:    mr 30, 3
+; CHECK-NEXT:    mr 3, 29
+; CHECK-NEXT:    bl _ZN1e1iEv
+; CHECK-NEXT:    addi 29, 3, 1
+; CHECK-NEXT:    srawi 3, 30, 31
+; CHECK-NEXT:    cmpwi 2, 30, 0
+; CHECK-NEXT:    li 27, 1
+; CHECK-NEXT:    li 26, 0
+; CHECK-NEXT:    andc 28, 30, 3
+; CHECK-NEXT:    b .LBB0_2
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_1: # %for.cond.cleanup
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stbux 26, 29, 28
+; CHECK-NEXT:  .LBB0_2: # %for.cond
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 4, 9, .LBB0_1
+; CHECK-NEXT:  # %bb.3: # %for.body.preheader
+; CHECK-NEXT:    #
+; CHECK-NEXT:    addi 3, 29, 1
+; CHECK-NEXT:    li 4, 5
+; CHECK-NEXT:    mr 5, 30
+; CHECK-NEXT:    bl memset
+; CHECK-NEXT:    add 27, 30, 27
+; CHECK-NEXT:    b .LBB0_1
+entry:
+  %call = tail call noundef i32 @_ZN1e1fEv(ptr noundef nonnull align 1 dereferenceable(1) %j) #3
+  %call2 = tail call noundef ptr @_ZN1e1iEv(ptr noundef nonnull align 1 dereferenceable(1) %j) #3
+  %cmp10 = icmp sgt i32 %call, 0
+  %uglygep = getelementptr i8, ptr %call2, i32 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond.cleanup, %entry
+  %g.0 = phi i32 [ 1, %entry ], [ %g.1.lcssa, %for.cond.cleanup ]
+  br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:                               ; preds = %for.cond
+  %uglygep13 = getelementptr i8, ptr %uglygep, i32 %g.0
+  tail call void @llvm.memset.p0.i32(ptr align 1 %uglygep13, i8 5, i32 %call, i1 false)
+  %0 = add i32 %call, %g.0
+  br label %for.cond.cleanup
+
+for.cond.cleanup:                                 ; preds = %for.body.preheader, %for.cond
+  %g.1.lcssa = phi i32 [ %g.0, %for.cond ], [ %0, %for.body.preheader ]
+  %arrayidx5 = getelementptr inbounds i8, ptr %call2, i32 %g.1.lcssa
+  store i8 0, ptr %arrayidx5, align 1
+  br label %for.cond
+}
+
+declare noundef i32 @_ZN1e1fEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1
+
+declare noundef ptr @_ZN1e1iEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1
+
+declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) #2