diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -2067,3 +2067,51 @@ %shl = shl i32 2, %tz ret i32 %shl } + +; shift (X, amt | bitwidth - 1) -> shift (X, bitwidth - 1) +define i6 @shl_or7_eq_shl7(i6 %x, i6 %c) { +; CHECK-LABEL: @shl_or7_eq_shl7( +; CHECK-NEXT: [[AMT:%.*]] = or i6 [[C:%.*]], 5 +; CHECK-NEXT: [[Y:%.*]] = shl nsw i6 [[X:%.*]], [[AMT]] +; CHECK-NEXT: ret i6 [[Y]] +; + %amt = or i6 %c, 5 + ;; nsw not needed for transform, just check that we propegate. + %y = shl nsw i6 %x, %amt + ret i6 %y +} + +define <2 x i8> @lshr_vec_or7_eq_shl7(<2 x i8> %x, <2 x i8> %c) { +; CHECK-LABEL: @lshr_vec_or7_eq_shl7( +; CHECK-NEXT: [[AMT:%.*]] = or <2 x i8> [[C:%.*]], +; CHECK-NEXT: [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], [[AMT]] +; CHECK-NEXT: ret <2 x i8> [[Y]] +; + %amt = or <2 x i8> %c, + ;; exact not needed for transform, just check that we propegate. + %y = lshr exact <2 x i8> %x, %amt + ret <2 x i8> %y +} + +define <2 x i8> @ashr_vec_or7_eq_ashr7(<2 x i8> %x, <2 x i8> %c) { +; CHECK-LABEL: @ashr_vec_or7_eq_ashr7( +; CHECK-NEXT: [[AMT:%.*]] = or <2 x i8> [[C:%.*]], +; CHECK-NEXT: [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]] +; CHECK-NEXT: ret <2 x i8> [[Y]] +; + %amt = or <2 x i8> %c, + %y = ashr <2 x i8> %x, %amt + ret <2 x i8> %y +} + +; Negative test not bitwidth - 1 +define <2 x i8> @ashr_vec_or6_fail(<2 x i8> %x, <2 x i8> %c) { +; CHECK-LABEL: @ashr_vec_or6_fail( +; CHECK-NEXT: [[AMT:%.*]] = or <2 x i8> [[C:%.*]], +; CHECK-NEXT: [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]] +; CHECK-NEXT: ret <2 x i8> [[Y]] +; + %amt = or <2 x i8> %c, + %y = ashr <2 x i8> %x, %amt + ret <2 x i8> %y +}