diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll @@ -1089,7 +1089,7 @@ ; Check that with 2 jump tables, the phi node doesn't lose the edge from the ; second one. -define void @jt_2_tables_phi_edge_from_second() { +define void @jt_2_tables_phi_edge_from_second(i1 %replace_undef_0) { ; CHECK-LABEL: name: jt_2_tables_phi_edge_from_second ; CHECK: bb.1.entry: ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF @@ -1309,7 +1309,7 @@ land.rhs.lr.ph: ; preds = %sw.bb12.i, %sw.bb9.i, %sw.bb8.i, %sw.bb7.i, %sw.bb6.i, %sw.bb4.i, %sw.bb1.i, %sw.bb14.i48 %retval.0.i.ph = phi i32 [ 0, %sw.bb14.i48 ], [ 1, %sw.bb1.i ], [ 4, %sw.bb4.i ], [ 6, %sw.bb6.i ], [ 7, %sw.bb7.i ], [ 8, %sw.bb8.i ], [ 9, %sw.bb9.i ], [ 12, %sw.bb12.i ] - br i1 undef, label %while.body, label %while.end + br i1 %replace_undef_0, label %while.body, label %while.end while.body: ; preds = %land.rhs.lr.ph call void @jt_2_tables_phi_edge_from_second() diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll @@ -7,8 +7,8 @@ ; Check that we don't crash when we have a metadata use of %i not being dominated by the def. ; CHECK-LABEL: @foo ; CHECK: DBG_VALUE %1:_(p0), $noreg, !370, !DIExpression(DW_OP_LLVM_fragment, 0, 64) -define hidden void @foo() unnamed_addr #1 !dbg !230 { - br i1 undef, label %bb4, label %bb5 +define hidden void @foo(i1 %replace_undef_0) unnamed_addr #1 !dbg !230 { + br i1 %replace_undef_0, label %bb4, label %bb5 bb4: ; preds = %bb3 %i = extractvalue { ptr, i64 } undef, 0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll @@ -4,7 +4,7 @@ ; Make sure that we don't duplicate successors/predecessors when translating ; indirectbr instructions with duplicate block labels. -define void @foo() { +define void @foo(i1 %replace_undef_0) { ; CHECK-LABEL: name: foo ; CHECK: bb.1 (%ir-block.0): ; CHECK: successors: %bb.2(0x2aaaaaaa), %bb.4(0x2aaaaaaa), %bb.3(0x2aaaaaaa) @@ -16,7 +16,7 @@ ; CHECK: successors: ; CHECK: bb.4 (%ir-block.3): ; CHECK: RET_ReallyLR - indirectbr ptr undef, [label %1, label %3, label %2, label %3, label %3] + indirectbr ptr %replace_undef_0, [label %1, label %3, label %2, label %3, label %3] 1: unreachable 2: diff --git a/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll b/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll --- a/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll @@ -2,7 +2,7 @@ ; PR20188: don't crash when merging sexts. ; CHECK: foo: -define void @foo() unnamed_addr align 2 { +define void @foo(i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2) unnamed_addr align 2 { entry: br label %invoke.cont145 @@ -12,7 +12,7 @@ if.then274: %0 = load i32, ptr null, align 4 - br i1 undef, label %invoke.cont291, label %if.else313 + br i1 %replace_undef_0, label %invoke.cont291, label %if.else313 invoke.cont291: %idxprom.i.i.i605 = sext i32 %0 to i64 @@ -26,7 +26,7 @@ br i1 %cmp314, label %invoke.cont317, label %invoke.cont353 invoke.cont317: - br i1 undef, label %invoke.cont326, label %invoke.cont334 + br i1 %replace_undef_1, label %invoke.cont326, label %invoke.cont334 invoke.cont326: %idxprom.i.i.i587 = sext i32 %0 to i64 @@ -36,7 +36,7 @@ invoke.cont334: %lo.1 = phi double [ %sub329, %invoke.cont326 ], [ undef, %invoke.cont317 ] - br i1 undef, label %invoke.cont342, label %if.end356 + br i1 %replace_undef_2, label %invoke.cont342, label %if.end356 invoke.cont342: %idxprom.i.i.i578 = sext i32 %0 to i64 diff --git a/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll b/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll --- a/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll @@ -3,15 +3,15 @@ ; Can't copy or spill / restore CPSR. ; rdar://9105206 -define fastcc void @t() ssp align 2 { +define fastcc void @t(i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2, i1 %replace_undef_3, i1 %replace_undef_4) ssp align 2 { entry: - br i1 undef, label %bb3.i, label %bb2.i + br i1 %replace_undef_0, label %bb3.i, label %bb2.i bb2.i: ; preds = %entry br label %bb3.i bb3.i: ; preds = %bb2.i, %entry - br i1 undef, label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71, label %bb.i69 + br i1 %replace_undef_1, label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71, label %bb.i69 bb.i69: ; preds = %bb3.i br label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71 @@ -22,10 +22,10 @@ %2 = fcmp ult float %1, 0xBF847AE140000000 %storemerge9 = select i1 %2, float %1, float 0.000000e+00 store float %storemerge9, ptr undef, align 4 - br i1 undef, label %bb42, label %bb47 + br i1 %replace_undef_2, label %bb42, label %bb47 bb42: ; preds = %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71 - br i1 undef, label %bb46, label %bb53 + br i1 %replace_undef_3, label %bb46, label %bb53 bb46: ; preds = %bb42 br label %bb48 @@ -34,7 +34,7 @@ br label %bb48 bb48: ; preds = %bb47, %bb46 - br i1 undef, label %bb1.i14, label %bb.i13 + br i1 %replace_undef_4, label %bb1.i14, label %bb.i13 bb.i13: ; preds = %bb48 br label %bb1.i14 diff --git a/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll @@ -5,10 +5,10 @@ source_filename = "test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll" ; Function Attrs: nounwind ssp -define void @drt_vsprintf() #0 { +define void @drt_vsprintf(i1 %replace_undef_0) #0 { entry: %do_tab_convert = alloca i32, align 4 - br i1 undef, label %if.then24, label %if.else295, !dbg !11 + br i1 %replace_undef_0, label %if.then24, label %if.else295, !dbg !11 if.then24: ; preds = %entry unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll b/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll --- a/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll @@ -3,7 +3,7 @@ ; CPSR is not allocatable so fast allocatable wouldn't mark them killed. ; rdar://9313272 -define hidden void @t() nounwind { +define hidden void @t(i1 %replace_undef_0) nounwind { entry: %cmp = icmp eq ptr null, undef %frombool = zext i1 %cmp to i8 @@ -16,7 +16,7 @@ unreachable if.end: ; preds = %entry - br i1 undef, label %land.lhs.true14, label %if.end33 + br i1 %replace_undef_0, label %land.lhs.true14, label %if.end33 land.lhs.true14: ; preds = %if.end unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll b/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll @@ -5,12 +5,12 @@ ; cycles in DAGs, and eventually crashes. This is the testcase for ; one of those crashes. (rdar://10653656) -define void @test(i1 zeroext %IsArrow) nounwind ssp align 2 { +define void @test(i1 zeroext %IsArrow, i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2, i1 %replace_undef_3) nounwind ssp align 2 { entry: - br i1 undef, label %return, label %lor.lhs.false + br i1 %replace_undef_0, label %return, label %lor.lhs.false lor.lhs.false: - br i1 undef, label %return, label %if.end + br i1 %replace_undef_1, label %return, label %if.end if.end: %tmp.i = load i64, ptr undef, align 8 @@ -18,7 +18,7 @@ br i1 %IsArrow, label %if.else_crit_edge, label %if.end32 if.else_crit_edge: - br i1 undef, label %if.end32, label %return + br i1 %replace_undef_2, label %if.end32, label %return if.end32: %0 = icmp ult i32 undef, 3 @@ -27,7 +27,7 @@ %.pn = shl i320 %1, %.pn.v %ins346392 = or i320 %.pn, 0 store i320 %ins346392, ptr undef, align 8 - br i1 undef, label %sw.bb.i.i, label %exit + br i1 %replace_undef_3, label %sw.bb.i.i, label %exit sw.bb.i.i: unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll b/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll --- a/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll @@ -15,18 +15,18 @@ declare noalias ptr @xstrdup(ptr) optsize -define ptr @dyld_fix_path(ptr %path) nounwind optsize ssp { +define ptr @dyld_fix_path(ptr %path, i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2, i1 %replace_undef_3) nounwind optsize ssp { entry: - br i1 undef, label %if.end56, label %for.cond + br i1 %replace_undef_0, label %if.end56, label %for.cond for.cond: ; preds = %entry - br i1 undef, label %for.cond10, label %for.body + br i1 %replace_undef_1, label %for.cond10, label %for.body for.body: ; preds = %for.cond unreachable for.cond10: ; preds = %for.cond - br i1 undef, label %if.end56, label %for.body14 + br i1 %replace_undef_2, label %if.end56, label %for.body14 for.body14: ; preds = %for.cond10 %call22 = tail call i64 @strlen(ptr undef) nounwind optsize @@ -38,7 +38,7 @@ %sext59 = add i64 %add31, 4294967296 %conv33 = ashr exact i64 %sext59, 32 %call34 = tail call noalias ptr @xmalloc(i64 %conv33) nounwind optsize - br i1 undef, label %cond.false45, label %cond.true43 + br i1 %replace_undef_3, label %cond.false45, label %cond.true43 cond.true43: ; preds = %for.body14 unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -mtriple=arm64-eabi ; Make sure we are not crashing on this test. -define void @autogen_SD13158() { +define void @autogen_SD13158(i1 %replace_undef_0, i1 %replace_undef_1) { entry: %B26 = frem float 0.000000e+00, undef - br i1 undef, label %CF, label %CF77 + br i1 %replace_undef_0, label %CF, label %CF77 CF: ; preds = %CF, %CF76 store float %B26, ptr undef - br i1 undef, label %CF, label %CF77 + br i1 %replace_undef_1, label %CF, label %CF77 CF77: ; preds = %CF ret void diff --git a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll @@ -2,13 +2,13 @@ ; Make sure we are not crashing on this test. -define void @autogen_SD12881() { +define void @autogen_SD12881(i1 %replace_undef_0) { BB: %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer br label %CF CF: ; preds = %CF83, %CF, %BB - br i1 undef, label %CF, label %CF83 + br i1 %replace_undef_0, label %CF, label %CF83 CF83: ; preds = %CF %FC70 = sitofp <4 x i32> %B17 to <4 x double> @@ -16,13 +16,13 @@ } -define void @autogen_SD12881_2() { +define void @autogen_SD12881_2(i1 %replace_undef_0) { BB: %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer br label %CF CF: ; preds = %CF83, %CF, %BB - br i1 undef, label %CF, label %CF83 + br i1 %replace_undef_0, label %CF, label %CF83 CF83: ; preds = %CF %FC70 = uitofp <4 x i32> %B17 to <4 x double> diff --git a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll --- a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll +++ b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll @@ -986,7 +986,7 @@ ; The following test excercises the case where we have a BFI ; instruction with the same input in both operands. We need to ; track the useful bits through both operands. -define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr) { +define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr, i1 %replace_undef_0) { ; LLC-LABEL: sameOperandBFI: ; LLC: // %bb.0: // %entry ; LLC-NEXT: cbnz wzr, .LBB30_2 @@ -1002,7 +1002,7 @@ ; OPT-NEXT: entry: ; OPT-NEXT: [[SHR47:%.*]] = lshr i64 [[SRC:%.*]], 47 ; OPT-NEXT: [[SRC2_TRUNC:%.*]] = trunc i64 [[SRC2:%.*]] to i32 -; OPT-NEXT: br i1 undef, label [[END:%.*]], label [[IF_ELSE:%.*]] +; OPT-NEXT: br i1 [[%replace_undef_0:%.*]], label [[END:%.*]], label [[IF_ELSE:%.*]] ; OPT: if.else: ; OPT-NEXT: [[AND3:%.*]] = and i32 [[SRC2_TRUNC]], 3 ; OPT-NEXT: [[SHL2:%.*]] = shl nuw nsw i64 [[SHR47]], 2 @@ -1019,7 +1019,7 @@ entry: %shr47 = lshr i64 %src, 47 %src2.trunc = trunc i64 %src2 to i32 - br i1 undef, label %end, label %if.else + br i1 %replace_undef_0, label %end, label %if.else if.else: %and3 = and i32 %src2.trunc, 3 diff --git a/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll b/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll --- a/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll +++ b/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll @@ -36,12 +36,12 @@ ret float %tmp } -define void @t7() nounwind { +define void @t7(i1 %replace_undef_0) nounwind { ; CHECK-LABEL: t7: ; CHECK: b _foo ; CHECK: b _bar - br i1 undef, label %bb, label %bb1.lr.ph + br i1 %replace_undef_0, label %bb, label %bb1.lr.ph bb1.lr.ph: ; preds = %entry tail call void @bar() nounwind diff --git a/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll b/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll --- a/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll +++ b/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll @@ -662,9 +662,9 @@ @.str.89 = external unnamed_addr constant [12 x i8], align 1 @.str.90 = external unnamed_addr constant [5 x i8], align 1 ; CHECK-LABEL: test_r274582 -define void @test_r274582(double %x) { +define void @test_r274582(double %x, i1 %replace_undef_0) { entry: - br i1 undef, label %if.then.i, label %if.end.i + br i1 %replace_undef_0, label %if.then.i, label %if.end.i if.then.i: ret void if.end.i: diff --git a/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll b/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll --- a/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll @@ -8,14 +8,14 @@ ; ; -define void @testcase() { +define void @testcase(i1 %replace_undef_0) { ; CHECK: testcase: ; CHECK-NOT: orr xzr, xzr, #0x2 bb1: %tmp1 = tail call float @ceilf(float 2.000000e+00) %tmp2 = fptoui float %tmp1 to i64 - br i1 undef, label %bb2, label %bb3 + br i1 %replace_undef_0, label %bb2, label %bb3 bb2: tail call void @foo() diff --git a/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll b/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll --- a/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll +++ b/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll @@ -395,13 +395,13 @@ ; This function from 175.vpr folds an ADDWri into a CSINC. ; Remember to clear the kill flag on the ADDWri. -define i32 @get_ytrack_to_xtracks() nounwind ssp { +define i32 @get_ytrack_to_xtracks(i1 %replace_undef_0, i1 %replace_undef_1) nounwind ssp { entry: br label %for.body for.body: %x0 = load i32, ptr undef, align 4 - br i1 undef, label %if.then.i146, label %is_sbox.exit155 + br i1 %replace_undef_0, label %if.then.i146, label %is_sbox.exit155 if.then.i146: %add8.i143 = add nsw i32 0, %x0 @@ -414,7 +414,7 @@ %idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64 %arrayidx18.i154 = getelementptr inbounds i32, ptr null, i64 %idxprom15.i152 %x1 = load i32, ptr %arrayidx18.i154, align 4 - br i1 undef, label %for.body51, label %for.body + br i1 %replace_undef_1, label %for.body51, label %for.body for.body51: ; preds = %is_sbox.exit155 call fastcc void @get_switch_type(i32 %x1, i32 undef, i16 signext undef, i16 signext undef, ptr undef) diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll @@ -118,14 +118,14 @@ declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) -define void @logicalReg() { +define void @logicalReg(i1 %replace_undef_0) { ; Make sure we generate a logical reg = reg, reg instruction without any ; machine verifier errors. ; CHECK-LABEL: logicalReg: ; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}} ; CHECK: ret entry: - br i1 undef, label %cond.end, label %cond.false + br i1 %replace_undef_0, label %cond.end, label %cond.false cond.false: %cond = select i1 undef, i1 true, i1 false diff --git a/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll b/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll --- a/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll +++ b/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll @@ -755,7 +755,7 @@ ; should return gracefully and continue compilation. ; The only condition for this test is the compilation finishes correctly. ; -define void @infiniteloop() { +define void @infiniteloop(i1 %replace_undef_0) { ; ENABLE-LABEL: infiniteloop: ; ENABLE: ; %bb.0: ; %entry ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill @@ -812,7 +812,7 @@ ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ret entry: - br i1 undef, label %if.then, label %if.end + br i1 %replace_undef_0, label %if.then, label %if.end if.then: %ptr = alloca i32, i32 4 @@ -830,7 +830,7 @@ } ; Another infinite loop test this time with a body bigger than just one block. -define void @infiniteloop2() { +define void @infiniteloop2(i1 %replace_undef_0, i1 %replace_undef_1) { ; ENABLE-LABEL: infiniteloop2: ; ENABLE: ; %bb.0: ; %entry ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill @@ -899,7 +899,7 @@ ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ret entry: - br i1 undef, label %if.then, label %if.end + br i1 %replace_undef_0, label %if.then, label %if.end if.then: %ptr = alloca i32, i32 4 @@ -910,7 +910,7 @@ %call = tail call i32 asm "mov $0, #0", "=r,~{x19}"() %add = add nsw i32 %call, %sum.03 store i32 %add, ptr %ptr - br i1 undef, label %body1, label %body2 + br i1 %replace_undef_1, label %body1, label %body2 body1: tail call void asm sideeffect "nop", "~{x19}"() @@ -925,7 +925,7 @@ } ; Another infinite loop test this time with two nested infinite loop. -define void @infiniteloop3() { +define void @infiniteloop3(i1 %replace_undef_0, i1 %replace_undef_1) { ; ENABLE-LABEL: infiniteloop3: ; ENABLE: ; %bb.0: ; %entry ; ENABLE-NEXT: cbnz wzr, LBB12_5 @@ -974,10 +974,10 @@ ; DISABLE-NEXT: LBB12_5: ; %end ; DISABLE-NEXT: ret entry: - br i1 undef, label %loop2a, label %body + br i1 %replace_undef_0, label %loop2a, label %body body: ; preds = %entry - br i1 undef, label %loop2a, label %end + br i1 %replace_undef_1, label %loop2a, label %end loop1: ; preds = %loop2a, %loop2b %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ] diff --git a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll --- a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll +++ b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll @@ -14,12 +14,12 @@ @q = external dso_local unnamed_addr global ptr, align 8 ; Function Attrs: nounwind -define void @test() local_unnamed_addr #0 { +define void @test(i1 %replace_undef_0) local_unnamed_addr #0 { entry: br label %for.body453.i for.body453.i: ; preds = %for.body453.i, %entry - br i1 undef, label %for.body453.i, label %for.end705.i + br i1 %replace_undef_0, label %for.body453.i, label %for.end705.i for.end705.i: ; preds = %for.body453.i %0 = load ptr, ptr @q, align 8 diff --git a/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll b/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll --- a/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll +++ b/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll @@ -7,16 +7,16 @@ ; that case, the machine verifier, which relies on analyzing branches for this ; kind of verification, is unable to check anything, so accepts the CFG. -define void @test_branch_to_landingpad() personality ptr @__objc_personality_v0 { +define void @test_branch_to_landingpad(i1 %replace_undef_0, i1 %replace_undef_1) personality ptr @__objc_personality_v0 { entry: - br i1 undef, label %if.end50.thread, label %if.then6 + br i1 %replace_undef_0, label %if.end50.thread, label %if.then6 lpad: %0 = landingpad { ptr, i32 } catch ptr @"OBJC_EHTYPE_$_NSString" catch ptr @OBJC_EHTYPE_id catch ptr null - br i1 undef, label %invoke.cont33, label %catch.fallthrough + br i1 %replace_undef_1, label %invoke.cont33, label %catch.fallthrough catch.fallthrough: %matches31 = icmp eq i32 undef, 0 diff --git a/llvm/test/CodeGen/AArch64/br-undef-cond.ll b/llvm/test/CodeGen/AArch64/br-undef-cond.ll --- a/llvm/test/CodeGen/AArch64/br-undef-cond.ll +++ b/llvm/test/CodeGen/AArch64/br-undef-cond.ll @@ -7,13 +7,13 @@ declare void @bar(ptr) -define void @foo(ptr %m, i32 %off0) { +define void @foo(ptr %m, i32 %off0, i1 %replace_undef_0, i1 %replace_undef_1) { .thread1653: - br i1 undef, label %0, label %.thread1880 + br i1 %replace_undef_0, label %0, label %.thread1880 %1 = icmp eq i32 undef, 0 %.not = xor i1 %1, true - %brmerge = or i1 %.not, undef + %brmerge = or i1 %.not, %replace_undef_1 br i1 %brmerge, label %.thread1880, label %.thread1705 .thread1705: diff --git a/llvm/test/CodeGen/AArch64/gep-nullptr.ll b/llvm/test/CodeGen/AArch64/gep-nullptr.ll --- a/llvm/test/CodeGen/AArch64/gep-nullptr.ll +++ b/llvm/test/CodeGen/AArch64/gep-nullptr.ll @@ -6,9 +6,9 @@ %unionMV = type { i32 } ; Function Attrs: nounwind -define void @test(ptr %mi_block) { +define void @test(ptr %mi_block, i1 %replace_undef_0) { entry: - br i1 undef, label %for.body13.us, label %if.else + br i1 %replace_undef_0, label %for.body13.us, label %if.else ; Just make sure we don't get a compiler ICE due to dereferncing a nullptr. ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll b/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll --- a/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll @@ -1,12 +1,12 @@ ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; CHECK-LABEL: foo: ; CHECK: TEST .Ltmp0 -define void @foo() { +define void @foo(i1 %replace_undef_0) { entry: br label %bar bar: call void asm sideeffect "#TEST $0", "i,~{dirflag},~{fpsr},~{flags}"(ptr blockaddress(@foo, %bar)) ret void indirectgoto: - indirectbr ptr undef, [label %bar] + indirectbr ptr %replace_undef_0, [label %bar] } diff --git a/llvm/test/CodeGen/AArch64/madd-combiner.ll b/llvm/test/CodeGen/AArch64/madd-combiner.ll --- a/llvm/test/CodeGen/AArch64/madd-combiner.ll +++ b/llvm/test/CodeGen/AArch64/madd-combiner.ll @@ -26,7 +26,7 @@ } ; bugpoint reduced test case. This only tests that we pass the MI verifier. -define void @mul_add_imm2() { +define void @mul_add_imm2(i1 %replace_undef_0) { ; CHECK-ISEL-LABEL: mul_add_imm2: ; CHECK-ISEL: ; %bb.0: ; %entry ; CHECK-ISEL-NEXT: mov w8, #1 @@ -53,7 +53,7 @@ entry: br label %for.body for.body: - br i1 undef, label %for.body, label %for.body8 + br i1 %replace_undef_0, label %for.body, label %for.body8 for.body8: %0 = mul i64 undef, -3 %mul1971 = add i64 %0, -3 diff --git a/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll b/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll --- a/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll +++ b/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll @@ -10,7 +10,7 @@ ; formed in SelectionDAG, optimizeCondBranch() only triggers if the and ; instruction is in a different block than the conditional jump. -define void @func() uwtable { +define void @func(i1 %replace_undef_0) uwtable { ; CHECK-LABEL: func: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #1 @@ -43,7 +43,7 @@ br i1 %c0, label %b1, label %b6 b1: - br i1 undef, label %b3, label %b2 + br i1 %replace_undef_0, label %b3, label %b2 b2: %v0 = tail call i32 @extfunc() diff --git a/llvm/test/CodeGen/AArch64/shrink-wrap.ll b/llvm/test/CodeGen/AArch64/shrink-wrap.ll --- a/llvm/test/CodeGen/AArch64/shrink-wrap.ll +++ b/llvm/test/CodeGen/AArch64/shrink-wrap.ll @@ -31,7 +31,7 @@ declare fastcc i32 @bar() -define internal fastcc i32 @func(i32 %alpha, i32 %beta) { +define internal fastcc i32 @func(i32 %alpha, i32 %beta, i1 %replace_undef_0) { entry: %v1 = alloca [2 x [11 x i32]], align 4 %v2 = alloca [11 x i32], align 16 @@ -69,7 +69,7 @@ %a.0983 = phi i32 [ 1, %if.end.9 ], [ %a.1, %for.inc ] %arrayidx = getelementptr inbounds [62 x i32], ptr @g17, i64 0, i64 undef %tmp5 = load i32, ptr %arrayidx, align 4 - br i1 undef, label %for.inc, label %if.else.51 + br i1 %replace_undef_0, label %for.inc, label %if.else.51 if.else.51: %idxprom53 = sext i32 %tmp5 to i64 diff --git a/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll b/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll --- a/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll +++ b/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll @@ -6,10 +6,10 @@ ; the attributes of the caller and the callee match. declare zeroext i1 @zcallee() -define void @zcaller() { +define void @zcaller(i1 %replace_undef_0) { ; CHECK-LABEL: name: zcaller entry: - br i1 undef, label %calllabel, label %retlabel + br i1 %replace_undef_0, label %calllabel, label %retlabel calllabel: ; CHECK: bb.1.calllabel: ; CHECK-NOT: BL @zcallee @@ -21,10 +21,10 @@ } declare signext i1 @scallee() -define void @scaller() { +define void @scaller(i1 %replace_undef_0) { ; CHECK-LABEL: name: scaller entry: - br i1 undef, label %calllabel, label %retlabel + br i1 %replace_undef_0, label %calllabel, label %retlabel calllabel: ; CHECK: bb.1.calllabel: ; CHECK-NOT: BL @scallee diff --git a/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll b/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll --- a/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=arm64-apple-ios %s -o - | FileCheck %s -define swifttailcc void @foo(ptr %call) ssp { +define swifttailcc void @foo(ptr %call, i1 %replace_undef_0) ssp { ; CHECK-LABEL: foo: %var = alloca [28 x i8], align 16 - br i1 undef, label %if.then, label %if.end + br i1 %replace_undef_0, label %if.then, label %if.end if.then: ret void