diff --git a/llvm/test/Analysis/BasicAA/phi-values-usage.ll b/llvm/test/Analysis/BasicAA/phi-values-usage.ll --- a/llvm/test/Analysis/BasicAA/phi-values-usage.ll +++ b/llvm/test/Analysis/BasicAA/phi-values-usage.ll @@ -20,10 +20,10 @@ ; This function is one where if we didn't free basicaa after memcpyopt then the ; usage of basicaa in instcombine would cause a segfault due to stale phi-values ; results being used. -define void @fn(ptr %this, ptr %ptr) personality ptr @__gxx_personality_v0 { +define void @fn(ptr %this, ptr %ptr, i1 %replaceUndef0) personality ptr @__gxx_personality_v0 { entry: %arr = alloca [4 x i8], align 8 - br i1 undef, label %then, label %if + br i1 %replaceUndef0, label %then, label %if if: br label %then @@ -50,7 +50,7 @@ ; When running instcombine after memdep, the basicaa used by instcombine uses ; the phivalues that memdep used. This would then cause a segfault due to ; instcombine deleting a phi whose values had been cached. -define void @fn2() { +define void @fn2( i1 %replaceUndef0) { entry: %a = alloca i8, align 1 %0 = load ptr, ptr @c, align 1 @@ -58,7 +58,7 @@ for.cond: ; preds = %for.body, %entry %d.0 = phi ptr [ %0, %entry ], [ null, %for.body ] - br i1 undef, label %for.body, label %for.cond.cleanup + br i1 %replaceUndef0, label %for.body, label %for.cond.cleanup for.body: ; preds = %for.cond store volatile i8 undef, ptr %a, align 1 diff --git a/llvm/test/Analysis/BasicAA/underlying-value.ll b/llvm/test/Analysis/BasicAA/underlying-value.ll --- a/llvm/test/Analysis/BasicAA/underlying-value.ll +++ b/llvm/test/Analysis/BasicAA/underlying-value.ll @@ -3,12 +3,12 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -define void @func_20() nounwind { +define void @func_20( i1 %replaceUndef0) nounwind { entry: br label %for.cond for.cond: ; preds = %for.cond2, %entry - br i1 undef, label %for.cond2, label %for.end22 + br i1 %replaceUndef0, label %for.cond2, label %for.end22 for.cond2: ; preds = %for.body5, %for.cond br i1 false, label %for.body5, label %for.cond diff --git a/llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll b/llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll --- a/llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll +++ b/llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll @@ -3,10 +3,10 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @fn1(i32* %f) { +define void @fn1(i32* %f, i1 %replaceUndef0, i1 %replaceUndef1) { entry: %tobool7 = icmp eq i32 undef, 0 - br i1 undef, label %if.end.12, label %for.body.5 + br i1 %replaceUndef0, label %if.end.12, label %for.body.5 for.inc: store i32 undef, i32* %f, align 4 @@ -19,7 +19,7 @@ br i1 %tobool7, label %for.inc.9.1, label %for.inc if.end.12: ; preds = %if.end.12, %for.body - br i1 undef, label %for.end.17, label %for.inc + br i1 %replaceUndef1, label %for.end.17, label %for.inc for.end.17: ; preds = %entry ret void diff --git a/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll b/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll --- a/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll +++ b/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll @@ -8,7 +8,7 @@ ; Even though the likeliness of 'invoke' to throw an exception is assessed as low ; all other paths are even less likely. Check that hot paths leads to excepion handler. -define void @test1(i32 %0) personality ptr @"personality_function" !prof !1 { +define void @test1(i32 %0, i1 %replaceUndef0) personality ptr @"personality_function" !prof !1 { ;CHECK: edge entry -> unreached probability is 0x00000001 / 0x80000000 = 0.00% ;CHECK: edge entry -> invoke probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge] ;CHECK: edge invoke -> invoke.cont.unreached probability is 0x00000000 / 0x80000000 = 0.00% @@ -16,7 +16,7 @@ ;CHECK: edge land.pad -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %unreached, label %invoke, !prof !2 + br i1 %replaceUndef0, label %unreached, label %invoke, !prof !2 invoke: invoke void @foo(i32 %0) to label %invoke.cont.unreached unwind label %land.pad @@ -38,7 +38,7 @@ ret void } -define void @test2(i32 %0) personality ptr @"personality_function" { +define void @test2(i32 %0, i1 %replaceUndef0) personality ptr @"personality_function" { ;CHECK: edge entry -> unreached probability is 0x00000000 / 0x80000000 = 0.00% ;CHECK: edge entry -> invoke probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] ;CHECK: edge invoke -> invoke.cont.cold probability is 0x7fff8000 / 0x80000000 = 100.00% [HOT edge] @@ -46,7 +46,7 @@ ;CHECK: edge land.pad -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %unreached, label %invoke + br i1 %replaceUndef0, label %unreached, label %invoke invoke: invoke void @foo(i32 %0) to label %invoke.cont.cold unwind label %land.pad @@ -68,14 +68,14 @@ ret void } -define void @test3(i32 %0) personality ptr @"personality_function" { +define void @test3(i32 %0, i1 %replaceUndef0) personality ptr @"personality_function" { ;CHECK: edge entry -> unreached probability is 0x00000000 / 0x80000000 = 0.00% ;CHECK: edge entry -> invoke probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] ;CHECK: edge invoke -> invoke.cont.cold probability is 0x7fff8000 / 0x80000000 = 100.00% [HOT edge] ;CHECK: edge invoke -> land.pad probability is 0x00008000 / 0x80000000 = 0.00% ;CHECK: edge land.pad -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %unreached, label %invoke + br i1 %replaceUndef0, label %unreached, label %invoke invoke: invoke void @foo(i32 %0) to label %invoke.cont.cold unwind label %land.pad diff --git a/llvm/test/Analysis/BranchProbabilityInfo/loop.ll b/llvm/test/Analysis/BranchProbabilityInfo/loop.ll --- a/llvm/test/Analysis/BranchProbabilityInfo/loop.ll +++ b/llvm/test/Analysis/BranchProbabilityInfo/loop.ll @@ -523,7 +523,7 @@ ; If loop has single exit and it leads to 'cold' block then edge leading to loop enter ; should be considered 'cold' as well. -define void @test13() { +define void @test13( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK: edge entry -> loop probability is 0x078780e3 / 0x80000000 = 5.88% ; CHECK: edge entry -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge] ; CHECK: edge loop -> loop probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge] @@ -531,12 +531,12 @@ ; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %loop, label %exit + br i1 %replaceUndef0, label %loop, label %exit loop: %i.0 = phi i32 [ 0, %entry ], [ %inc, %loop ] %inc = add nsw i32 %i.0, 1 - br i1 undef, label %loop, label %cold + br i1 %replaceUndef1, label %loop, label %cold cold: call void @cold() @@ -547,7 +547,7 @@ } ; This is the same case as test13 but with additional loop 'preheader' block. -define void @test14() { +define void @test14( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK: edge entry -> preheader probability is 0x078780e3 / 0x80000000 = 5.88% ; CHECK: edge entry -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge] ; CHECK: edge preheader -> loop probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] @@ -556,7 +556,7 @@ ; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %preheader, label %exit + br i1 %replaceUndef0, label %preheader, label %exit preheader: br label %loop @@ -564,7 +564,7 @@ loop: %i.0 = phi i32 [ 0, %preheader ], [ %inc, %loop ] %inc = add nsw i32 %i.0, 1 - br i1 undef, label %loop, label %cold + br i1 %replaceUndef1, label %loop, label %cold cold: call void @cold() @@ -576,7 +576,7 @@ ; If loop has multiple low probability exits then edge leading to loop enter ; should be considered low probable as well. -define void @test15() { +define void @test15( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK: edge entry -> loop probability is 0x078780e3 / 0x80000000 = 5.88% ; CHECK: edge entry -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge] ; CHECK: edge loop -> cont probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] @@ -586,15 +586,15 @@ ; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %loop, label %exit + br i1 %replaceUndef0, label %loop, label %exit loop: %i.0 = phi i32 [ 0, %entry ], [ %inc, %cont ] %inc = add nsw i32 %i.0, 1 - br i1 undef, label %cont, label %unreached + br i1 %replaceUndef1, label %cont, label %unreached cont: - br i1 undef, label %loop, label %cold + br i1 %replaceUndef2, label %loop, label %cold unreached: unreachable @@ -609,7 +609,7 @@ } ; This is the same case as test15 but with additional loop 'preheader' block. -define void @test16() { +define void @test16( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK: edge entry -> preheader probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] ; CHECK: edge preheader -> loop probability is 0x078780e3 / 0x80000000 = 5.88% ; CHECK: edge preheader -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge] @@ -623,15 +623,15 @@ br label %preheader preheader: - br i1 undef, label %loop, label %exit + br i1 %replaceUndef0, label %loop, label %exit loop: %i.0 = phi i32 [ 0, %preheader ], [ %inc, %cont ] %inc = add nsw i32 %i.0, 1 - br i1 undef, label %cont, label %unreached + br i1 %replaceUndef1, label %cont, label %unreached cont: - br i1 undef, label %loop, label %cold + br i1 %replaceUndef2, label %loop, label %cold unreached: unreachable @@ -649,7 +649,7 @@ ; Check that 'preheader' has 50/50 probability since there is one 'normal' exit. ; Check that exit to 'cold' and 'noreturn' has lower probability than 'normal' exit. -define void @test17() { +define void @test17( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) { ; CHECK: edge entry -> preheader probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] ; CHECK: edge preheader -> loop probability is 0x40000000 / 0x80000000 = 50.00% ; CHECK: edge preheader -> exit probability is 0x40000000 / 0x80000000 = 50.00% @@ -664,18 +664,18 @@ br label %preheader preheader: - br i1 undef, label %loop, label %exit + br i1 %replaceUndef0, label %loop, label %exit loop: %i.0 = phi i32 [ 0, %preheader ], [ %inc, %cont2 ] %inc = add nsw i32 %i.0, 1 - br i1 undef, label %cont, label %noreturn + br i1 %replaceUndef1, label %cont, label %noreturn cont: - br i1 undef, label %cont2, label %cold + br i1 %replaceUndef2, label %cont2, label %cold cont2: - br i1 undef, label %loop, label %exit + br i1 %replaceUndef3, label %loop, label %exit noreturn: call void @abort() @@ -692,7 +692,7 @@ ; This is case with two loops where one nested into another. Nested loop has ; low probable exit what encreases robability to take exit in the top level loop. -define void @test18() { +define void @test18( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK: edge entry -> top.loop probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] ; CHECK: edge top.loop -> loop probability is 0x546cd4b7 / 0x80000000 = 65.96% ; CHECK: edge top.loop -> exit probability is 0x2b932b49 / 0x80000000 = 34.04% @@ -705,12 +705,12 @@ top.loop: %j.0 = phi i32 [ 0, %entry ], [ %j.inc, %cold ] - br i1 undef, label %loop, label %exit + br i1 %replaceUndef0, label %loop, label %exit loop: %i.0 = phi i32 [ %j.0, %top.loop ], [ %inc, %loop ] %inc = add nsw i32 %i.0, 1 - br i1 undef, label %loop, label %cold + br i1 %replaceUndef1, label %loop, label %cold cold: call void @cold() diff --git a/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll b/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll --- a/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll +++ b/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll @@ -5,7 +5,7 @@ ; Both 'l1' and 'r1' has one edge leading to 'cold' and another one to ; 'unreachable' blocks. Check that 'cold' paths are preferred. Also ensure both ; paths from 'entry' block are equal. -define void @test1(i32 %0) { +define void @test1(i32 %0, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ;CHECK: edge entry -> l1 probability is 0x40000000 / 0x80000000 = 50.00% ;CHECK: edge entry -> r1 probability is 0x40000000 / 0x80000000 = 50.00% ;CHECK: edge l1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] @@ -14,13 +14,13 @@ ;CHECK: edge r1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %l1, label %r1 + br i1 %replaceUndef0, label %l1, label %r1 l1: - br i1 undef, label %cold, label %unreached + br i1 %replaceUndef1, label %cold, label %unreached r1: - br i1 undef, label %unreached, label %cold + br i1 %replaceUndef2, label %unreached, label %cold unreached: unreachable @@ -33,7 +33,7 @@ ; Both edges of 'l1' leads to 'cold' blocks while one edge of 'r1' leads to ; 'unreachable' block. Check that 'l1' has 50/50 while 'r1' has 0/100 ; distributuion. Also ensure both paths from 'entry' block are equal. -define void @test2(i32 %0) { +define void @test2(i32 %0, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ;CHECK: edge entry -> l1 probability is 0x40000000 / 0x80000000 = 50.00% ;CHECK: edge entry -> r1 probability is 0x40000000 / 0x80000000 = 50.00% ;CHECK: edge l1 -> cold probability is 0x40000000 / 0x80000000 = 50.00% @@ -42,13 +42,13 @@ ;CHECK: edge r1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %l1, label %r1 + br i1 %replaceUndef0, label %l1, label %r1 l1: - br i1 undef, label %cold, label %cold2 + br i1 %replaceUndef1, label %cold, label %cold2 r1: - br i1 undef, label %unreached, label %cold + br i1 %replaceUndef2, label %unreached, label %cold unreached: unreachable @@ -64,7 +64,7 @@ ; Both edges of 'r1' leads to 'unreachable' blocks while one edge of 'l1' leads to ; 'cold' block. Ensure that path leading to 'cold' block is preferred. -define void @test3(i32 %0) { +define void @test3(i32 %0, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ;CHECK: edge entry -> l1 probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] ;CHECK: edge entry -> r1 probability is 0x00000000 / 0x80000000 = 0.00% ;CHECK: edge l1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] @@ -73,13 +73,13 @@ ;CHECK: edge r1 -> unreached2 probability is 0x40000000 / 0x80000000 = 50.00% entry: - br i1 undef, label %l1, label %r1 + br i1 %replaceUndef0, label %l1, label %r1 l1: - br i1 undef, label %cold, label %unreached + br i1 %replaceUndef1, label %cold, label %unreached r1: - br i1 undef, label %unreached, label %unreached2 + br i1 %replaceUndef2, label %unreached, label %unreached2 unreached: unreachable @@ -95,7 +95,7 @@ ; Left edge of 'entry' leads to 'cold' block while right edge is 'normal' continuation. ; Check that we able to propagate 'cold' weight to 'entry' block. Also ensure ; both edges from 'l1' are equally likely. -define void @test4(i32 %0) { +define void @test4(i32 %0, i1 %replaceUndef0, i1 %replaceUndef1) { ;CHECK: edge entry -> l1 probability is 0x078780e3 / 0x80000000 = 5.88% ;CHECK: edge entry -> r1 probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge] ;CHECK: edge l1 -> l2 probability is 0x40000000 / 0x80000000 = 50.00% @@ -105,10 +105,10 @@ ;CHECK: edge to.cold -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] entry: - br i1 undef, label %l1, label %r1 + br i1 %replaceUndef0, label %l1, label %r1 l1: - br i1 undef, label %l2, label %r2 + br i1 %replaceUndef1, label %l2, label %r2 l2: br label %to.cold @@ -128,7 +128,7 @@ } ; Check that most likely path from 'entry' to 'l2' through 'r1' is preferred. -define void @test5(i32 %0) { +define void @test5(i32 %0, i1 %replaceUndef0, i1 %replaceUndef1) { ;CHECK: edge entry -> cold probability is 0x078780e3 / 0x80000000 = 5.88% ;CHECK: edge entry -> r1 probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge] ;CHECK: edge cold -> l2 probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] @@ -136,14 +136,14 @@ ;CHECK: edge r1 -> unreached probability is 0x00000000 / 0x80000000 = 0.00% entry: - br i1 undef, label %cold, label %r1 + br i1 %replaceUndef0, label %cold, label %r1 cold: call void @bar() br label %l2 r1: - br i1 undef, label %l2, label %unreached + br i1 %replaceUndef1, label %l2, label %unreached l2: ret void diff --git a/llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll b/llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll --- a/llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll +++ b/llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll @@ -3,21 +3,19 @@ ; RUN: opt -passes="print" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck --check-prefixes=ALL-SIZE %s ; END. -define amdgpu_kernel void @test_br_cost(ptr addrspace(1) %vaddr, i32 %b) #0 { +define amdgpu_kernel void @test_br_cost(ptr addrspace(1) %vaddr, i32 %b, i1 %replaceUndef0) #0 { ; ALL-LABEL: 'test_br_cost' -; ALL-NEXT: Cost Model: Found an estimated cost of 7 for instruction: br i1 undef, label %bb1, label %bb2 ; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: br label %bb2 ; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %phi = phi i32 [ %b, %bb0 ], [ undef, %bb1 ] ; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void ; ; ALL-SIZE-LABEL: 'test_br_cost' -; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: br i1 undef, label %bb1, label %bb2 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: br label %bb2 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %phi = phi i32 [ %b, %bb0 ], [ undef, %bb1 ] ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; bb0: - br i1 undef, label %bb1, label %bb2 + br i1 %replaceUndef0, label %bb1, label %bb2 bb1: br label %bb2 diff --git a/llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll b/llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll --- a/llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll +++ b/llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll @@ -31,7 +31,7 @@ entry: %NumOperands.i = getelementptr inbounds %"class.llvm::SDNode.310.1762.9990.10474.10958.11442.11926.12410.12894.13378.13862.15314.15798.16282.17734.19186.21122.25962.26930.29350.29834.30318.30802.31286.31770.32254.32738.33706.36610.38062.41642", ptr %N, i64 0, i32 8 %0 = load i16, ptr %NumOperands.i, align 8, !tbaa !1 - br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph + br i1 %replaceUndef0, label %for.cond.cleanup, label %for.body.lr.ph for.body.lr.ph: ; preds = %entry %wide.trip.count192 = zext i16 %0 to i64 diff --git a/llvm/test/Analysis/CycleInfo/basic.ll b/llvm/test/Analysis/CycleInfo/basic.ll --- a/llvm/test/Analysis/CycleInfo/basic.ll +++ b/llvm/test/Analysis/CycleInfo/basic.ll @@ -7,36 +7,36 @@ ret void } -define void @simple() { +define void @simple( i1 %replaceUndef0) { ; CHECK-LABEL: CycleInfo for function: simple ; CHECK: depth=1: entries(loop) entry: br label %loop loop: - br i1 undef, label %loop, label %exit + br i1 %replaceUndef0, label %loop, label %exit exit: ret void } -define void @two_latches() { +define void @two_latches( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK-LABEL: CycleInfo for function: two_latches ; CHECK: depth=1: entries(loop) loop_next entry: br label %loop loop: - br i1 undef, label %loop, label %loop_next + br i1 %replaceUndef0, label %loop, label %loop_next loop_next: - br i1 undef, label %exit, label %loop + br i1 %replaceUndef1, label %exit, label %loop exit: ret void } -define void @nested_simple() { +define void @nested_simple( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK-LABEL: CycleInfo for function: nested_simple ; CHECK: depth=1: entries(outer_header) outer_latch inner ; CHECK: depth=2: entries(inner) @@ -47,16 +47,16 @@ br label %inner inner: - br i1 undef, label %inner, label %outer_latch + br i1 %replaceUndef0, label %inner, label %outer_latch outer_latch: - br i1 undef, label %outer_header, label %exit + br i1 %replaceUndef1, label %outer_header, label %exit exit: ret void } -define void @nested_outer_latch_in_inner_loop() { +define void @nested_outer_latch_in_inner_loop( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK-LABEL: CycleInfo for function: nested_outer_latch_in_inner_loop ; CHECK: depth=1: entries(outer_header) inner_header inner_latch ; CHECK: depth=2: entries(inner_header) inner_latch @@ -67,33 +67,33 @@ br label %inner_header inner_header: - br i1 undef, label %inner_latch, label %outer_header + br i1 %replaceUndef0, label %inner_latch, label %outer_header inner_latch: - br i1 undef, label %exit, label %inner_header + br i1 %replaceUndef1, label %exit, label %inner_header exit: ret void } -define void @sibling_loops() { +define void @sibling_loops( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: CycleInfo for function: sibling_loops ; CHECK-DAG: depth=1: entries(left) ; CHECK-DAG: depth=1: entries(right) entry: - br i1 undef, label %left, label %right + br i1 %replaceUndef0, label %left, label %right left: - br i1 undef, label %left, label %exit + br i1 %replaceUndef1, label %left, label %exit right: - br i1 undef, label %right, label %exit + br i1 %replaceUndef2, label %right, label %exit exit: ret void } -define void @serial_loops() { +define void @serial_loops( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK-LABEL: CycleInfo for function: serial_loops ; CHECK-DAG: depth=1: entries(second) ; CHECK-DAG: depth=1: entries(first) @@ -101,16 +101,16 @@ br label %first first: - br i1 undef, label %first, label %second + br i1 %replaceUndef0, label %first, label %second second: - br i1 undef, label %second, label %exit + br i1 %replaceUndef1, label %second, label %exit exit: ret void } -define void @nested_sibling_loops() { +define void @nested_sibling_loops( i1 %replaceUndef0) { ; CHECK-LABEL: CycleInfo for function: nested_sibling_loops ; CHECK: depth=1: entries(outer_header) left right ; CHECK-DAG: depth=2: entries(right) @@ -119,7 +119,7 @@ br label %outer_header outer_header: - br i1 undef, label %left, label %right + br i1 %replaceUndef0, label %left, label %right left: switch i32 undef, label %exit [ i32 0, label %left @@ -133,7 +133,7 @@ ret void } -define void @deeper_nest() { +define void @deeper_nest( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: CycleInfo for function: deeper_nest ; CHECK: depth=1: entries(outer_header) outer_latch middle_header inner_header inner_latch ; CHECK: depth=2: entries(middle_header) inner_header inner_latch @@ -148,47 +148,47 @@ br label %inner_header inner_header: - br i1 undef, label %middle_header, label %inner_latch + br i1 %replaceUndef0, label %middle_header, label %inner_latch inner_latch: - br i1 undef, label %inner_header, label %outer_latch + br i1 %replaceUndef1, label %inner_header, label %outer_latch outer_latch: - br i1 undef, label %outer_header, label %exit + br i1 %replaceUndef2, label %outer_header, label %exit exit: ret void } -define void @irreducible_basic() { +define void @irreducible_basic( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: CycleInfo for function: irreducible_basic ; CHECK: depth=1: entries(right left) entry: - br i1 undef, label %left, label %right + br i1 %replaceUndef0, label %left, label %right left: - br i1 undef, label %right, label %exit + br i1 %replaceUndef1, label %right, label %exit right: - br i1 undef, label %left, label %exit + br i1 %replaceUndef2, label %left, label %exit exit: ret void } -define void @irreducible_mess() { +define void @irreducible_mess( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: CycleInfo for function: irreducible_mess ; CHECK: depth=1: entries(B A) D C ; CHECK: depth=2: entries(D C A) ; CHECK: depth=3: entries(C A) entry: - br i1 undef, label %A, label %B + br i1 %replaceUndef0, label %A, label %B A: - br i1 undef, label %C, label %D + br i1 %replaceUndef1, label %C, label %D B: - br i1 undef, label %C, label %D + br i1 %replaceUndef2, label %C, label %D C: switch i32 undef, label %A [ i32 0, label %D @@ -202,7 +202,7 @@ ret void } -define void @irreducible_into_simple_cycle() { +define void @irreducible_into_simple_cycle( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK-LABEL: CycleInfo for function: irreducible_into_simple_cycle ; CHECK: depth=1: entries(F C A) E D B entry: @@ -219,28 +219,28 @@ br label %D D: - br i1 undef, label %E, label %exit + br i1 %replaceUndef0, label %E, label %exit E: br label %F F: - br i1 undef, label %A, label %exit + br i1 %replaceUndef1, label %A, label %exit exit: ret void } -define void @irreducible_mountain_bug() { +define void @irreducible_mountain_bug( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13) { ; CHECK-LABEL: CycleInfo for function: irreducible_mountain_bug ; CHECK: depth=1: entries(while.cond) ; CHECK: depth=2: entries(cond.end61 cond.true49) while.body63 while.cond47 ; CHECK: depth=3: entries(while.body63 cond.true49) while.cond47 entry: - br i1 undef, label %if.end, label %if.then + br i1 %replaceUndef0, label %if.end, label %if.then if.end: - br i1 undef, label %if.then7, label %if.else + br i1 %replaceUndef1, label %if.then7, label %if.else if.then7: br label %if.end16 @@ -249,49 +249,49 @@ br label %if.end16 if.end16: - br i1 undef, label %while.cond.preheader, label %if.then39 + br i1 %replaceUndef2, label %while.cond.preheader, label %if.then39 while.cond.preheader: br label %while.cond while.cond: - br i1 undef, label %cond.true49, label %lor.rhs + br i1 %replaceUndef3, label %cond.true49, label %lor.rhs cond.true49: - br i1 undef, label %if.then69, label %while.body63 + br i1 %replaceUndef4, label %if.then69, label %while.body63 while.body63: - br i1 undef, label %exit, label %while.cond47 + br i1 %replaceUndef5, label %exit, label %while.cond47 while.cond47: - br i1 undef, label %cond.true49, label %cond.end61 + br i1 %replaceUndef6, label %cond.true49, label %cond.end61 cond.end61: - br i1 undef, label %while.body63, label %while.cond + br i1 %replaceUndef7, label %while.body63, label %while.cond if.then69: - br i1 undef, label %exit, label %while.cond + br i1 %replaceUndef8, label %exit, label %while.cond lor.rhs: - br i1 undef, label %cond.end61, label %while.end76 + br i1 %replaceUndef9, label %cond.end61, label %while.end76 while.end76: br label %exit if.then39: - br i1 undef, label %exit, label %if.end.i145 + br i1 %replaceUndef10, label %exit, label %if.end.i145 if.end.i145: - br i1 undef, label %exit, label %if.end8.i149 + br i1 %replaceUndef11, label %exit, label %if.end8.i149 if.end8.i149: br label %exit if.then: - br i1 undef, label %exit, label %if.end.i + br i1 %replaceUndef12, label %exit, label %if.end.i if.end.i: - br i1 undef, label %exit, label %if.end8.i + br i1 %replaceUndef13, label %exit, label %if.end8.i if.end8.i: br label %exit diff --git a/llvm/test/Analysis/Delinearization/type_mismatch.ll b/llvm/test/Analysis/Delinearization/type_mismatch.ll --- a/llvm/test/Analysis/Delinearization/type_mismatch.ll +++ b/llvm/test/Analysis/Delinearization/type_mismatch.ll @@ -8,7 +8,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32" -define fastcc void @test() { +define fastcc void @test( i1 %replaceUndef0) { entry: %0 = load i16, ptr undef, align 2 %conv21 = zext i16 %0 to i32 @@ -21,7 +21,7 @@ for.body11: %arrayidx.phi = phi ptr [ %p1.022, %for.cond7.preheader ], [ undef, %for.body11 ] store i8 undef, ptr %arrayidx.phi, align 1 - br i1 undef, label %for.body11, label %for.end + br i1 %replaceUndef0, label %for.body11, label %for.end for.end: %add.ptr = getelementptr inbounds i8, ptr %p1.022, i32 %conv21 diff --git a/llvm/test/Analysis/Delinearization/undef.ll b/llvm/test/Analysis/Delinearization/undef.ll --- a/llvm/test/Analysis/Delinearization/undef.ll +++ b/llvm/test/Analysis/Delinearization/undef.ll @@ -2,17 +2,17 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @foo(ptr %Ey) { +define void @foo(ptr %Ey, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4) { entry: - br i1 undef, label %for.cond55.preheader, label %for.end324 + br i1 %replaceUndef0, label %for.cond55.preheader, label %for.end324 for.cond55.preheader: %iz.069 = phi i64 [ %inc323, %for.inc322 ], [ 0, %entry ] - br i1 undef, label %for.cond58.preheader, label %for.inc322 + br i1 %replaceUndef1, label %for.cond58.preheader, label %for.inc322 for.cond58.preheader: %iy.067 = phi i64 [ %inc320, %for.end ], [ 0, %for.cond55.preheader ] - br i1 undef, label %for.body60, label %for.end + br i1 %replaceUndef2, label %for.body60, label %for.end for.body60: %ix.062 = phi i64 [ %inc, %for.body60 ], [ 0, %for.cond58.preheader ] @@ -27,11 +27,11 @@ for.end: %inc320 = add nsw i64 %iy.067, 1 - br i1 undef, label %for.cond58.preheader, label %for.inc322 + br i1 %replaceUndef3, label %for.cond58.preheader, label %for.inc322 for.inc322: %inc323 = add nsw i64 %iz.069, 1 - br i1 undef, label %for.cond55.preheader, label %for.end324 + br i1 %replaceUndef4, label %for.cond55.preheader, label %for.end324 for.end324: ret void diff --git a/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll b/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll --- a/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll +++ b/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll @@ -29,21 +29,21 @@ %20 = type { [768 x i32] } %21 = type { [416 x i32] } -define void @test(ptr %A) #0 align 2 { +define void @test(ptr %A, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) #0 align 2 { entry: %v1 = load i32, ptr undef, align 4 br label %bb13 bb13: %v2 = phi i32 [ undef, %entry ], [ %v39, %bb38 ] - br i1 undef, label %bb15, label %bb38 + br i1 %replaceUndef0, label %bb15, label %bb38 bb15: %v3 = mul nsw i32 %v2, undef br label %bb17 bb17: - br i1 undef, label %bb21, label %bb37 + br i1 %replaceUndef1, label %bb21, label %bb37 bb21: %v22 = add nsw i32 undef, 1 @@ -55,10 +55,10 @@ %v29 = mul nsw i32 %v28, 32 %v30 = getelementptr inbounds %1, ptr %A, i32 0, i32 7, i32 14, i32 %v29 %v32 = load <32 x i32>, ptr %v30, align 128 - br i1 undef, label %bb21, label %bb37 + br i1 %replaceUndef2, label %bb21, label %bb37 bb37: - br i1 undef, label %bb17, label %bb38 + br i1 %replaceUndef3, label %bb17, label %bb38 bb38: %v39 = add nsw i32 %v2, 1 diff --git a/llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll b/llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll --- a/llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll +++ b/llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll @@ -7,7 +7,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64" target triple = "thumbv7--linux-gnueabi" -define void @f(ptr %a, i32 %n) align 2 { +define void @f(ptr %a, i32 %n, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) align 2 { for.preheader: %t.0 = ashr exact i32 %n, 3 br label %for.body.1 @@ -15,7 +15,7 @@ for.body.1: %i.1 = phi i32 [ %t.5, %for.inc ], [ 0, %for.preheader ] %i.2 = phi i32 [ %i.5, %for.inc ], [ %t.0, %for.preheader ] - br i1 undef, label %for.inc, label %for.body.2 + br i1 %replaceUndef0, label %for.inc, label %for.body.2 for.body.2: %i.3 = phi i32 [ %t.1, %for.body.2 ], [ %i.1, %for.body.1 ] @@ -23,13 +23,13 @@ %t.2 = load ptr, ptr %a, align 4 %t.3 = getelementptr inbounds i32, ptr %t.2, i32 %i.3 %t.4 = load i32, ptr %t.3, align 4 - br i1 undef, label %for.inc, label %for.body.2 + br i1 %replaceUndef1, label %for.inc, label %for.body.2 for.inc: %i.4 = phi i32 [ %i.2, %for.body.1 ], [ %i.2, %for.body.2 ] %t.5 = add i32 %i.1, %i.4 %i.5 = add i32 %i.2, -1 - br i1 undef, label %for.exit, label %for.body.1 + br i1 %replaceUndef2, label %for.exit, label %for.body.1 for.exit: ret void diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/join-at-loop-heart.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/join-at-loop-heart.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/join-at-loop-heart.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/join-at-loop-heart.ll @@ -7,7 +7,7 @@ ; CHECK: DIVERGENT: %inc = add i32 %phi.h, 1 ; CHECK: DIVERGENT: br i1 %div.cond, label %C, label %D -define void @nested_loop_extension() { +define void @nested_loop_extension( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { entry: %anchor = call token @llvm.experimental.convergence.anchor() br label %A @@ -23,14 +23,14 @@ br i1 %div.cond, label %C, label %D C: - br i1 undef, label %A, label %E + br i1 %replaceUndef0, label %A, label %E D: - br i1 undef, label %A, label %E + br i1 %replaceUndef1, label %A, label %E E: %b = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %anchor) ] - br i1 undef, label %A, label %F + br i1 %replaceUndef2, label %A, label %F F: ret void diff --git a/llvm/test/Analysis/Dominators/basic.ll b/llvm/test/Analysis/Dominators/basic.ll --- a/llvm/test/Analysis/Dominators/basic.ll +++ b/llvm/test/Analysis/Dominators/basic.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -disable-output -passes='print' 2>&1 | FileCheck %s -define void @test1() { +define void @test1( i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK-LABEL: DominatorTree for function: test1 ; CHECK: [1] %entry ; CHECK-NEXT: [2] %a @@ -10,7 +10,7 @@ ; CHECK-NEXT: [2] %b entry: - br i1 undef, label %a, label %b + br i1 %replaceUndef0, label %a, label %b a: br label %c @@ -19,7 +19,7 @@ br label %c c: - br i1 undef, label %d, label %e + br i1 %replaceUndef1, label %d, label %e d: ret void @@ -28,7 +28,7 @@ ret void } -define void @test2() { +define void @test2( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: DominatorTree for function: test2 ; CHECK: [1] %entry ; CHECK-NEXT: [2] %a @@ -44,13 +44,13 @@ br label %b b: - br i1 undef, label %a, label %c + br i1 %replaceUndef0, label %a, label %c c: - br i1 undef, label %d, label %ret + br i1 %replaceUndef1, label %d, label %ret d: - br i1 undef, label %a, label %ret + br i1 %replaceUndef2, label %a, label %ret ret: ret void diff --git a/llvm/test/Analysis/Dominators/print-dot-dom.ll b/llvm/test/Analysis/Dominators/print-dot-dom.ll --- a/llvm/test/Analysis/Dominators/print-dot-dom.ll +++ b/llvm/test/Analysis/Dominators/print-dot-dom.ll @@ -2,7 +2,7 @@ ; RUN: FileCheck %s -input-file=dom.test1.dot -check-prefix=TEST1 ; RUN: FileCheck %s -input-file=dom.test2.dot -check-prefix=TEST2 -define void @test1() { +define void @test1( i1 %replaceUndef0, i1 %replaceUndef1) { ; TEST1: digraph "Dominator tree for 'test1' function" ; TEST1-NEXT: label="Dominator tree for 'test1' function" ; TEST1: Node0x[[EntryID:.*]] [shape=record,label="{entry: @@ -18,7 +18,7 @@ ; TEST1-NEXT: Node0x[[B_ID]] [shape=record,label="{b: entry: - br i1 undef, label %a, label %b + br i1 %replaceUndef0, label %a, label %b a: br label %c @@ -27,7 +27,7 @@ br label %c c: - br i1 undef, label %d, label %e + br i1 %replaceUndef1, label %d, label %e d: ret void @@ -36,7 +36,7 @@ ret void } -define void @test2() { +define void @test2( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; TEST2: digraph "Dominator tree for 'test2' function" ; TEST2-NEXT: label="Dominator tree for 'test2' function" ; TEST2: Node0x[[EntryID:.*]] [shape=record,label="{entry: @@ -58,13 +58,13 @@ br label %b b: - br i1 undef, label %a, label %c + br i1 %replaceUndef0, label %a, label %c c: - br i1 undef, label %d, label %e + br i1 %replaceUndef1, label %d, label %e d: - br i1 undef, label %a, label %e + br i1 %replaceUndef2, label %a, label %e e: ret void diff --git a/llvm/test/Analysis/MemorySSA/cyclicphi.ll b/llvm/test/Analysis/MemorySSA/cyclicphi.ll --- a/llvm/test/Analysis/MemorySSA/cyclicphi.ll +++ b/llvm/test/Analysis/MemorySSA/cyclicphi.ll @@ -3,15 +3,14 @@ %struct.hoge = type { i32, %struct.widget } %struct.widget = type { i64 } -define hidden void @quux(ptr %f) align 2 { +define hidden void @quux(ptr %f, i1 %replaceUndef0) align 2 { %tmp = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1, i32 0 %tmp24 = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1 br label %bb26 bb26: ; preds = %bb77, %0 ; CHECK: 3 = MemoryPhi({%0,liveOnEntry},{bb77,2}) -; CHECK-NEXT: br i1 undef, label %bb68, label %bb77 - br i1 undef, label %bb68, label %bb77 + br i1 %replaceUndef0, label %bb68, label %bb77 bb68: ; preds = %bb26 ; CHECK: MemoryUse(liveOnEntry) @@ -31,7 +30,7 @@ br label %bb26 } -define hidden void @quux_no_null_opt(ptr %f) align 2 #0 { +define hidden void @quux_no_null_opt(ptr %f, i1 %replaceUndef0) align 2 #0 { ; CHECK-LABEL: quux_no_null_opt( %tmp = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1, i32 0 %tmp24 = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1 @@ -39,8 +38,7 @@ bb26: ; preds = %bb77, %0 ; CHECK: 3 = MemoryPhi({%0,liveOnEntry},{bb77,2}) -; CHECK-NEXT: br i1 undef, label %bb68, label %bb77 - br i1 undef, label %bb68, label %bb77 + br i1 %replaceUndef0, label %bb68, label %bb77 bb68: ; preds = %bb26 ; CHECK: MemoryUse(3) @@ -61,15 +59,14 @@ } ; CHECK-LABEL: define void @quux_skip -define void @quux_skip(ptr noalias %f, ptr noalias %g) align 2 { +define void @quux_skip(ptr noalias %f, ptr noalias %g, i1 %replaceUndef0) align 2 { %tmp = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1, i32 0 %tmp24 = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1 br label %bb26 bb26: ; preds = %bb77, %0 ; CHECK: 3 = MemoryPhi({%0,liveOnEntry},{bb77,2}) -; CHECK-NEXT: br i1 undef, label %bb68, label %bb77 - br i1 undef, label %bb68, label %bb77 + br i1 %replaceUndef0, label %bb68, label %bb77 bb68: ; preds = %bb26 ; CHECK: MemoryUse(3) @@ -89,7 +86,7 @@ } ; CHECK-LABEL: define void @quux_dominated -define void @quux_dominated(ptr noalias %f, ptr noalias %g) align 2 { +define void @quux_dominated(ptr noalias %f, ptr noalias %g, i1 %replaceUndef0) align 2 { %tmp = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1, i32 0 %tmp24 = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1 br label %bb26 @@ -99,7 +96,7 @@ ; CHECK: MemoryUse(3) ; CHECK-NEXT: load ptr, ptr %tmp24, align 8 load ptr, ptr %tmp24, align 8 - br i1 undef, label %bb68, label %bb77 + br i1 %replaceUndef0, label %bb68, label %bb77 bb68: ; preds = %bb26 ; CHECK: MemoryUse(3) @@ -119,7 +116,7 @@ } ; CHECK-LABEL: define void @quux_nodominate -define void @quux_nodominate(ptr noalias %f, ptr noalias %g) align 2 { +define void @quux_nodominate(ptr noalias %f, ptr noalias %g, i1 %replaceUndef0) align 2 { %tmp = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1, i32 0 %tmp24 = getelementptr inbounds %struct.hoge, ptr %f, i64 0, i32 1 br label %bb26 @@ -129,7 +126,7 @@ ; CHECK: MemoryUse(liveOnEntry) ; CHECK-NEXT: load ptr, ptr %tmp24, align 8 load ptr, ptr %tmp24, align 8 - br i1 undef, label %bb68, label %bb77 + br i1 %replaceUndef0, label %bb68, label %bb77 bb68: ; preds = %bb26 ; CHECK: MemoryUse(3) diff --git a/llvm/test/Analysis/MemorySSA/debugvalue.ll b/llvm/test/Analysis/MemorySSA/debugvalue.ll --- a/llvm/test/Analysis/MemorySSA/debugvalue.ll +++ b/llvm/test/Analysis/MemorySSA/debugvalue.ll @@ -2,14 +2,14 @@ ; REQUIRES: asserts ; CHECK-LABEL: @f_w4_i2 -define void @f_w4_i2() { +define void @f_w4_i2( i1 %replaceUndef0) { entry: br label %for.cond for.cond: ; preds = %for.body, %entry %i.0 = phi i16 [ 0, %entry ], [ %inc, %for.body ] call void @llvm.dbg.value(metadata i16 %i.0, metadata !32, metadata !DIExpression()), !dbg !31 - br i1 undef, label %for.body, label %for.cond.cleanup + br i1 %replaceUndef0, label %for.body, label %for.cond.cleanup for.cond.cleanup: ; preds = %for.cond ret void diff --git a/llvm/test/Analysis/MemorySSA/debugvalue2.ll b/llvm/test/Analysis/MemorySSA/debugvalue2.ll --- a/llvm/test/Analysis/MemorySSA/debugvalue2.ll +++ b/llvm/test/Analysis/MemorySSA/debugvalue2.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: @overflow_iter_var ; CHECK-NOT: MemoryDef -define void @overflow_iter_var() !dbg !11 { +define void @overflow_iter_var( i1 %replaceUndef0) !dbg !11 { entry: call void @llvm.dbg.value(metadata i16 0, metadata !16, metadata !DIExpression()), !dbg !18 br label %for.cond @@ -16,7 +16,7 @@ for.cond: ; preds = %for.body, %entry call void @llvm.dbg.value(metadata i16 0, metadata !16, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata i16 undef, metadata !20, metadata !DIExpression()), !dbg !21 - br i1 undef, label %for.end, label %for.body + br i1 %replaceUndef0, label %for.end, label %for.body for.body: ; preds = %for.cond %0 = load i16, ptr undef, align 1 diff --git a/llvm/test/Analysis/MemorySSA/forward-unreachable.ll b/llvm/test/Analysis/MemorySSA/forward-unreachable.ll --- a/llvm/test/Analysis/MemorySSA/forward-unreachable.ll +++ b/llvm/test/Analysis/MemorySSA/forward-unreachable.ll @@ -1,9 +1,9 @@ ; RUN: opt -aa-pipeline=basic-aa -passes='print,verify' -disable-output < %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" -define void @test() { +define void @test( i1 %replaceUndef0) { entry: - br i1 undef, label %split1, label %split2 + br i1 %replaceUndef0, label %split1, label %split2 split1: store i16 undef, ptr undef, align 2 diff --git a/llvm/test/Analysis/MemorySSA/function-clobber.ll b/llvm/test/Analysis/MemorySSA/function-clobber.ll --- a/llvm/test/Analysis/MemorySSA/function-clobber.ll +++ b/llvm/test/Analysis/MemorySSA/function-clobber.ll @@ -29,11 +29,11 @@ declare void @clobberEverything() ; CHECK-LABEL: define void @bar -define void @bar() { +define void @bar( i1 %replaceUndef0) { ; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK-NEXT: call void @clobberEverything() call void @clobberEverything() - br i1 undef, label %if.end, label %if.then + br i1 %replaceUndef0, label %if.end, label %if.then if.then: ; CHECK: MemoryUse(1) diff --git a/llvm/test/Analysis/MemorySSA/invariant-groups.ll b/llvm/test/Analysis/MemorySSA/invariant-groups.ll --- a/llvm/test/Analysis/MemorySSA/invariant-groups.ll +++ b/llvm/test/Analysis/MemorySSA/invariant-groups.ll @@ -195,7 +195,7 @@ } ; CHECK-LABEL: define {{.*}} @loop2( -define i8 @loop2(ptr %p) { +define i8 @loop2(ptr %p, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { entry: ; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK-NEXT: store i8 @@ -207,7 +207,7 @@ ; CHECK: 3 = MemoryDef(2) ; CHECK-NEXT: %after = call ptr @llvm.launder.invariant.group.p0(ptr %p) %after = call ptr @llvm.launder.invariant.group.p0(ptr %p) - br i1 undef, label %Loop.Body, label %Loop.End + br i1 %replaceUndef0, label %Loop.Body, label %Loop.End Loop.Body: ; CHECK: MemoryUse(6) @@ -221,7 +221,7 @@ ; CHECK: 4 = MemoryDef(6) store i8 4, ptr %after, !invariant.group !0 - br i1 undef, label %Loop.End, label %Loop.Body + br i1 %replaceUndef1, label %Loop.End, label %Loop.Body Loop.End: ; CHECK: MemoryUse(5) @@ -231,7 +231,7 @@ ; CHECK: MemoryUse(5) {{.*}} clobbered by 1 ; CHECK-NEXT: %3 = load %3 = load i8, ptr %p, align 4, !invariant.group !0 - br i1 undef, label %Ret, label %Loop.Body + br i1 %replaceUndef2, label %Ret, label %Loop.Body Ret: ret i8 %3 @@ -239,7 +239,7 @@ ; CHECK-LABEL: define {{.*}} @loop3( -define i8 @loop3(ptr %p) { +define i8 @loop3(ptr %p, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) { entry: ; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK-NEXT: store i8 @@ -251,7 +251,7 @@ ; CHECK: 3 = MemoryDef(2) ; CHECK-NEXT: %after = call ptr @llvm.launder.invariant.group.p0(ptr %p) %after = call ptr @llvm.launder.invariant.group.p0(ptr %p) - br i1 undef, label %Loop.Body, label %Loop.End + br i1 %replaceUndef0, label %Loop.Body, label %Loop.End Loop.Body: ; CHECK: MemoryUse(8) @@ -266,7 +266,7 @@ ; CHECK-NEXT: %1 = load i8 %1 = load i8, ptr %after, !invariant.group !0 - br i1 undef, label %Loop.next, label %Loop.Body + br i1 %replaceUndef1, label %Loop.next, label %Loop.Body Loop.next: ; CHECK: 5 = MemoryDef(4) ; CHECK-NEXT: call void @clobber8 @@ -276,7 +276,7 @@ ; CHECK-NEXT: %2 = load i8 %2 = load i8, ptr %after, !invariant.group !0 - br i1 undef, label %Loop.End, label %Loop.Body + br i1 %replaceUndef2, label %Loop.End, label %Loop.Body Loop.End: ; CHECK: MemoryUse(7) @@ -290,14 +290,14 @@ ; CHECK: MemoryUse(6) {{.*}} clobbered by 7 ; CHECK-NEXT: %4 = load %4 = load i8, ptr %after, align 4, !invariant.group !0 - br i1 undef, label %Ret, label %Loop.Body + br i1 %replaceUndef3, label %Ret, label %Loop.Body Ret: ret i8 %3 } ; CHECK-LABEL: define {{.*}} @loop4( -define i8 @loop4(ptr %p) { +define i8 @loop4(ptr %p, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { entry: ; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK-NEXT: store i8 @@ -308,7 +308,7 @@ ; CHECK: 3 = MemoryDef(2) ; CHECK-NEXT: %after = call ptr @llvm.launder.invariant.group.p0(ptr %p) %after = call ptr @llvm.launder.invariant.group.p0(ptr %p) - br i1 undef, label %Loop.Pre, label %Loop.End + br i1 %replaceUndef0, label %Loop.Pre, label %Loop.End Loop.Pre: ; CHECK: MemoryUse(2) @@ -326,7 +326,7 @@ ; CHECK: 4 = MemoryDef(6) store i8 4, ptr %after, !invariant.group !0 - br i1 undef, label %Loop.End, label %Loop.Body + br i1 %replaceUndef1, label %Loop.End, label %Loop.Body Loop.End: ; CHECK: MemoryUse(5) @@ -336,7 +336,7 @@ ; CHECK: MemoryUse(5) {{.*}} clobbered by 1 ; CHECK-NEXT: %4 = load %4 = load i8, ptr %p, align 4, !invariant.group !0 - br i1 undef, label %Ret, label %Loop.Body + br i1 %replaceUndef2, label %Ret, label %Loop.Body Ret: ret i8 %3 diff --git a/llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll b/llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll --- a/llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll +++ b/llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll @@ -5,13 +5,13 @@ ; CHECK-LABEL: @main ; CHECK-NOT: MemoryDef -define void @main() { +define void @main( i1 %replaceUndef0) { entry: br label %for.cond120 for.cond120: ; preds = %for.body127, %entry call void @foo() - br i1 undef, label %for.body127, label %for.cond.cleanup126 + br i1 %replaceUndef0, label %for.body127, label %for.cond.cleanup126 for.cond.cleanup126: ; preds = %for.cond120 unreachable diff --git a/llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll b/llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll --- a/llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll +++ b/llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll @@ -5,7 +5,7 @@ ; otherwise, MemorySSA will assert. ; CHECK-LABEL: @f -define void @f() { +define void @f( i1 %replaceUndef0) { entry: br label %for.body16 @@ -15,7 +15,7 @@ for.body16: ; preds = %for.body16.for.body16_crit_edge, %entry %call.i = tail call float @expf(float 0.000000e+00) #1 %0 = load ptr, ptr undef, align 8 - br i1 undef, label %for.cond.cleanup15, label %for.body16.for.body16_crit_edge + br i1 %replaceUndef0, label %for.cond.cleanup15, label %for.body16.for.body16_crit_edge for.body16.for.body16_crit_edge: ; preds = %for.body16 %.pre = load float, ptr undef, align 8 diff --git a/llvm/test/Analysis/MemorySSA/phi-translation.ll b/llvm/test/Analysis/MemorySSA/phi-translation.ll --- a/llvm/test/Analysis/MemorySSA/phi-translation.ll +++ b/llvm/test/Analysis/MemorySSA/phi-translation.ll @@ -73,7 +73,7 @@ } ; CHECK-LABEL: define void @cross_phi -define void @cross_phi(ptr noalias %p1, ptr noalias %p2) { +define void @cross_phi(ptr noalias %p1, ptr noalias %p2, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK-NEXT: store i8 0, ptr %p1 store i8 0, ptr %p1 @@ -82,19 +82,19 @@ ; LIMIT: MemoryUse(1) ; LIMIT-NEXT: load i8, ptr %p1 load i8, ptr %p1 - br i1 undef, label %a, label %b + br i1 %replaceUndef0, label %a, label %b a: ; CHECK: 2 = MemoryDef(1) ; CHECK-NEXT: store i8 0, ptr %p2 store i8 0, ptr %p2 - br i1 undef, label %c, label %d + br i1 %replaceUndef1, label %c, label %d b: ; CHECK: 3 = MemoryDef(1) ; CHECK-NEXT: store i8 1, ptr %p2 store i8 1, ptr %p2 - br i1 undef, label %c, label %d + br i1 %replaceUndef2, label %c, label %d c: ; CHECK: 6 = MemoryPhi({a,2},{b,3}) @@ -121,7 +121,7 @@ } ; CHECK-LABEL: define void @looped -define void @looped(ptr noalias %p1, ptr noalias %p2) { +define void @looped(ptr noalias %p1, ptr noalias %p2, i1 %replaceUndef0, i1 %replaceUndef1) { ; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK-NEXT: store i8 0, ptr %p1 store i8 0, ptr %p1 @@ -132,7 +132,7 @@ ; CHECK: 2 = MemoryDef(6) ; CHECK-NEXT: store i8 0, ptr %p2 store i8 0, ptr %p2 - br i1 undef, label %loop.2, label %loop.3 + br i1 %replaceUndef0, label %loop.2, label %loop.3 loop.2: ; CHECK: 5 = MemoryPhi({loop.1,2},{loop.3,4}) @@ -151,23 +151,22 @@ ; LIMIT: MemoryUse(4) ; LIMIT-NEXT: load i8, ptr %p1 load i8, ptr %p1 - br i1 undef, label %loop.2, label %loop.1 + br i1 %replaceUndef1, label %loop.2, label %loop.1 } ; CHECK-LABEL: define void @looped_visitedonlyonce -define void @looped_visitedonlyonce(ptr noalias %p1, ptr noalias %p2) { +define void @looped_visitedonlyonce(ptr noalias %p1, ptr noalias %p2, i1 %replaceUndef0, i1 %replaceUndef1) { br label %while.cond while.cond: ; CHECK: 5 = MemoryPhi({%0,liveOnEntry},{if.end,3}) -; CHECK-NEXT: br i1 undef, label %if.then, label %if.end - br i1 undef, label %if.then, label %if.end + br i1 %replaceUndef0, label %if.then, label %if.end if.then: ; CHECK: 1 = MemoryDef(5) ; CHECK-NEXT: store i8 0, ptr %p1 store i8 0, ptr %p1 - br i1 undef, label %if.end, label %if.then2 + br i1 %replaceUndef1, label %if.end, label %if.then2 if.then2: ; CHECK: 2 = MemoryDef(1) diff --git a/llvm/test/Analysis/MemorySSA/pr28880.ll b/llvm/test/Analysis/MemorySSA/pr28880.ll --- a/llvm/test/Analysis/MemorySSA/pr28880.ll +++ b/llvm/test/Analysis/MemorySSA/pr28880.ll @@ -8,9 +8,9 @@ @global.1 = external hidden unnamed_addr global double, align 8 ; Function Attrs: nounwind ssp uwtable -define hidden fastcc void @hoge() unnamed_addr #0 { +define hidden fastcc void @hoge( i1 %replaceUndef0, i1 %replaceUndef1) unnamed_addr #0 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %replaceUndef0, label %bb1, label %bb2 bb1: ; preds = %bb ; These accesses should not conflict. @@ -28,7 +28,7 @@ br label %bb3 bb3: ; preds = %bb2 - br i1 undef, label %bb4, label %bb6 + br i1 %replaceUndef1, label %bb4, label %bb6 bb4: ; preds = %bb3 ; These accesses should conflict. diff --git a/llvm/test/Analysis/MemorySSA/pr40749_2.ll b/llvm/test/Analysis/MemorySSA/pr40749_2.ll --- a/llvm/test/Analysis/MemorySSA/pr40749_2.ll +++ b/llvm/test/Analysis/MemorySSA/pr40749_2.ll @@ -7,7 +7,7 @@ @g_993 = external dso_local local_unnamed_addr global i32, align 4 ; CHECK-LABEL: @ff6 -define dso_local fastcc void @ff6(i16 %arg1) unnamed_addr #0 { +define dso_local fastcc void @ff6(i16 %arg1, i1 %replaceUndef0) unnamed_addr #0 { bb: %tmp6.i = icmp sgt i16 %arg1, 0 br label %bb10 @@ -50,7 +50,7 @@ br label %bb75 bb75: ; preds = %bb67, %bb67.us.loopexit - br i1 undef, label %bb24.preheader, label %bb84.loopexit + br i1 %replaceUndef0, label %bb24.preheader, label %bb84.loopexit bb81.loopexit: ; preds = %bb61.us br label %bb10 diff --git a/llvm/test/Analysis/MemorySSA/pr43641.ll b/llvm/test/Analysis/MemorySSA/pr43641.ll --- a/llvm/test/Analysis/MemorySSA/pr43641.ll +++ b/llvm/test/Analysis/MemorySSA/pr43641.ll @@ -2,9 +2,9 @@ ; REQUIRES: asserts ; CHECK-LABEL: @c -define dso_local void @c(i32 signext %d) local_unnamed_addr { +define dso_local void @c(i32 signext %d, i1 %replaceUndef0) local_unnamed_addr { entry: - br i1 undef, label %while.end, label %while.body.lr.ph + br i1 %replaceUndef0, label %while.end, label %while.body.lr.ph while.body.lr.ph: ; preds = %entry %tobool1 = icmp ne i32 %d, 0 diff --git a/llvm/test/Analysis/MemorySSA/renamephis.ll b/llvm/test/Analysis/MemorySSA/renamephis.ll --- a/llvm/test/Analysis/MemorySSA/renamephis.ll +++ b/llvm/test/Analysis/MemorySSA/renamephis.ll @@ -11,20 +11,20 @@ declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0 ; CHECK-LABEL: @f -define void @f() align 2 { +define void @f( i1 %replaceUndef0, i1 %replaceUndef1) align 2 { entry: %P = alloca ptr, align 8 br label %cond.end.i.i.i.i cond.end.i.i.i.i: ; preds = %cont20, %entry - br i1 undef, label %cont20, label %if.end + br i1 %replaceUndef0, label %cont20, label %if.end cont20: ; preds = %cond.end.i.i.i.i, %cond.end.i.i.i.i, %cond.end.i.i.i.i store ptr undef, ptr %P, align 8 br label %cond.end.i.i.i.i if.end: ; preds = %cond.end.i.i.i.i - br i1 undef, label %cond.exit, label %handler.type_mismatch2.i + br i1 %replaceUndef1, label %cond.exit, label %handler.type_mismatch2.i handler.type_mismatch2.i: ; preds = %if.end tail call void @g() diff --git a/llvm/test/Analysis/MemorySSA/unreachable.ll b/llvm/test/Analysis/MemorySSA/unreachable.ll --- a/llvm/test/Analysis/MemorySSA/unreachable.ll +++ b/llvm/test/Analysis/MemorySSA/unreachable.ll @@ -8,9 +8,9 @@ declare dso_local void @f() ; CHECK-LABEL: @foo -define dso_local void @foo() { +define dso_local void @foo( i1 %replaceUndef0) { entry: - br i1 undef, label %if.then, label %if.end + br i1 %replaceUndef0, label %if.then, label %if.end if.then: ; preds = %entry br label %try.cont diff --git a/llvm/test/Analysis/MemorySSA/update_unroll.ll b/llvm/test/Analysis/MemorySSA/update_unroll.ll --- a/llvm/test/Analysis/MemorySSA/update_unroll.ll +++ b/llvm/test/Analysis/MemorySSA/update_unroll.ll @@ -7,7 +7,7 @@ ; Check verification passes after loop rotate, when adding phis in blocks ; receiving incoming edges and adding phis in IDF blocks. ; CHECK-LABEL: @f -define void @f() align 32 { +define void @f( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) align 32 { entry: br label %while.cond.outer @@ -15,13 +15,13 @@ br label %while.cond.outer while.cond.outer: ; preds = %while.cond80.while.cond.loopexit_crit_edge, %entry - br i1 undef, label %while.cond.outer.return.loopexit2_crit_edge, label %while.body.lr.ph + br i1 %replaceUndef0, label %while.cond.outer.return.loopexit2_crit_edge, label %while.body.lr.ph while.body.lr.ph: ; preds = %while.cond.outer br label %while.body while.body: ; preds = %while.body.lr.ph - br i1 undef, label %if.then42, label %if.end61 + br i1 %replaceUndef1, label %if.then42, label %if.end61 if.then42: ; preds = %while.body br label %return.loopexit2 @@ -30,7 +30,7 @@ br label %while.body82 while.body82: ; preds = %if.end61 - br i1 undef, label %return.loopexit, label %if.else99 + br i1 %replaceUndef2, label %return.loopexit, label %if.else99 if.else99: ; preds = %while.body82 store i32 0, ptr inttoptr (i64 44 to ptr), align 4 diff --git a/llvm/test/Analysis/PhiValues/basic.ll b/llvm/test/Analysis/PhiValues/basic.ll --- a/llvm/test/Analysis/PhiValues/basic.ll +++ b/llvm/test/Analysis/PhiValues/basic.ll @@ -3,9 +3,9 @@ @X = common global i32 0 ; CHECK-LABEL: PHI Values for function: simple -define void @simple(ptr %ptr) { +define void @simple(ptr %ptr, i1 %replaceUndef0) { entry: - br i1 undef, label %if, label %else + br i1 %replaceUndef0, label %if, label %else if: br label %end @@ -26,9 +26,9 @@ } ; CHECK-LABEL: PHI Values for function: chain -define void @chain() { +define void @chain( i1 %replaceUndef0, i1 %replaceUndef1) { entry: - br i1 undef, label %if1, label %else1 + br i1 %replaceUndef0, label %if1, label %else1 if1: br label %middle @@ -41,7 +41,7 @@ ; CHECK-DAG: i32 0 ; CHECK-DAG: i32 1 %phi1 = phi i32 [ 0, %if1 ], [ 1, %else1 ] - br i1 undef, label %if2, label %else2 + br i1 %replaceUndef1, label %if2, label %else2 if2: br label %end @@ -71,7 +71,7 @@ } ; CHECK-LABEL: PHI Values for function: simple_loop -define void @simple_loop() { +define void @simple_loop( i1 %replaceUndef0) { entry: br label %loop @@ -79,23 +79,23 @@ ; CHECK: PHI %phi has values: ; CHECK-DAG: i32 0 %phi = phi i32 [ 0, %entry ], [ %phi, %loop ] - br i1 undef, label %loop, label %end + br i1 %replaceUndef0, label %loop, label %end end: ret void } ; CHECK-LABEL: PHI Values for function: complex_loop -define void @complex_loop() { +define void @complex_loop( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { entry: - br i1 undef, label %loop, label %end + br i1 %replaceUndef0, label %loop, label %end loop: ; CHECK: PHI %phi1 has values: ; CHECK-DAG: i32 0 ; CHECK-DAG: i32 1 %phi1 = phi i32 [ 0, %entry ], [ %phi2, %then ] - br i1 undef, label %if, label %else + br i1 %replaceUndef1, label %if, label %else if: br label %then @@ -108,7 +108,7 @@ ; CHECK-DAG: i32 0 ; CHECK-DAG: i32 1 %phi2 = phi i32 [ %phi1, %if ], [ 1, %else ] - br i1 undef, label %loop, label %end + br i1 %replaceUndef2, label %loop, label %end end: ; CHECK: PHI %phi3 has values: @@ -120,9 +120,9 @@ } ; CHECK-LABEL: PHI Values for function: strange_loop -define void @strange_loop() { +define void @strange_loop( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) { entry: - br i1 undef, label %ifelse, label %inloop + br i1 %replaceUndef0, label %ifelse, label %inloop loop: ; CHECK: PHI %phi1 has values: @@ -131,7 +131,7 @@ ; CHECK-DAG: i32 2 ; CHECK-DAG: i32 3 %phi1 = phi i32 [ %phi3, %if ], [ 0, %else ], [ %phi2, %inloop ] - br i1 undef, label %inloop, label %end + br i1 %replaceUndef1, label %inloop, label %end inloop: ; CHECK: PHI %phi2 has values: @@ -140,14 +140,14 @@ ; CHECK-DAG: i32 2 ; CHECK-DAG: i32 3 %phi2 = phi i32 [ %phi1, %loop ], [ 1, %entry ] - br i1 undef, label %ifelse, label %loop + br i1 %replaceUndef2, label %ifelse, label %loop ifelse: ; CHECK: PHI %phi3 has values: ; CHECK-DAG: i32 2 ; CHECK-DAG: i32 3 %phi3 = phi i32 [ 2, %entry ], [ 3, %inloop ] - br i1 undef, label %if, label %else + br i1 %replaceUndef3, label %if, label %else if: br label %loop @@ -160,9 +160,9 @@ } ; CHECK-LABEL: PHI Values for function: mutual_loops -define void @mutual_loops() { +define void @mutual_loops( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6) { entry: - br i1 undef, label %loop1, label %loop2 + br i1 %replaceUndef0, label %loop1, label %loop2 loop1: ; CHECK: PHI %phi1 has values: @@ -172,10 +172,10 @@ ; CHECK-DAG: 3 ; CHECK-DAG: 4 %phi1 = phi i32 [ 0, %entry ], [ %phi2, %loop1.then ], [ %phi3, %loop2.if ] - br i1 undef, label %loop1.if, label %loop1.else + br i1 %replaceUndef1, label %loop1.if, label %loop1.else loop1.if: - br i1 undef, label %loop1.then, label %loop2 + br i1 %replaceUndef2, label %loop1.then, label %loop2 loop1.else: br label %loop1.then @@ -188,7 +188,7 @@ ; CHECK-DAG: 3 ; CHECK-DAG: 4 %phi2 = phi i32 [ 1, %loop1.if ], [ %phi1, %loop1.else ] - br i1 undef, label %loop1, label %end + br i1 %replaceUndef3, label %loop1, label %end loop2: ; CHECK: PHI %phi3 has values: @@ -196,10 +196,10 @@ ; CHECK-DAG: 3 ; CHECK-DAG: 4 %phi3 = phi i32 [ 2, %entry ], [ %phi4, %loop2.then ], [ 3, %loop1.if ] - br i1 undef, label %loop2.if, label %loop2.else + br i1 %replaceUndef4, label %loop2.if, label %loop2.else loop2.if: - br i1 undef, label %loop2.then, label %loop1 + br i1 %replaceUndef5, label %loop2.then, label %loop1 loop2.else: br label %loop2.then @@ -210,7 +210,7 @@ ; CHECK-DAG: 3 ; CHECK-DAG: 4 %phi4 = phi i32 [ 4, %loop2.if ], [ %phi3, %loop2.else ] - br i1 undef, label %loop2, label %end + br i1 %replaceUndef6, label %loop2, label %end end: ; CHECK: PHI %phi5 has values: @@ -224,7 +224,7 @@ } ; CHECK-LABEL: PHI Values for function: nested_loops_several_values -define void @nested_loops_several_values() { +define void @nested_loops_several_values( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { entry: br label %loop1 @@ -233,14 +233,14 @@ ; CHECK-DAG: i32 0 ; CHECK-DAG: %add %phi1 = phi i32 [ 0, %entry ], [ %phi2, %loop2 ] - br i1 undef, label %loop2, label %end + br i1 %replaceUndef0, label %loop2, label %end loop2: ; CHECK: PHI %phi2 has values: ; CHECK-DAG: i32 0 ; CHECK-DAG: %add %phi2 = phi i32 [ %phi1, %loop1 ], [ %phi3, %loop3 ] - br i1 undef, label %loop3, label %loop1 + br i1 %replaceUndef1, label %loop3, label %loop1 loop3: ; CHECK: PHI %phi3 has values: @@ -248,14 +248,14 @@ ; CHECK-DAG: %add %phi3 = phi i32 [ %add, %loop3 ], [ %phi2, %loop2 ] %add = add i32 %phi3, 1 - br i1 undef, label %loop3, label %loop2 + br i1 %replaceUndef2, label %loop3, label %loop2 end: ret void } ; CHECK-LABEL: PHI Values for function: nested_loops_one_value -define void @nested_loops_one_value() { +define void @nested_loops_one_value( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { entry: br label %loop1 @@ -263,19 +263,19 @@ ; CHECK: PHI %phi1 has values: ; CHECK-DAG: i32 0 %phi1 = phi i32 [ 0, %entry ], [ %phi2, %loop2 ] - br i1 undef, label %loop2, label %end + br i1 %replaceUndef0, label %loop2, label %end loop2: ; CHECK: PHI %phi2 has values: ; CHECK-DAG: i32 0 %phi2 = phi i32 [ %phi1, %loop1 ], [ %phi3, %loop3 ] - br i1 undef, label %loop3, label %loop1 + br i1 %replaceUndef1, label %loop3, label %loop1 loop3: ; CHECK: PHI %phi3 has values: ; CHECK-DAG: i32 0 %phi3 = phi i32 [ 0, %loop3 ], [ %phi2, %loop2 ] - br i1 undef, label %loop3, label %loop2 + br i1 %replaceUndef2, label %loop3, label %loop2 end: ret void diff --git a/llvm/test/Analysis/PhiValues/long_phi_chain.ll b/llvm/test/Analysis/PhiValues/long_phi_chain.ll --- a/llvm/test/Analysis/PhiValues/long_phi_chain.ll +++ b/llvm/test/Analysis/PhiValues/long_phi_chain.ll @@ -4,7 +4,7 @@ ; phi values analysis to segfault if it's not careful about that kind of thing. ; CHECK-LABEL: PHI Values for function: fn -define void @fn(ptr %arg) { +define void @fn(ptr %arg, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13) { entry: br label %while1.cond @@ -12,10 +12,10 @@ ; CHECK: PHI %phi1 has values: ; CHECK: ptr %arg %phi1 = phi ptr [ %arg, %entry ], [ %phi2, %while1.then ] - br i1 undef, label %while1.end, label %while1.body + br i1 %replaceUndef0, label %while1.end, label %while1.body while1.body: - br i1 undef, label %while1.then, label %while1.if + br i1 %replaceUndef1, label %while1.then, label %while1.if while1.if: br label %while1.then @@ -33,16 +33,16 @@ ; CHECK: PHI %phi3 has values: ; CHECK: ptr %arg %phi3 = phi ptr [ %phi1, %while1.end ], [ %phi5, %while2.then ] - br i1 undef, label %while2.end, label %while2.body1 + br i1 %replaceUndef2, label %while2.end, label %while2.body1 while2.body1: - br i1 undef, label %while2.cond2, label %while2.then + br i1 %replaceUndef3, label %while2.cond2, label %while2.then while2.cond2: ; CHECK: PHI %phi4 has values: ; CHECK: ptr %arg %phi4 = phi ptr [ %phi3, %while2.body1 ], [ %phi4, %while2.if ] - br i1 undef, label %while2.then, label %while2.if + br i1 %replaceUndef4, label %while2.then, label %while2.if while2.if: br label %while2.cond2 @@ -60,13 +60,13 @@ ; CHECK: PHI %phi6 has values: ; CHECK: ptr %arg %phi6 = phi ptr [ %phi3, %while2.end ], [ %phi7, %while3.cond2 ] - br i1 undef, label %while3.end, label %while3.cond2 + br i1 %replaceUndef5, label %while3.end, label %while3.cond2 while3.cond2: ; CHECK: PHI %phi7 has values: ; CHECK: ptr %arg %phi7 = phi ptr [ %phi6, %while3.cond1 ], [ %phi7, %while3.body ] - br i1 undef, label %while3.cond1, label %while3.body + br i1 %replaceUndef6, label %while3.cond1, label %while3.body while3.body: br label %while3.cond2 @@ -78,16 +78,16 @@ ; CHECK: PHI %phi8 has values: ; CHECK: ptr %arg %phi8 = phi ptr [ %phi6, %while3.end ], [ %phi10, %while4.then ] - br i1 undef, label %while4.end, label %while4.if + br i1 %replaceUndef7, label %while4.end, label %while4.if while4.if: - br i1 undef, label %while4.cond2, label %while4.then + br i1 %replaceUndef8, label %while4.cond2, label %while4.then while4.cond2: ; CHECK: PHI %phi9 has values: ; CHECK: ptr %arg %phi9 = phi ptr [ %phi8, %while4.if ], [ %phi9, %while4.body ] - br i1 undef, label %while4.then, label %while4.body + br i1 %replaceUndef9, label %while4.then, label %while4.body while4.body: br label %while4.cond2 @@ -105,16 +105,16 @@ ; CHECK: PHI %phi11 has values: ; CHECK: ptr %arg %phi11 = phi ptr [ %phi8, %while4.end ], [ %phi13, %while5.then ] - br i1 undef, label %while5.end, label %while5.body1 + br i1 %replaceUndef10, label %while5.end, label %while5.body1 while5.body1: - br i1 undef, label %while5.if, label %while5.then + br i1 %replaceUndef11, label %while5.if, label %while5.then while5.if: ; CHECK: PHI %phi12 has values: ; CHECK: ptr %arg %phi12 = phi ptr [ %phi11, %while5.body1 ], [ %phi12, %while5.body2 ] - br i1 undef, label %while5.then, label %while5.body2 + br i1 %replaceUndef12, label %while5.then, label %while5.body2 while5.body2: br label %while5.if @@ -132,7 +132,7 @@ ; CHECK: PHI %phi14 has values: ; CHECK: ptr %arg %phi14 = phi ptr [ %phi11, %while5.end ], [ %phi14, %while6.cond1 ] - br i1 undef, label %while6.cond2, label %while6.cond1 + br i1 %replaceUndef13, label %while6.cond2, label %while6.cond1 while6.cond2: ; CHECK: PHI %phi15 has values: diff --git a/llvm/test/Analysis/PostDominators/pr6047_a.ll b/llvm/test/Analysis/PostDominators/pr6047_a.ll --- a/llvm/test/Analysis/PostDominators/pr6047_a.ll +++ b/llvm/test/Analysis/PostDominators/pr6047_a.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -passes='print' 2>&1 | FileCheck %s -define internal void @f() { +define internal void @f( i1 %replaceUndef0) { entry: - br i1 undef, label %bb35, label %bb3.i + br i1 %replaceUndef0, label %bb35, label %bb3.i bb3.i: br label %bb3.i diff --git a/llvm/test/Analysis/PostDominators/pr6047_b.ll b/llvm/test/Analysis/PostDominators/pr6047_b.ll --- a/llvm/test/Analysis/PostDominators/pr6047_b.ll +++ b/llvm/test/Analysis/PostDominators/pr6047_b.ll @@ -1,10 +1,10 @@ ; RUN: opt < %s -passes='print' 2>&1 | FileCheck %s -define internal void @f() { +define internal void @f( i1 %replaceUndef0, i1 %replaceUndef1) { entry: - br i1 undef, label %a, label %bb3.i + br i1 %replaceUndef0, label %a, label %bb3.i a: - br i1 undef, label %bb35, label %bb3.i + br i1 %replaceUndef1, label %bb35, label %bb3.i bb3.i: br label %bb3.i diff --git a/llvm/test/Analysis/PostDominators/pr6047_c.ll b/llvm/test/Analysis/PostDominators/pr6047_c.ll --- a/llvm/test/Analysis/PostDominators/pr6047_c.ll +++ b/llvm/test/Analysis/PostDominators/pr6047_c.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -passes='print' 2>&1 | FileCheck %s -define internal void @f() { +define internal void @f( i1 %replaceUndef0) { entry: - br i1 undef, label %bb35, label %bb3.i + br i1 %replaceUndef0, label %bb35, label %bb3.i bb3.i: br label %bb3.i diff --git a/llvm/test/Analysis/PostDominators/pr6047_d.ll b/llvm/test/Analysis/PostDominators/pr6047_d.ll --- a/llvm/test/Analysis/PostDominators/pr6047_d.ll +++ b/llvm/test/Analysis/PostDominators/pr6047_d.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -passes='print' 2>&1 | FileCheck %s -define internal void @f() { +define internal void @f( i1 %replaceUndef0) { entry: br i1 1, label %a, label %b @@ -10,7 +10,7 @@ br label %c c: - br i1 undef, label %bb35, label %bb3.i + br i1 %replaceUndef0, label %bb35, label %bb3.i bb3.i: br label %bb3.i diff --git a/llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll b/llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll --- a/llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll +++ b/llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll @@ -2,7 +2,7 @@ ; PR9633: Tests that SCEV handles the mul.i2 recurrence being folded to ; constant zero. -define signext i8 @func_14(i8 signext %p_18) nounwind readnone ssp { +define signext i8 @func_14(i8 signext %p_18, i1 %replaceUndef0) nounwind readnone ssp { entry: br label %for.inc @@ -16,7 +16,7 @@ %shl.i = select i1 %tobool.i, i32 13, i32 0 %shl.left.i = shl i32 %add, %shl.i %conv.i4 = trunc i32 %shl.left.i to i8 - br i1 undef, label %for.inc9, label %if.then + br i1 %replaceUndef0, label %for.inc9, label %if.then for.inc9: %p_18.addr.011 = phi i8 [ %add12, %for.inc9 ], [ %p_18, %for.cond ] diff --git a/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll b/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll --- a/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll +++ b/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll @@ -36,7 +36,7 @@ ; PR10383 ; These next two used to crash. -define void @test2(i1 %cmp, i64 %n) { +define void @test2(i1 %cmp, i64 %n, i1 %replaceUndef0) { entry: br label %for.body1 @@ -54,16 +54,16 @@ %tmp114 = mul i64 %a0.08, %indvar %mul542 = mul i64 %tmp114, %tmp111 %indvar.next = add i64 %indvar, 1 - br i1 undef, label %end, label %for.body2 + br i1 %replaceUndef0, label %end, label %for.body2 end: ret void } ; CHECK: Determining loop execution counts for: @test2 -define i32 @test3() { +define i32 @test3( i1 %replaceUndef0, i1 %replaceUndef1) { if.then466: - br i1 undef, label %for.cond539.preheader, label %for.inc479 + br i1 %replaceUndef0, label %for.cond539.preheader, label %for.inc479 for.inc479: %a2.07 = phi i32 [ %add495, %for.inc479 ], [ 0, %if.then466 ] @@ -73,7 +73,7 @@ %mul493 = mul i32 %mul491, %mul484 %add495 = add nsw i32 %mul493, %a2.07 %inc497 = add nsw i32 %j.36, 1 - br i1 undef, label %for.cond539.preheader, label %for.inc479 + br i1 %replaceUndef1, label %for.cond539.preheader, label %for.inc479 for.cond539.preheader: unreachable diff --git a/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll b/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll --- a/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll +++ b/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll @@ -5,14 +5,14 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" -define i32 @test() { +define i32 @test( i1 %replaceUndef0) { entry: %0 = load ptr, ptr undef, align 8 ; [#uses=1] %1 = ptrtoint ptr %0 to i64 ; [#uses=1] %2 = sub i64 undef, %1 ; [#uses=1] %3 = lshr i64 %2, 3 ; [#uses=1] %4 = trunc i64 %3 to i32 ; [#uses=2] - br i1 undef, label %bb10, label %bb4.i + br i1 %replaceUndef0, label %bb10, label %bb4.i bb4.i: ; preds = %bb4.i, %entry %i.0.i6 = phi i32 [ %8, %bb4.i ], [ 0, %entry ] ; [#uses=2] diff --git a/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll b/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll --- a/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll +++ b/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll @@ -207,9 +207,9 @@ %union.pager_info = type <{ [4 x i8] }> %union.sigval = type <{ [8 x i8] }> -define i32 @vlrureclaim(ptr %mp) nounwind { +define i32 @vlrureclaim(ptr %mp, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18, i1 %replaceUndef19, i1 %replaceUndef20, i1 %replaceUndef21, i1 %replaceUndef22) nounwind { entry: - br i1 undef, label %if.then11, label %do.end + br i1 %replaceUndef0, label %if.then11, label %do.end if.then11: ; preds = %entry br label %do.end @@ -230,19 +230,19 @@ br label %while.cond27 while.cond27: ; preds = %while.body36, %while.body - br i1 undef, label %do.body288.loopexit, label %land.rhs + br i1 %replaceUndef1, label %do.body288.loopexit, label %land.rhs land.rhs: ; preds = %while.cond27 - br i1 undef, label %while.body36, label %while.end + br i1 %replaceUndef2, label %while.body36, label %while.end while.body36: ; preds = %land.rhs br label %while.cond27 while.end: ; preds = %land.rhs - br i1 undef, label %do.body288.loopexit4, label %do.body46 + br i1 %replaceUndef3, label %do.body288.loopexit4, label %do.body46 do.body46: ; preds = %while.end - br i1 undef, label %if.else64, label %if.then53 + br i1 %replaceUndef4, label %if.else64, label %if.then53 if.then53: ; preds = %do.body46 br label %if.end72 @@ -252,58 +252,58 @@ if.end72: ; preds = %if.else64, %if.then53 %dec = add i32 %count.0, -1 ; [#uses=2] - br i1 undef, label %next_iter, label %if.end111 + br i1 %replaceUndef5, label %next_iter, label %if.end111 if.end111: ; preds = %if.end72 - br i1 undef, label %lor.lhs.false, label %do.body145 + br i1 %replaceUndef6, label %lor.lhs.false, label %do.body145 lor.lhs.false: ; preds = %if.end111 - br i1 undef, label %lor.lhs.false122, label %do.body145 + br i1 %replaceUndef7, label %lor.lhs.false122, label %do.body145 lor.lhs.false122: ; preds = %lor.lhs.false - br i1 undef, label %lor.lhs.false128, label %do.body145 + br i1 %replaceUndef8, label %lor.lhs.false128, label %do.body145 lor.lhs.false128: ; preds = %lor.lhs.false122 - br i1 undef, label %do.body162, label %land.lhs.true + br i1 %replaceUndef9, label %do.body162, label %land.lhs.true land.lhs.true: ; preds = %lor.lhs.false128 - br i1 undef, label %do.body145, label %do.body162 + br i1 %replaceUndef10, label %do.body145, label %do.body162 do.body145: ; preds = %land.lhs.true, %lor.lhs.false122, %lor.lhs.false, %if.end111 - br i1 undef, label %if.then156, label %next_iter + br i1 %replaceUndef11, label %if.then156, label %next_iter if.then156: ; preds = %do.body145 br label %next_iter do.body162: ; preds = %land.lhs.true, %lor.lhs.false128 - br i1 undef, label %if.then173, label %do.end177 + br i1 %replaceUndef12, label %if.then173, label %do.end177 if.then173: ; preds = %do.body162 br label %do.end177 do.end177: ; preds = %if.then173, %do.body162 - br i1 undef, label %do.body185, label %if.then182 + br i1 %replaceUndef13, label %do.body185, label %if.then182 if.then182: ; preds = %do.end177 br label %next_iter_mntunlocked do.body185: ; preds = %do.end177 - br i1 undef, label %if.then196, label %do.end202 + br i1 %replaceUndef14, label %if.then196, label %do.end202 if.then196: ; preds = %do.body185 br label %do.end202 do.end202: ; preds = %if.then196, %do.body185 - br i1 undef, label %lor.lhs.false207, label %if.then231 + br i1 %replaceUndef15, label %lor.lhs.false207, label %if.then231 lor.lhs.false207: ; preds = %do.end202 - br i1 undef, label %lor.lhs.false214, label %if.then231 + br i1 %replaceUndef16, label %lor.lhs.false214, label %if.then231 lor.lhs.false214: ; preds = %lor.lhs.false207 - br i1 undef, label %do.end236, label %land.lhs.true221 + br i1 %replaceUndef17, label %do.end236, label %land.lhs.true221 land.lhs.true221: ; preds = %lor.lhs.false214 - br i1 undef, label %if.then231, label %do.end236 + br i1 %replaceUndef18, label %if.then231, label %do.end236 if.then231: ; preds = %land.lhs.true221, %lor.lhs.false207, %do.end202 br label %next_iter_mntunlocked @@ -312,7 +312,7 @@ br label %next_iter_mntunlocked next_iter_mntunlocked: ; preds = %do.end236, %if.then231, %if.then182 - br i1 undef, label %yield, label %do.body269 + br i1 %replaceUndef19, label %yield, label %do.body269 next_iter: ; preds = %if.then156, %do.body145, %if.end72 %rem2482 = and i32 %dec, 255 ; [#uses=1] @@ -320,7 +320,7 @@ br i1 %cmp249, label %do.body253, label %while.cond do.body253: ; preds = %next_iter - br i1 undef, label %if.then264, label %yield + br i1 %replaceUndef20, label %if.then264, label %yield if.then264: ; preds = %do.body253 br label %yield @@ -329,7 +329,7 @@ br label %do.body269 do.body269: ; preds = %yield, %next_iter_mntunlocked - br i1 undef, label %if.then280, label %while.cond.outer.backedge + br i1 %replaceUndef21, label %if.then280, label %while.cond.outer.backedge if.then280: ; preds = %do.body269 br label %while.cond.outer.backedge @@ -344,7 +344,7 @@ br label %do.body288 do.body288: ; preds = %do.body288.loopexit4, %do.body288.loopexit - br i1 undef, label %if.then299, label %do.end303 + br i1 %replaceUndef22, label %if.then299, label %do.end303 if.then299: ; preds = %do.body288 br label %do.end303 diff --git a/llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll b/llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll --- a/llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll +++ b/llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll @@ -261,7 +261,7 @@ ; Another mix of previous use cases that demonstrates that incorrect picking of ; a loop for a recurrence may cause a crash of SCEV analysis. -define void @test_04() { +define void @test_04( i1 %replaceUndef0) { ; CHECK-LABEL: Classifying expressions for: @test_04 ; CHECK: %tmp = phi i64 [ 2, %bb ], [ %tmp4, %bb3 ] @@ -290,7 +290,7 @@ loop1: %tmp = phi i64 [ 2, %bb ], [ %tmp4, %bb3 ] %tmp2 = trunc i64 %tmp to i32 - br i1 undef, label %loop2, label %bb3 + br i1 %replaceUndef0, label %loop2, label %bb3 bb3: %tmp4 = add nuw nsw i64 %tmp, 1 diff --git a/llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll b/llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll --- a/llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll +++ b/llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll @@ -6,10 +6,10 @@ ; SCEVExpander would try to RAUW %val_2 with %c.lcssa, breaking "def ; dominates uses". -define void @pr27232(i32 %val) { +define void @pr27232(i32 %val, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: @pr27232( entry: - br i1 undef, label %loop_0.cond, label %for.body.us + br i1 %replaceUndef0, label %loop_0.cond, label %for.body.us for.body.us: br label %loop_0.cond @@ -29,12 +29,12 @@ br label %loop_1 loop_0: - br i1 undef, label %loop_0, label %loop_1.exit + br i1 %replaceUndef1, label %loop_0, label %loop_1.exit loop_1: %d.1 = phi i32 [ %c.lcssa, %loop_1 ], [ %val_2, %loop_1.ph ] %t.1 = phi i32 [ %val_2, %loop_1 ], [ %c.lcssa, %loop_1.ph ] - br i1 undef, label %leave, label %loop_1 + br i1 %replaceUndef2, label %leave, label %loop_1 leave: ret void @@ -44,10 +44,10 @@ ; @ReplaceArg_0 and @ReplaceArg_1 used to trigger a failed cast<> ; assertion in SCEVExpander. -define void @ReplaceArg_0(i32 %val) { +define void @ReplaceArg_0(i32 %val, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: @ReplaceArg_0( entry: - br i1 undef, label %loop_0.cond, label %for.body.us + br i1 %replaceUndef0, label %loop_0.cond, label %for.body.us for.body.us: br label %loop_0.cond @@ -66,21 +66,21 @@ br label %loop_1 loop_0: - br i1 undef, label %loop_0, label %loop_1.exit + br i1 %replaceUndef1, label %loop_0, label %loop_1.exit loop_1: %d.1 = phi i32 [ %c.lcssa, %loop_1 ], [ %val, %loop_1.ph ] %t.1 = phi i32 [ %val, %loop_1 ], [ %c.lcssa, %loop_1.ph ] - br i1 undef, label %leave, label %loop_1 + br i1 %replaceUndef2, label %leave, label %loop_1 leave: ret void } -define void @ReplaceArg_1(i32 %val) { +define void @ReplaceArg_1(i32 %val, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { ; CHECK-LABEL: @ReplaceArg_1( entry: - br i1 undef, label %loop_0.cond, label %for.body.us + br i1 %replaceUndef0, label %loop_0.cond, label %for.body.us for.body.us: br label %loop_0.cond @@ -99,12 +99,12 @@ br label %loop_1 loop_0: - br i1 undef, label %loop_0, label %loop_1.exit + br i1 %replaceUndef1, label %loop_0, label %loop_1.exit loop_1: %t.1 = phi i32 [ %val, %loop_1 ], [ %c.lcssa, %loop_1.ph ] %d.1 = phi i32 [ %c.lcssa, %loop_1 ], [ %val, %loop_1.ph ] - br i1 undef, label %leave, label %loop_1 + br i1 %replaceUndef2, label %leave, label %loop_1 leave: ret void diff --git a/llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll b/llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll --- a/llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll +++ b/llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -disable-output "-passes=print" 2>&1 | FileCheck %s ; PR13228 -define void @f() nounwind uwtable readnone { +define void @f( i1 %replaceUndef0) nounwind uwtable readnone { entry: br label %for.cond @@ -14,7 +14,7 @@ while.cond: ; preds = %while.body, %for.cond %b.2 = phi i8 [ %add, %while.body ], [ 0, %for.cond ] - br i1 undef, label %while.end, label %while.body + br i1 %replaceUndef0, label %while.end, label %while.body while.body: ; preds = %while.cond %add = add i8 %b.2, %c.0 diff --git a/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll --- a/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll @@ -8,7 +8,7 @@ declare { i16, i1 } @llvm.smul.with.overflow.i16(i16, i16) nounwind readnone declare { i16, i1 } @llvm.umul.with.overflow.i16(i16, i16) nounwind readnone -define void @uadd_exhaustive() { +define void @uadd_exhaustive( i1 %replaceUndef0) { ; CHECK-LABEL: 'uadd_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @uadd_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 35 @@ -19,7 +19,7 @@ ; CHECK: Loop %for.body: Trip multiple is 36 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -35,7 +35,7 @@ ret void } -define void @sadd_exhaustive() { +define void @sadd_exhaustive( i1 %replaceUndef0) { ; CHECK-LABEL: 'sadd_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @sadd_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 67 @@ -46,7 +46,7 @@ ; CHECK: Loop %for.body: Trip multiple is 68 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -62,7 +62,7 @@ ret void } -define void @usub_exhaustive() { +define void @usub_exhaustive( i1 %replaceUndef0) { ; CHECK-LABEL: 'usub_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @usub_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 50 @@ -73,7 +73,7 @@ ; CHECK: Loop %for.body: Trip multiple is 51 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -89,7 +89,7 @@ ret void } -define void @ssub_exhaustive() { +define void @ssub_exhaustive( i1 %replaceUndef0) { ; CHECK-LABEL: 'ssub_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @ssub_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 68 @@ -100,7 +100,7 @@ ; CHECK: Loop %for.body: Trip multiple is 69 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -116,7 +116,7 @@ ret void } -define void @smul_exhaustive() { +define void @smul_exhaustive( i1 %replaceUndef0) { ; CHECK-LABEL: 'smul_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @smul_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 14 @@ -127,7 +127,7 @@ ; CHECK: Loop %for.body: Trip multiple is 15 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -143,7 +143,7 @@ ret void } -define void @umul_exhaustive() { +define void @umul_exhaustive( i1 %replaceUndef0) { ; CHECK-LABEL: 'umul_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @umul_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 15 @@ -154,7 +154,7 @@ ; CHECK: Loop %for.body: Trip multiple is 16 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -170,7 +170,7 @@ ret void } -define void @uadd_symbolic_start(i16 %start) { +define void @uadd_symbolic_start(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'uadd_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @uadd_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (-1 * %start)) @@ -181,7 +181,7 @@ ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -197,7 +197,7 @@ ret void } -define void @sadd_symbolic_start(i16 %start) { +define void @sadd_symbolic_start(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'sadd_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (32767 + (-1 * %start)) @@ -208,7 +208,7 @@ ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -224,7 +224,7 @@ ret void } -define void @sadd_symbolic_start2(i16 %start) { +define void @sadd_symbolic_start2(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'sadd_symbolic_start2' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_start2 ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. @@ -233,7 +233,7 @@ ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -250,7 +250,7 @@ ret void } -define void @sadd_symbolic_swapped(i16 %start) { +define void @sadd_symbolic_swapped(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'sadd_symbolic_swapped' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_swapped ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. @@ -259,7 +259,7 @@ ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -275,7 +275,7 @@ ret void } -define void @usub_symbolic_start(i16 %start) { +define void @usub_symbolic_start(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'usub_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @usub_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is %start @@ -286,7 +286,7 @@ ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -302,7 +302,7 @@ ret void } -define void @ssub_symbolic_start(i16 %start) { +define void @ssub_symbolic_start(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'ssub_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @ssub_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-32768 + %start) @@ -313,7 +313,7 @@ ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -329,7 +329,7 @@ ret void } -define void @smul_symbolic_start(i16 %start) { +define void @smul_symbolic_start(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'smul_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @smul_symbolic_start ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. @@ -338,7 +338,7 @@ ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -354,7 +354,7 @@ ret void } -define void @umul_symbolic_start(i16 %start) { +define void @umul_symbolic_start(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'umul_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @umul_symbolic_start ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. @@ -363,7 +363,7 @@ ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body @@ -379,7 +379,7 @@ ret void } -define void @sadd_symbolic_non_latch(i16 %start) { +define void @sadd_symbolic_non_latch(i16 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'sadd_symbolic_non_latch' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_non_latch ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((230 + (-1 * %start)) umin (32767 + (-1 * %start))) @@ -394,7 +394,7 @@ ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: - br i1 undef, label %for.end, label %for.body.preheader + br i1 %replaceUndef0, label %for.end, label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body diff --git a/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll b/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll --- a/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll +++ b/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll @@ -3,9 +3,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" %JavaObject = type { ptr, ptr } -define void @JnJVM_antlr_CSharpCodeGenerator_genBitSet__Lantlr_collections_impl_BitSet_2I(ptr, ptr, i32) { +define void @JnJVM_antlr_CSharpCodeGenerator_genBitSet__Lantlr_collections_impl_BitSet_2I(ptr, ptr, i32, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18, i1 %replaceUndef19, i1 %replaceUndef20, i1 %replaceUndef21, i1 %replaceUndef22, i1 %replaceUndef23, i1 %replaceUndef24, i1 %replaceUndef25, i1 %replaceUndef26, i1 %replaceUndef27, i1 %replaceUndef28, i1 %replaceUndef29, i1 %replaceUndef30, i1 %replaceUndef31, i1 %replaceUndef32) { start: - br i1 undef, label %"stack overflow", label %"no stack overflow" + br i1 %replaceUndef0, label %"stack overflow", label %"no stack overflow" "GOTO or IF*2": ; preds = %"true verifyAndComputePtr89", %verifyNullCont84 unreachable @@ -27,151 +27,151 @@ ret void "no stack overflow": ; preds = %start - br i1 undef, label %verifyNullCont, label %"no stack overflow.end_crit_edge" + br i1 %replaceUndef1, label %verifyNullCont, label %"no stack overflow.end_crit_edge" "no stack overflow.end_crit_edge": ; preds = %"no stack overflow" ret void verifyNullCont: ; preds = %"no stack overflow" - br i1 undef, label %verifyNullCont9, label %verifyNullCont.end_crit_edge + br i1 %replaceUndef2, label %verifyNullCont9, label %verifyNullCont.end_crit_edge verifyNullCont.end_crit_edge: ; preds = %verifyNullCont ret void verifyNullCont9: ; preds = %verifyNullCont - br i1 undef, label %verifyNullCont12, label %verifyNullCont9.end_crit_edge + br i1 %replaceUndef3, label %verifyNullCont12, label %verifyNullCont9.end_crit_edge verifyNullCont9.end_crit_edge: ; preds = %verifyNullCont9 ret void verifyNullCont12: ; preds = %verifyNullCont9 - br i1 undef, label %"no exception block13", label %verifyNullCont12.end_crit_edge + br i1 %replaceUndef4, label %"no exception block13", label %verifyNullCont12.end_crit_edge verifyNullCont12.end_crit_edge: ; preds = %verifyNullCont12 ret void "no exception block13": ; preds = %verifyNullCont12 - br i1 undef, label %verifyNullExit14, label %verifyNullCont15 + br i1 %replaceUndef5, label %verifyNullExit14, label %verifyNullCont15 verifyNullExit14: ; preds = %"no exception block13" ret void verifyNullCont15: ; preds = %"no exception block13" - br i1 undef, label %"no exception block16", label %verifyNullCont15.end_crit_edge + br i1 %replaceUndef6, label %"no exception block16", label %verifyNullCont15.end_crit_edge verifyNullCont15.end_crit_edge: ; preds = %verifyNullCont15 ret void "no exception block16": ; preds = %verifyNullCont15 - br i1 undef, label %verifyNullExit17, label %verifyNullCont18 + br i1 %replaceUndef7, label %verifyNullExit17, label %verifyNullCont18 verifyNullExit17: ; preds = %"no exception block16" ret void verifyNullCont18: ; preds = %"no exception block16" - br i1 undef, label %"no exception block19", label %verifyNullCont18.end_crit_edge + br i1 %replaceUndef8, label %"no exception block19", label %verifyNullCont18.end_crit_edge verifyNullCont18.end_crit_edge: ; preds = %verifyNullCont18 ret void "no exception block19": ; preds = %verifyNullCont18 - br i1 undef, label %verifyNullExit20, label %verifyNullCont21 + br i1 %replaceUndef9, label %verifyNullExit20, label %verifyNullCont21 verifyNullExit20: ; preds = %"no exception block19" ret void verifyNullCont21: ; preds = %"no exception block19" - br i1 undef, label %verifyNullCont24, label %verifyNullCont21.end_crit_edge + br i1 %replaceUndef10, label %verifyNullCont24, label %verifyNullCont21.end_crit_edge verifyNullCont21.end_crit_edge: ; preds = %verifyNullCont21 ret void verifyNullCont24: ; preds = %verifyNullCont21 - br i1 undef, label %verifyNullCont27, label %verifyNullCont24.end_crit_edge + br i1 %replaceUndef11, label %verifyNullCont27, label %verifyNullCont24.end_crit_edge verifyNullCont24.end_crit_edge: ; preds = %verifyNullCont24 ret void verifyNullCont27: ; preds = %verifyNullCont24 - br i1 undef, label %verifyNullCont32, label %verifyNullCont27.end_crit_edge + br i1 %replaceUndef12, label %verifyNullCont32, label %verifyNullCont27.end_crit_edge verifyNullCont27.end_crit_edge: ; preds = %verifyNullCont27 ret void verifyNullCont32: ; preds = %verifyNullCont27 - br i1 undef, label %verifyNullExit33, label %verifyNullCont34 + br i1 %replaceUndef13, label %verifyNullExit33, label %verifyNullCont34 verifyNullExit33: ; preds = %verifyNullCont32 ret void verifyNullCont34: ; preds = %verifyNullCont32 - br i1 undef, label %"no exception block35", label %verifyNullCont34.end_crit_edge + br i1 %replaceUndef14, label %"no exception block35", label %verifyNullCont34.end_crit_edge verifyNullCont34.end_crit_edge: ; preds = %verifyNullCont34 ret void "no exception block35": ; preds = %verifyNullCont34 - br i1 undef, label %end, label %verifyNullCont60 + br i1 %replaceUndef15, label %end, label %verifyNullCont60 verifyNullCont60: ; preds = %"no exception block35" - br i1 undef, label %verifyNullCont63, label %verifyNullCont60.end_crit_edge + br i1 %replaceUndef16, label %verifyNullCont63, label %verifyNullCont60.end_crit_edge verifyNullCont60.end_crit_edge: ; preds = %verifyNullCont60 ret void verifyNullCont63: ; preds = %verifyNullCont60 - br i1 undef, label %"no exception block64", label %verifyNullCont63.end_crit_edge + br i1 %replaceUndef17, label %"no exception block64", label %verifyNullCont63.end_crit_edge verifyNullCont63.end_crit_edge: ; preds = %verifyNullCont63 ret void "no exception block64": ; preds = %verifyNullCont63 - br i1 undef, label %verifyNullExit65, label %verifyNullCont66 + br i1 %replaceUndef18, label %verifyNullExit65, label %verifyNullCont66 verifyNullExit65: ; preds = %"no exception block64" ret void verifyNullCont66: ; preds = %"no exception block64" - br i1 undef, label %"no exception block67", label %verifyNullCont66.end_crit_edge + br i1 %replaceUndef19, label %"no exception block67", label %verifyNullCont66.end_crit_edge verifyNullCont66.end_crit_edge: ; preds = %verifyNullCont66 ret void "no exception block67": ; preds = %verifyNullCont66 - br i1 undef, label %verifyNullExit68, label %verifyNullCont69 + br i1 %replaceUndef20, label %verifyNullExit68, label %verifyNullCont69 verifyNullExit68: ; preds = %"no exception block67" ret void verifyNullCont69: ; preds = %"no exception block67" - br i1 undef, label %"no exception block70", label %verifyNullCont69.end_crit_edge + br i1 %replaceUndef21, label %"no exception block70", label %verifyNullCont69.end_crit_edge verifyNullCont69.end_crit_edge: ; preds = %verifyNullCont69 ret void "no exception block70": ; preds = %verifyNullCont69 - br i1 undef, label %verifyNullExit71, label %verifyNullCont72 + br i1 %replaceUndef22, label %verifyNullExit71, label %verifyNullCont72 verifyNullExit71: ; preds = %"no exception block70" ret void verifyNullCont72: ; preds = %"no exception block70" - br i1 undef, label %verifyNullCont75, label %verifyNullCont72.end_crit_edge + br i1 %replaceUndef23, label %verifyNullCont75, label %verifyNullCont72.end_crit_edge verifyNullCont72.end_crit_edge: ; preds = %verifyNullCont72 ret void verifyNullCont75: ; preds = %verifyNullCont72 - br i1 undef, label %verifyNullCont78, label %verifyNullCont75.end_crit_edge + br i1 %replaceUndef24, label %verifyNullCont78, label %verifyNullCont75.end_crit_edge verifyNullCont75.end_crit_edge: ; preds = %verifyNullCont75 ret void verifyNullCont78: ; preds = %verifyNullCont75 - br i1 undef, label %"verifyNullCont78.GOTO or IF*4_crit_edge", label %verifyNullCont78.end_crit_edge + br i1 %replaceUndef25, label %"verifyNullCont78.GOTO or IF*4_crit_edge", label %verifyNullCont78.end_crit_edge "verifyNullCont78.GOTO or IF*4_crit_edge": ; preds = %verifyNullCont78 - br i1 undef, label %verifyNullExit80, label %verifyNullCont81 + br i1 %replaceUndef26, label %verifyNullExit80, label %verifyNullCont81 verifyNullCont78.end_crit_edge: ; preds = %verifyNullCont78 ret void @@ -185,28 +185,28 @@ br i1 %5, label %verifyNullCont84, label %verifyNullCont172 verifyNullCont84: ; preds = %verifyNullCont81 - br i1 undef, label %"GOTO or IF*2", label %verifyNullCont86 + br i1 %replaceUndef27, label %"GOTO or IF*2", label %verifyNullCont86 verifyNullCont86: ; preds = %verifyNullCont84 - br i1 undef, label %"true verifyAndComputePtr", label %"false verifyAndComputePtr" + br i1 %replaceUndef28, label %"true verifyAndComputePtr", label %"false verifyAndComputePtr" "true verifyAndComputePtr": ; preds = %verifyNullCont86 - br i1 undef, label %"true verifyAndComputePtr89", label %"false verifyAndComputePtr90" + br i1 %replaceUndef29, label %"true verifyAndComputePtr89", label %"false verifyAndComputePtr90" "false verifyAndComputePtr": ; preds = %verifyNullCont86 ret void "true verifyAndComputePtr89": ; preds = %"true verifyAndComputePtr" - br i1 undef, label %"GOTO or IF*6", label %"GOTO or IF*2" + br i1 %replaceUndef30, label %"GOTO or IF*6", label %"GOTO or IF*2" "false verifyAndComputePtr90": ; preds = %"true verifyAndComputePtr" ret void verifyNullCont126: ; preds = %"GOTO or IF*6" - br i1 undef, label %"true verifyAndComputePtr127", label %"false verifyAndComputePtr128" + br i1 %replaceUndef31, label %"true verifyAndComputePtr127", label %"false verifyAndComputePtr128" "true verifyAndComputePtr127": ; preds = %verifyNullCont126 - br i1 undef, label %"true verifyAndComputePtr131.GOTO or IF*6_crit_edge", label %"GOTO or IF*5" + br i1 %replaceUndef32, label %"true verifyAndComputePtr131.GOTO or IF*6_crit_edge", label %"GOTO or IF*5" "false verifyAndComputePtr128": ; preds = %verifyNullCont126 ret void diff --git a/llvm/test/Analysis/ScalarEvolution/pr22674.ll b/llvm/test/Analysis/ScalarEvolution/pr22674.ll --- a/llvm/test/Analysis/ScalarEvolution/pr22674.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr22674.ll @@ -11,12 +11,12 @@ %"class.llvm::AttributeImpl.2.1802.3601.5914.6685.7456.8227.9255.9769.10026.18508" = type <{ ptr, %"class.llvm::FoldingSetImpl::Node.1.1801.3600.5913.6684.7455.8226.9254.9768.10025.18505", i8, [3 x i8] }> ; Function Attrs: nounwind uwtable -define void @_ZNK4llvm11AttrBuilder13hasAttributesENS_12AttributeSetEy() #0 align 2 { +define void @_ZNK4llvm11AttrBuilder13hasAttributesENS_12AttributeSetEy( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6) #0 align 2 { entry: - br i1 undef, label %cond.false, label %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit + br i1 %replaceUndef0, label %cond.false, label %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit _ZNK4llvm12AttributeSet11getNumSlotsEv.exit: ; preds = %entry - br i1 undef, label %cond.false, label %for.body.lr.ph.for.body.lr.ph.split_crit_edge + br i1 %replaceUndef1, label %cond.false, label %for.body.lr.ph.for.body.lr.ph.split_crit_edge for.body.lr.ph.for.body.lr.ph.split_crit_edge: ; preds = %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit br label %land.lhs.true.i @@ -30,15 +30,15 @@ unreachable _ZNK4llvm12AttributeSet12getSlotIndexEj.exit: ; preds = %land.lhs.true.i - br i1 undef, label %for.end, label %for.inc + br i1 %replaceUndef2, label %for.end, label %for.inc for.inc: ; preds = %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit %inc = add i32 %I.099, 1 - br i1 undef, label %cond.false, label %land.lhs.true.i + br i1 %replaceUndef3, label %cond.false, label %land.lhs.true.i for.end: ; preds = %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit %I.099.lcssa129 = phi i32 [ %I.099, %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit ] - br i1 undef, label %cond.false, label %_ZNK4llvm12AttributeSet3endEj.exit + br i1 %replaceUndef4, label %cond.false, label %_ZNK4llvm12AttributeSet3endEj.exit cond.false: ; preds = %for.end, %for.inc, %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit, %entry unreachable @@ -49,7 +49,7 @@ %NumAttrs.i.i.i = getelementptr inbounds %"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506", ptr %0, i32 0, i32 1 %1 = load i32, ptr %NumAttrs.i.i.i, align 4, !tbaa !8 %add.ptr.i.i.i55 = getelementptr inbounds %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509", ptr undef, i32 %1 - br i1 undef, label %return, label %for.body11 + br i1 %replaceUndef5, label %return, label %for.body11 for.cond9: ; preds = %_ZNK4llvm9Attribute13getKindAsEnumEv.exit %cmp10 = icmp eq ptr %incdec.ptr, %add.ptr.i.i.i55 @@ -70,7 +70,7 @@ _ZNK4llvm9Attribute13getKindAsEnumEv.exit: ; preds = %_ZNK4llvm9Attribute15isEnumAttributeEv.exit, %_ZNK4llvm9Attribute15isEnumAttributeEv.exit %incdec.ptr = getelementptr inbounds %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509", ptr %I5.096, i32 1 - br i1 undef, label %for.cond9, label %return + br i1 %replaceUndef6, label %for.cond9, label %return cond.false21: ; preds = %_ZNK4llvm9Attribute15isEnumAttributeEv.exit, %for.body11 unreachable diff --git a/llvm/test/Analysis/ScalarEvolution/pr22856.ll b/llvm/test/Analysis/ScalarEvolution/pr22856.ll --- a/llvm/test/Analysis/ScalarEvolution/pr22856.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr22856.ll @@ -3,17 +3,17 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64--linux-gnu" -define void @unbounded() { +define void @unbounded( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { block_A: %0 = sext i32 undef to i64 - br i1 undef, label %block_F, label %block_G + br i1 %replaceUndef0, label %block_F, label %block_G block_C: ; preds = %block_F - br i1 undef, label %block_D, label %block_E + br i1 %replaceUndef1, label %block_D, label %block_E block_D: ; preds = %block_D, %block_C - br i1 undef, label %block_E, label %block_D + br i1 %replaceUndef2, label %block_E, label %block_D block_E: ; preds = %block_D, %block_C %iv2 = phi i64 [ %4, %block_D ], [ %4, %block_C ] diff --git a/llvm/test/Analysis/ScalarEvolution/pr25369.ll b/llvm/test/Analysis/ScalarEvolution/pr25369.ll --- a/llvm/test/Analysis/ScalarEvolution/pr25369.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr25369.ll @@ -3,10 +3,10 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @hoge1() { +define void @hoge1( i1 %replaceUndef0) { ; CHECK-LABEL: Classifying expressions for: @hoge1 bb: - br i1 undef, label %bb4, label %bb2 + br i1 %replaceUndef0, label %bb4, label %bb2 bb2: ; preds = %bb2, %bb br i1 false, label %bb4, label %bb2 @@ -40,10 +40,10 @@ ret void } -define void @hoge2() { +define void @hoge2( i1 %replaceUndef0) { ; CHECK-LABEL: Classifying expressions for: @hoge2 bb: - br i1 undef, label %bb4, label %bb2 + br i1 %replaceUndef0, label %bb4, label %bb2 bb2: ; preds = %bb2, %bb br i1 false, label %bb4, label %bb2 diff --git a/llvm/test/Analysis/ScalarEvolution/scev-aa.ll b/llvm/test/Analysis/ScalarEvolution/scev-aa.ll --- a/llvm/test/Analysis/ScalarEvolution/scev-aa.ll +++ b/llvm/test/Analysis/ScalarEvolution/scev-aa.ll @@ -223,7 +223,7 @@ ; different loops where neither dominates the other. This used to crash ; because we expected the arguments to an AddExpr to have a strict ; dominance order. -define void @test_no_dom(ptr %data) { +define void @test_no_dom(ptr %data, i1 %replaceUndef0) { entry: load double, ptr %data br label %for.body @@ -231,7 +231,7 @@ for.body: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.latch ] %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - br i1 undef, label %subloop1, label %subloop2 + br i1 %replaceUndef0, label %subloop1, label %subloop2 subloop1: %iv1 = phi i32 [0, %for.body], [%iv1.next, %subloop1] @@ -266,7 +266,7 @@ ; In this case, checking %addr1 and %add2 involves two addrecs in two ; different loops where neither dominates the other. This is analogous ; to test_no_dom, but involves SCEVUnknown as opposed to SCEVAddRecExpr. -define void @test_no_dom2(ptr %data) { +define void @test_no_dom2(ptr %data, i1 %replaceUndef0) { entry: load double, ptr %data br label %for.body @@ -274,7 +274,7 @@ for.body: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.latch ] %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - br i1 undef, label %subloop1, label %subloop2 + br i1 %replaceUndef0, label %subloop1, label %subloop2 subloop1: %iv1 = phi i32 [0, %for.body], [%iv1.next, %subloop1] diff --git a/llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll b/llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll --- a/llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll +++ b/llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll @@ -6,12 +6,12 @@ target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind uwtable -define void @ehF() #0 { +define void @ehF( i1 %replaceUndef0, i1 %replaceUndef1) #0 { entry: - br i1 undef, label %if.then.i, label %hup.exit + br i1 %replaceUndef0, label %if.then.i, label %hup.exit if.then.i: ; preds = %entry - br i1 undef, label %for.body.lr.ph.i, label %hup.exit + br i1 %replaceUndef1, label %for.body.lr.ph.i, label %hup.exit for.body.lr.ph.i: ; preds = %if.then.i br label %for.body.i diff --git a/llvm/test/Analysis/ScalarEvolution/scev-invalid.ll b/llvm/test/Analysis/ScalarEvolution/scev-invalid.ll --- a/llvm/test/Analysis/ScalarEvolution/scev-invalid.ll +++ b/llvm/test/Analysis/ScalarEvolution/scev-invalid.ll @@ -15,13 +15,13 @@ ; CHECK-NOT: phi ; CHECK-NOT: icmp ; CHECK: ret void -define void @test() { +define void @test( i1 %replaceUndef0) { entry: %xor1 = xor i32 0, 1 br label %b17 b17: - br i1 undef, label %b22, label %b18 + br i1 %replaceUndef0, label %b22, label %b18 b18: %phi1 = phi i32 [ %add1, %b18 ], [ %xor1, %b17 ] diff --git a/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll b/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll --- a/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll +++ b/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt -disable-output "-passes=print" < %s 2>&1 | FileCheck %s -define void @test_lshr() { +define void @test_lshr( i1 %replaceUndef0) { ; CHECK-LABEL: 'test_lshr' ; CHECK-NEXT: Classifying expressions for: @test_lshr ; CHECK-NEXT: %iv.lshr = phi i64 [ 1023, %entry ], [ %iv.lshr.next, %loop ] @@ -19,13 +19,13 @@ loop: %iv.lshr = phi i64 [1023, %entry], [%iv.lshr.next, %loop] %iv.lshr.next = lshr i64 %iv.lshr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } ; Deliberate overflow doesn't change range -define void @test_lshr2() { +define void @test_lshr2( i1 %replaceUndef0) { ; CHECK-LABEL: 'test_lshr2' ; CHECK-NEXT: Classifying expressions for: @test_lshr2 ; CHECK-NEXT: %iv.lshr = phi i64 [ 1023, %entry ], [ %iv.lshr.next, %loop ] @@ -43,13 +43,13 @@ loop: %iv.lshr = phi i64 [1023, %entry], [%iv.lshr.next, %loop] %iv.lshr.next = lshr i64 %iv.lshr, 4 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } -define void @test_ashr_zeros() { +define void @test_ashr_zeros( i1 %replaceUndef0) { ; CHECK-LABEL: 'test_ashr_zeros' ; CHECK-NEXT: Classifying expressions for: @test_ashr_zeros ; CHECK-NEXT: %iv.ashr = phi i64 [ 1023, %entry ], [ %iv.ashr.next, %loop ] @@ -67,12 +67,12 @@ loop: %iv.ashr = phi i64 [1023, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } -define void @test_ashr_ones() { +define void @test_ashr_ones( i1 %replaceUndef0) { ; CHECK-LABEL: 'test_ashr_ones' ; CHECK-NEXT: Classifying expressions for: @test_ashr_ones ; CHECK-NEXT: %iv.ashr = phi i64 [ -1023, %entry ], [ %iv.ashr.next, %loop ] @@ -90,13 +90,13 @@ loop: %iv.ashr = phi i64 [-1023, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } ; Same as previous, but swapped operands to phi -define void @test_ashr_ones2() { +define void @test_ashr_ones2( i1 %replaceUndef0) { ; CHECK-LABEL: 'test_ashr_ones2' ; CHECK-NEXT: Classifying expressions for: @test_ashr_ones2 ; CHECK-NEXT: %iv.ashr = phi i64 [ %iv.ashr.next, %loop ], [ -1023, %entry ] @@ -114,14 +114,14 @@ loop: %iv.ashr = phi i64 [%iv.ashr.next, %loop], [-1023, %entry] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } ; negative case for when start is unknown -define void @test_ashr_unknown(i64 %start) { +define void @test_ashr_unknown(i64 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'test_ashr_unknown' ; CHECK-NEXT: Classifying expressions for: @test_ashr_unknown ; CHECK-NEXT: %iv.ashr = phi i64 [ %start, %entry ], [ %iv.ashr.next, %loop ] @@ -139,14 +139,14 @@ loop: %iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } ; Negative case where we don't have a (shift) recurrence because the operands ; of the ashr are swapped. (This does end up being a divide recurrence.) -define void @test_ashr_wrong_op(i64 %start) { +define void @test_ashr_wrong_op(i64 %start, i1 %replaceUndef0) { ; CHECK-LABEL: 'test_ashr_wrong_op' ; CHECK-NEXT: Classifying expressions for: @test_ashr_wrong_op ; CHECK-NEXT: %iv.ashr = phi i64 [ %start, %entry ], [ %iv.ashr.next, %loop ] @@ -164,13 +164,13 @@ loop: %iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 1, %iv.ashr - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } -define void @test_shl() { +define void @test_shl( i1 %replaceUndef0) { ; CHECK-LABEL: 'test_shl' ; CHECK-NEXT: Classifying expressions for: @test_shl ; CHECK-NEXT: %iv.shl = phi i64 [ 8, %entry ], [ %iv.shl.next, %loop ] @@ -188,7 +188,7 @@ loop: %iv.shl = phi i64 [8, %entry], [%iv.shl.next, %loop] %iv.shl.next = shl i64 %iv.shl, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: ret void } @@ -423,7 +423,7 @@ ; Corner case where phi is not in loop header because binop is in unreachable ; code (which loopinfo ignores, but simple recurrence matching does not). -define void @unreachable_binop() { +define void @unreachable_binop( i1 %replaceUndef0) { ; CHECK-LABEL: 'unreachable_binop' ; CHECK-NEXT: Classifying expressions for: @unreachable_binop ; CHECK-NEXT: %p_58.addr.1 = phi i32 [ undef, %header ], [ %sub2629, %unreachable ] @@ -444,7 +444,7 @@ for.cond2295: %p_58.addr.1 = phi i32 [ undef, %header ], [ %sub2629, %unreachable ] - br i1 undef, label %if.then2321, label %header + br i1 %replaceUndef0, label %if.then2321, label %header if.then2321: ret void diff --git a/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll b/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll --- a/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll +++ b/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll @@ -287,10 +287,10 @@ ; Just check that we don't crash. ; CHECK-LABEL: 'opaque_type_crasher' -define void @opaque_type_crasher(ptr dereferenceable(16) %a) { +define void @opaque_type_crasher(ptr dereferenceable(16) %a, i1 %replaceUndef0) { entry: %ptr8 = getelementptr inbounds i8, ptr %a, i32 8 - br i1 undef, label %if.then, label %if.end + br i1 %replaceUndef0, label %if.then, label %if.end if.then: %res = load i32, ptr %ptr8, align 4 diff --git a/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll b/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll --- a/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll +++ b/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll @@ -1,12 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -passes=instcombine -S | FileCheck %s -define i64 @test_lshr() { +define i64 @test_lshr( i1 %replaceUndef0) { ; CHECK-LABEL: @test_lshr( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret i64 1023 ; @@ -15,18 +14,17 @@ loop: %iv.lshr = phi i64 [1023, %entry], [%iv.lshr.next, %loop] %iv.lshr.next = lshr i64 %iv.lshr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = or i64 %iv.lshr, 1023 ret i64 %res } -define i64 @test_ashr_zeros() { +define i64 @test_ashr_zeros( i1 %replaceUndef0) { ; CHECK-LABEL: @test_ashr_zeros( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret i64 1023 ; @@ -35,18 +33,17 @@ loop: %iv.ashr = phi i64 [1023, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = or i64 %iv.ashr, 1023 ret i64 %res } -define i64 @test_ashr_ones() { +define i64 @test_ashr_ones( i1 %replaceUndef0) { ; CHECK-LABEL: @test_ashr_ones( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 ; @@ -55,19 +52,18 @@ loop: %iv.ashr = phi i64 [-1023, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = or i64 %iv.ashr, 1023 ret i64 %res } ; Same as previous, but swapped operands to phi -define i64 @test_ashr_ones2() { +define i64 @test_ashr_ones2( i1 %replaceUndef0) { ; CHECK-LABEL: @test_ashr_ones2( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 ; @@ -76,7 +72,7 @@ loop: %iv.ashr = phi i64 [%iv.ashr.next, %loop], [-1023, %entry] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = or i64 %iv.ashr, 1023 ret i64 %res @@ -84,14 +80,13 @@ ; negative case for when start is unknown -define i64 @test_ashr_unknown(i64 %start) { +define i64 @test_ashr_unknown(i64 %start, i1 %replaceUndef0) { ; CHECK-LABEL: @test_ashr_unknown( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV_ASHR:%.*]] = phi i64 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_ASHR_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[IV_ASHR_NEXT]] = ashr i64 [[IV_ASHR]], 1 -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: [[RES:%.*]] = or i64 [[IV_ASHR]], 1023 ; CHECK-NEXT: ret i64 [[RES]] @@ -101,7 +96,7 @@ loop: %iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 %iv.ashr, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = or i64 %iv.ashr, 1023 ret i64 %res @@ -109,14 +104,13 @@ ; Negative case where we don't have a (shift) recurrence because the operands ; of the ashr are swapped. (This does end up being a divide recurrence.) -define i64 @test_ashr_wrong_op(i64 %start) { +define i64 @test_ashr_wrong_op(i64 %start, i1 %replaceUndef0) { ; CHECK-LABEL: @test_ashr_wrong_op( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV_ASHR:%.*]] = phi i64 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_ASHR_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[IV_ASHR_NEXT]] = lshr i64 1, [[IV_ASHR]] -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: [[RES:%.*]] = or i64 [[IV_ASHR]], 1023 ; CHECK-NEXT: ret i64 [[RES]] @@ -126,19 +120,18 @@ loop: %iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop] %iv.ashr.next = ashr i64 1, %iv.ashr - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = or i64 %iv.ashr, 1023 ret i64 %res } -define i64 @test_shl() { +define i64 @test_shl( i1 %replaceUndef0) { ; CHECK-LABEL: @test_shl( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret i64 0 ; @@ -147,7 +140,7 @@ loop: %iv.shl = phi i64 [8, %entry], [%iv.shl.next, %loop] %iv.shl.next = shl i64 %iv.shl, 1 - br i1 undef, label %exit, label %loop + br i1 %replaceUndef0, label %exit, label %loop exit: %res = and i64 %iv.shl, 7 ret i64 %res diff --git a/llvm/test/Assembler/atomicrmw.ll b/llvm/test/Assembler/atomicrmw.ll --- a/llvm/test/Assembler/atomicrmw.ll +++ b/llvm/test/Assembler/atomicrmw.ll @@ -4,7 +4,7 @@ ; CHECK: @f ; CHECK: atomicrmw -define void @f() { +define void @f( i1 %replaceUndef0) { entry: br label %def @@ -14,5 +14,5 @@ def: %y = add i32 undef, undef - br i1 undef, label %use, label %use + br i1 %replaceUndef0, label %use, label %use } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll @@ -1089,7 +1089,7 @@ ; Check that with 2 jump tables, the phi node doesn't lose the edge from the ; second one. -define void @jt_2_tables_phi_edge_from_second() { +define void @jt_2_tables_phi_edge_from_second( i1 %replaceUndef0) { ; CHECK-LABEL: name: jt_2_tables_phi_edge_from_second ; CHECK: bb.1.entry: ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF @@ -1309,7 +1309,7 @@ land.rhs.lr.ph: ; preds = %sw.bb12.i, %sw.bb9.i, %sw.bb8.i, %sw.bb7.i, %sw.bb6.i, %sw.bb4.i, %sw.bb1.i, %sw.bb14.i48 %retval.0.i.ph = phi i32 [ 0, %sw.bb14.i48 ], [ 1, %sw.bb1.i ], [ 4, %sw.bb4.i ], [ 6, %sw.bb6.i ], [ 7, %sw.bb7.i ], [ 8, %sw.bb8.i ], [ 9, %sw.bb9.i ], [ 12, %sw.bb12.i ] - br i1 undef, label %while.body, label %while.end + br i1 %replaceUndef0, label %while.body, label %while.end while.body: ; preds = %land.rhs.lr.ph call void @jt_2_tables_phi_edge_from_second() diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll @@ -7,8 +7,8 @@ ; Check that we don't crash when we have a metadata use of %i not being dominated by the def. ; CHECK-LABEL: @foo ; CHECK: DBG_VALUE %1:_(p0), $noreg, !370, !DIExpression(DW_OP_LLVM_fragment, 0, 64) -define hidden void @foo() unnamed_addr #1 !dbg !230 { - br i1 undef, label %bb4, label %bb5 +define hidden void @foo( i1 %replaceUndef0) unnamed_addr #1 !dbg !230 { + br i1 %replaceUndef0, label %bb4, label %bb5 bb4: ; preds = %bb3 %i = extractvalue { ptr, i64 } undef, 0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll @@ -4,7 +4,7 @@ ; Make sure that we don't duplicate successors/predecessors when translating ; indirectbr instructions with duplicate block labels. -define void @foo() { +define void @foo( i1 %replaceUndef0) { ; CHECK-LABEL: name: foo ; CHECK: bb.1 (%ir-block.0): ; CHECK: successors: %bb.2(0x2aaaaaaa), %bb.4(0x2aaaaaaa), %bb.3(0x2aaaaaaa) @@ -16,7 +16,7 @@ ; CHECK: successors: ; CHECK: bb.4 (%ir-block.3): ; CHECK: RET_ReallyLR - indirectbr ptr undef, [label %1, label %3, label %2, label %3, label %3] + indirectbr ptr %replaceUndef0, [label %1, label %3, label %2, label %3, label %3] 1: unreachable 2: diff --git a/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll b/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll --- a/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll @@ -2,7 +2,7 @@ ; PR20188: don't crash when merging sexts. ; CHECK: foo: -define void @foo() unnamed_addr align 2 { +define void @foo( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) unnamed_addr align 2 { entry: br label %invoke.cont145 @@ -12,7 +12,7 @@ if.then274: %0 = load i32, ptr null, align 4 - br i1 undef, label %invoke.cont291, label %if.else313 + br i1 %replaceUndef0, label %invoke.cont291, label %if.else313 invoke.cont291: %idxprom.i.i.i605 = sext i32 %0 to i64 @@ -26,7 +26,7 @@ br i1 %cmp314, label %invoke.cont317, label %invoke.cont353 invoke.cont317: - br i1 undef, label %invoke.cont326, label %invoke.cont334 + br i1 %replaceUndef1, label %invoke.cont326, label %invoke.cont334 invoke.cont326: %idxprom.i.i.i587 = sext i32 %0 to i64 @@ -36,7 +36,7 @@ invoke.cont334: %lo.1 = phi double [ %sub329, %invoke.cont326 ], [ undef, %invoke.cont317 ] - br i1 undef, label %invoke.cont342, label %if.end356 + br i1 %replaceUndef2, label %invoke.cont342, label %if.end356 invoke.cont342: %idxprom.i.i.i578 = sext i32 %0 to i64 diff --git a/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll b/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll --- a/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll @@ -3,15 +3,15 @@ ; Can't copy or spill / restore CPSR. ; rdar://9105206 -define fastcc void @t() ssp align 2 { +define fastcc void @t( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4) ssp align 2 { entry: - br i1 undef, label %bb3.i, label %bb2.i + br i1 %replaceUndef0, label %bb3.i, label %bb2.i bb2.i: ; preds = %entry br label %bb3.i bb3.i: ; preds = %bb2.i, %entry - br i1 undef, label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71, label %bb.i69 + br i1 %replaceUndef1, label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71, label %bb.i69 bb.i69: ; preds = %bb3.i br label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71 @@ -22,10 +22,10 @@ %2 = fcmp ult float %1, 0xBF847AE140000000 %storemerge9 = select i1 %2, float %1, float 0.000000e+00 store float %storemerge9, ptr undef, align 4 - br i1 undef, label %bb42, label %bb47 + br i1 %replaceUndef2, label %bb42, label %bb47 bb42: ; preds = %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71 - br i1 undef, label %bb46, label %bb53 + br i1 %replaceUndef3, label %bb46, label %bb53 bb46: ; preds = %bb42 br label %bb48 @@ -34,7 +34,7 @@ br label %bb48 bb48: ; preds = %bb47, %bb46 - br i1 undef, label %bb1.i14, label %bb.i13 + br i1 %replaceUndef4, label %bb1.i14, label %bb.i13 bb.i13: ; preds = %bb48 br label %bb1.i14 diff --git a/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll @@ -5,10 +5,10 @@ source_filename = "test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll" ; Function Attrs: nounwind ssp -define void @drt_vsprintf() #0 { +define void @drt_vsprintf( i1 %replaceUndef0) #0 { entry: %do_tab_convert = alloca i32, align 4 - br i1 undef, label %if.then24, label %if.else295, !dbg !11 + br i1 %replaceUndef0, label %if.then24, label %if.else295, !dbg !11 if.then24: ; preds = %entry unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll b/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll --- a/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll @@ -3,7 +3,7 @@ ; CPSR is not allocatable so fast allocatable wouldn't mark them killed. ; rdar://9313272 -define hidden void @t() nounwind { +define hidden void @t( i1 %replaceUndef0) nounwind { entry: %cmp = icmp eq ptr null, undef %frombool = zext i1 %cmp to i8 @@ -16,7 +16,7 @@ unreachable if.end: ; preds = %entry - br i1 undef, label %land.lhs.true14, label %if.end33 + br i1 %replaceUndef0, label %land.lhs.true14, label %if.end33 land.lhs.true14: ; preds = %if.end unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll b/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll @@ -5,12 +5,12 @@ ; cycles in DAGs, and eventually crashes. This is the testcase for ; one of those crashes. (rdar://10653656) -define void @test(i1 zeroext %IsArrow) nounwind ssp align 2 { +define void @test(i1 zeroext %IsArrow, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) nounwind ssp align 2 { entry: - br i1 undef, label %return, label %lor.lhs.false + br i1 %replaceUndef0, label %return, label %lor.lhs.false lor.lhs.false: - br i1 undef, label %return, label %if.end + br i1 %replaceUndef1, label %return, label %if.end if.end: %tmp.i = load i64, ptr undef, align 8 @@ -18,7 +18,7 @@ br i1 %IsArrow, label %if.else_crit_edge, label %if.end32 if.else_crit_edge: - br i1 undef, label %if.end32, label %return + br i1 %replaceUndef2, label %if.end32, label %return if.end32: %0 = icmp ult i32 undef, 3 @@ -27,7 +27,7 @@ %.pn = shl i320 %1, %.pn.v %ins346392 = or i320 %.pn, 0 store i320 %ins346392, ptr undef, align 8 - br i1 undef, label %sw.bb.i.i, label %exit + br i1 %replaceUndef3, label %sw.bb.i.i, label %exit sw.bb.i.i: unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll b/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll --- a/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll @@ -15,18 +15,18 @@ declare noalias ptr @xstrdup(ptr) optsize -define ptr @dyld_fix_path(ptr %path) nounwind optsize ssp { +define ptr @dyld_fix_path(ptr %path, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) nounwind optsize ssp { entry: - br i1 undef, label %if.end56, label %for.cond + br i1 %replaceUndef0, label %if.end56, label %for.cond for.cond: ; preds = %entry - br i1 undef, label %for.cond10, label %for.body + br i1 %replaceUndef1, label %for.cond10, label %for.body for.body: ; preds = %for.cond unreachable for.cond10: ; preds = %for.cond - br i1 undef, label %if.end56, label %for.body14 + br i1 %replaceUndef2, label %if.end56, label %for.body14 for.body14: ; preds = %for.cond10 %call22 = tail call i64 @strlen(ptr undef) nounwind optsize @@ -38,7 +38,7 @@ %sext59 = add i64 %add31, 4294967296 %conv33 = ashr exact i64 %sext59, 32 %call34 = tail call noalias ptr @xmalloc(i64 %conv33) nounwind optsize - br i1 undef, label %cond.false45, label %cond.true43 + br i1 %replaceUndef3, label %cond.false45, label %cond.true43 cond.true43: ; preds = %for.body14 unreachable diff --git a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -mtriple=arm64-eabi ; Make sure we are not crashing on this test. -define void @autogen_SD13158() { +define void @autogen_SD13158( i1 %replaceUndef0, i1 %replaceUndef1) { entry: %B26 = frem float 0.000000e+00, undef - br i1 undef, label %CF, label %CF77 + br i1 %replaceUndef0, label %CF, label %CF77 CF: ; preds = %CF, %CF76 store float %B26, ptr undef - br i1 undef, label %CF, label %CF77 + br i1 %replaceUndef1, label %CF, label %CF77 CF77: ; preds = %CF ret void diff --git a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll --- a/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll +++ b/llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll @@ -2,13 +2,13 @@ ; Make sure we are not crashing on this test. -define void @autogen_SD12881() { +define void @autogen_SD12881( i1 %replaceUndef0) { BB: %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer br label %CF CF: ; preds = %CF83, %CF, %BB - br i1 undef, label %CF, label %CF83 + br i1 %replaceUndef0, label %CF, label %CF83 CF83: ; preds = %CF %FC70 = sitofp <4 x i32> %B17 to <4 x double> @@ -16,13 +16,13 @@ } -define void @autogen_SD12881_2() { +define void @autogen_SD12881_2( i1 %replaceUndef0) { BB: %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer br label %CF CF: ; preds = %CF83, %CF, %BB - br i1 undef, label %CF, label %CF83 + br i1 %replaceUndef0, label %CF, label %CF83 CF83: ; preds = %CF %FC70 = uitofp <4 x i32> %B17 to <4 x double> diff --git a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll --- a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll +++ b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll @@ -986,7 +986,7 @@ ; The following test excercises the case where we have a BFI ; instruction with the same input in both operands. We need to ; track the useful bits through both operands. -define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr) { +define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr, i1 %replaceUndef0) { ; LLC-LABEL: sameOperandBFI: ; LLC: // %bb.0: // %entry ; LLC-NEXT: cbnz wzr, .LBB30_2 @@ -1002,7 +1002,6 @@ ; OPT-NEXT: entry: ; OPT-NEXT: [[SHR47:%.*]] = lshr i64 [[SRC:%.*]], 47 ; OPT-NEXT: [[SRC2_TRUNC:%.*]] = trunc i64 [[SRC2:%.*]] to i32 -; OPT-NEXT: br i1 undef, label [[END:%.*]], label [[IF_ELSE:%.*]] ; OPT: if.else: ; OPT-NEXT: [[AND3:%.*]] = and i32 [[SRC2_TRUNC]], 3 ; OPT-NEXT: [[SHL2:%.*]] = shl nuw nsw i64 [[SHR47]], 2 @@ -1019,7 +1018,7 @@ entry: %shr47 = lshr i64 %src, 47 %src2.trunc = trunc i64 %src2 to i32 - br i1 undef, label %end, label %if.else + br i1 %replaceUndef0, label %end, label %if.else if.else: %and3 = and i32 %src2.trunc, 3 diff --git a/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll b/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll --- a/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll +++ b/llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll @@ -36,12 +36,12 @@ ret float %tmp } -define void @t7() nounwind { +define void @t7( i1 %replaceUndef0) nounwind { ; CHECK-LABEL: t7: ; CHECK: b _foo ; CHECK: b _bar - br i1 undef, label %bb, label %bb1.lr.ph + br i1 %replaceUndef0, label %bb, label %bb1.lr.ph bb1.lr.ph: ; preds = %entry tail call void @bar() nounwind diff --git a/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll b/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll --- a/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll +++ b/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll @@ -662,9 +662,9 @@ @.str.89 = external unnamed_addr constant [12 x i8], align 1 @.str.90 = external unnamed_addr constant [5 x i8], align 1 ; CHECK-LABEL: test_r274582 -define void @test_r274582(double %x) { +define void @test_r274582(double %x, i1 %replaceUndef0) { entry: - br i1 undef, label %if.then.i, label %if.end.i + br i1 %replaceUndef0, label %if.then.i, label %if.end.i if.then.i: ret void if.end.i: diff --git a/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll b/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll --- a/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll @@ -8,14 +8,14 @@ ; ; -define void @testcase() { +define void @testcase( i1 %replaceUndef0) { ; CHECK: testcase: ; CHECK-NOT: orr xzr, xzr, #0x2 bb1: %tmp1 = tail call float @ceilf(float 2.000000e+00) %tmp2 = fptoui float %tmp1 to i64 - br i1 undef, label %bb2, label %bb3 + br i1 %replaceUndef0, label %bb2, label %bb3 bb2: tail call void @foo() diff --git a/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll b/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll --- a/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll +++ b/llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll @@ -395,13 +395,13 @@ ; This function from 175.vpr folds an ADDWri into a CSINC. ; Remember to clear the kill flag on the ADDWri. -define i32 @get_ytrack_to_xtracks() nounwind ssp { +define i32 @get_ytrack_to_xtracks( i1 %replaceUndef0, i1 %replaceUndef1) nounwind ssp { entry: br label %for.body for.body: %x0 = load i32, ptr undef, align 4 - br i1 undef, label %if.then.i146, label %is_sbox.exit155 + br i1 %replaceUndef0, label %if.then.i146, label %is_sbox.exit155 if.then.i146: %add8.i143 = add nsw i32 0, %x0 @@ -414,7 +414,7 @@ %idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64 %arrayidx18.i154 = getelementptr inbounds i32, ptr null, i64 %idxprom15.i152 %x1 = load i32, ptr %arrayidx18.i154, align 4 - br i1 undef, label %for.body51, label %for.body + br i1 %replaceUndef1, label %for.body51, label %for.body for.body51: ; preds = %is_sbox.exit155 call fastcc void @get_switch_type(i32 %x1, i32 undef, i16 signext undef, i16 signext undef, ptr undef) diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll @@ -118,14 +118,14 @@ declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) -define void @logicalReg() { +define void @logicalReg( i1 %replaceUndef0) { ; Make sure we generate a logical reg = reg, reg instruction without any ; machine verifier errors. ; CHECK-LABEL: logicalReg: ; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}} ; CHECK: ret entry: - br i1 undef, label %cond.end, label %cond.false + br i1 %replaceUndef0, label %cond.end, label %cond.false cond.false: %cond = select i1 undef, i1 true, i1 false diff --git a/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll b/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll --- a/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll +++ b/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll @@ -755,7 +755,7 @@ ; should return gracefully and continue compilation. ; The only condition for this test is the compilation finishes correctly. ; -define void @infiniteloop() { +define void @infiniteloop( i1 %replaceUndef0) { ; ENABLE-LABEL: infiniteloop: ; ENABLE: ; %bb.0: ; %entry ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill @@ -812,7 +812,7 @@ ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ret entry: - br i1 undef, label %if.then, label %if.end + br i1 %replaceUndef0, label %if.then, label %if.end if.then: %ptr = alloca i32, i32 4 @@ -830,7 +830,7 @@ } ; Another infinite loop test this time with a body bigger than just one block. -define void @infiniteloop2() { +define void @infiniteloop2( i1 %replaceUndef0, i1 %replaceUndef1) { ; ENABLE-LABEL: infiniteloop2: ; ENABLE: ; %bb.0: ; %entry ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill @@ -899,7 +899,7 @@ ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ret entry: - br i1 undef, label %if.then, label %if.end + br i1 %replaceUndef0, label %if.then, label %if.end if.then: %ptr = alloca i32, i32 4 @@ -910,7 +910,7 @@ %call = tail call i32 asm "mov $0, #0", "=r,~{x19}"() %add = add nsw i32 %call, %sum.03 store i32 %add, ptr %ptr - br i1 undef, label %body1, label %body2 + br i1 %replaceUndef1, label %body1, label %body2 body1: tail call void asm sideeffect "nop", "~{x19}"() @@ -925,7 +925,7 @@ } ; Another infinite loop test this time with two nested infinite loop. -define void @infiniteloop3() { +define void @infiniteloop3( i1 %replaceUndef0, i1 %replaceUndef1) { ; ENABLE-LABEL: infiniteloop3: ; ENABLE: ; %bb.0: ; %entry ; ENABLE-NEXT: cbnz wzr, LBB12_5 @@ -974,10 +974,10 @@ ; DISABLE-NEXT: LBB12_5: ; %end ; DISABLE-NEXT: ret entry: - br i1 undef, label %loop2a, label %body + br i1 %replaceUndef0, label %loop2a, label %body body: ; preds = %entry - br i1 undef, label %loop2a, label %end + br i1 %replaceUndef1, label %loop2a, label %end loop1: ; preds = %loop2a, %loop2b %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ] diff --git a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll --- a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll +++ b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll @@ -14,12 +14,12 @@ @q = external dso_local unnamed_addr global ptr, align 8 ; Function Attrs: nounwind -define void @test() local_unnamed_addr #0 { +define void @test( i1 %replaceUndef0) local_unnamed_addr #0 { entry: br label %for.body453.i for.body453.i: ; preds = %for.body453.i, %entry - br i1 undef, label %for.body453.i, label %for.end705.i + br i1 %replaceUndef0, label %for.body453.i, label %for.end705.i for.end705.i: ; preds = %for.body453.i %0 = load ptr, ptr @q, align 8 diff --git a/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll b/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll --- a/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll +++ b/llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll @@ -7,16 +7,16 @@ ; that case, the machine verifier, which relies on analyzing branches for this ; kind of verification, is unable to check anything, so accepts the CFG. -define void @test_branch_to_landingpad() personality ptr @__objc_personality_v0 { +define void @test_branch_to_landingpad( i1 %replaceUndef0, i1 %replaceUndef1) personality ptr @__objc_personality_v0 { entry: - br i1 undef, label %if.end50.thread, label %if.then6 + br i1 %replaceUndef0, label %if.end50.thread, label %if.then6 lpad: %0 = landingpad { ptr, i32 } catch ptr @"OBJC_EHTYPE_$_NSString" catch ptr @OBJC_EHTYPE_id catch ptr null - br i1 undef, label %invoke.cont33, label %catch.fallthrough + br i1 %replaceUndef1, label %invoke.cont33, label %catch.fallthrough catch.fallthrough: %matches31 = icmp eq i32 undef, 0 diff --git a/llvm/test/CodeGen/AArch64/br-undef-cond.ll b/llvm/test/CodeGen/AArch64/br-undef-cond.ll --- a/llvm/test/CodeGen/AArch64/br-undef-cond.ll +++ b/llvm/test/CodeGen/AArch64/br-undef-cond.ll @@ -7,13 +7,13 @@ declare void @bar(ptr) -define void @foo(ptr %m, i32 %off0) { +define void @foo(ptr %m, i32 %off0, i1 %replaceUndef0, i1 %replaceUndef1) { .thread1653: - br i1 undef, label %0, label %.thread1880 + br i1 %replaceUndef0, label %0, label %.thread1880 %1 = icmp eq i32 undef, 0 %.not = xor i1 %1, true - %brmerge = or i1 %.not, undef + %brmerge = or i1 %.not, %replaceUndef1 br i1 %brmerge, label %.thread1880, label %.thread1705 .thread1705: diff --git a/llvm/test/CodeGen/AArch64/gep-nullptr.ll b/llvm/test/CodeGen/AArch64/gep-nullptr.ll --- a/llvm/test/CodeGen/AArch64/gep-nullptr.ll +++ b/llvm/test/CodeGen/AArch64/gep-nullptr.ll @@ -6,9 +6,9 @@ %unionMV = type { i32 } ; Function Attrs: nounwind -define void @test(ptr %mi_block) { +define void @test(ptr %mi_block, i1 %replaceUndef0) { entry: - br i1 undef, label %for.body13.us, label %if.else + br i1 %replaceUndef0, label %for.body13.us, label %if.else ; Just make sure we don't get a compiler ICE due to dereferncing a nullptr. ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll b/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll --- a/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll @@ -1,12 +1,12 @@ ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; CHECK-LABEL: foo: ; CHECK: TEST .Ltmp0 -define void @foo() { +define void @foo( i1 %replaceUndef0) { entry: br label %bar bar: call void asm sideeffect "#TEST $0", "i,~{dirflag},~{fpsr},~{flags}"(ptr blockaddress(@foo, %bar)) ret void indirectgoto: - indirectbr ptr undef, [label %bar] + indirectbr ptr %replaceUndef0, [label %bar] } diff --git a/llvm/test/CodeGen/AArch64/madd-combiner.ll b/llvm/test/CodeGen/AArch64/madd-combiner.ll --- a/llvm/test/CodeGen/AArch64/madd-combiner.ll +++ b/llvm/test/CodeGen/AArch64/madd-combiner.ll @@ -26,7 +26,7 @@ } ; bugpoint reduced test case. This only tests that we pass the MI verifier. -define void @mul_add_imm2() { +define void @mul_add_imm2( i1 %replaceUndef0) { ; CHECK-ISEL-LABEL: mul_add_imm2: ; CHECK-ISEL: ; %bb.0: ; %entry ; CHECK-ISEL-NEXT: mov w8, #1 @@ -53,7 +53,7 @@ entry: br label %for.body for.body: - br i1 undef, label %for.body, label %for.body8 + br i1 %replaceUndef0, label %for.body, label %for.body8 for.body8: %0 = mul i64 undef, -3 %mul1971 = add i64 %0, -3 diff --git a/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll b/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll --- a/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll +++ b/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll @@ -10,7 +10,7 @@ ; formed in SelectionDAG, optimizeCondBranch() only triggers if the and ; instruction is in a different block than the conditional jump. -define void @func() uwtable { +define void @func( i1 %replaceUndef0) uwtable { ; CHECK-LABEL: func: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #1 @@ -43,7 +43,7 @@ br i1 %c0, label %b1, label %b6 b1: - br i1 undef, label %b3, label %b2 + br i1 %replaceUndef0, label %b3, label %b2 b2: %v0 = tail call i32 @extfunc() diff --git a/llvm/test/CodeGen/AArch64/shrink-wrap.ll b/llvm/test/CodeGen/AArch64/shrink-wrap.ll --- a/llvm/test/CodeGen/AArch64/shrink-wrap.ll +++ b/llvm/test/CodeGen/AArch64/shrink-wrap.ll @@ -31,7 +31,7 @@ declare fastcc i32 @bar() -define internal fastcc i32 @func(i32 %alpha, i32 %beta) { +define internal fastcc i32 @func(i32 %alpha, i32 %beta, i1 %replaceUndef0) { entry: %v1 = alloca [2 x [11 x i32]], align 4 %v2 = alloca [11 x i32], align 16 @@ -69,7 +69,7 @@ %a.0983 = phi i32 [ 1, %if.end.9 ], [ %a.1, %for.inc ] %arrayidx = getelementptr inbounds [62 x i32], ptr @g17, i64 0, i64 undef %tmp5 = load i32, ptr %arrayidx, align 4 - br i1 undef, label %for.inc, label %if.else.51 + br i1 %replaceUndef0, label %for.inc, label %if.else.51 if.else.51: %idxprom53 = sext i32 %tmp5 to i64 diff --git a/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll b/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll --- a/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll +++ b/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll @@ -6,10 +6,10 @@ ; the attributes of the caller and the callee match. declare zeroext i1 @zcallee() -define void @zcaller() { +define void @zcaller( i1 %replaceUndef0) { ; CHECK-LABEL: name: zcaller entry: - br i1 undef, label %calllabel, label %retlabel + br i1 %replaceUndef0, label %calllabel, label %retlabel calllabel: ; CHECK: bb.1.calllabel: ; CHECK-NOT: BL @zcallee @@ -21,10 +21,10 @@ } declare signext i1 @scallee() -define void @scaller() { +define void @scaller( i1 %replaceUndef0) { ; CHECK-LABEL: name: scaller entry: - br i1 undef, label %calllabel, label %retlabel + br i1 %replaceUndef0, label %calllabel, label %retlabel calllabel: ; CHECK: bb.1.calllabel: ; CHECK-NOT: BL @scallee diff --git a/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll b/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll --- a/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=arm64-apple-ios %s -o - | FileCheck %s -define swifttailcc void @foo(ptr %call) ssp { +define swifttailcc void @foo(ptr %call, i1 %replaceUndef0) ssp { ; CHECK-LABEL: foo: %var = alloca [28 x i8], align 16 - br i1 undef, label %if.then, label %if.end + br i1 %replaceUndef0, label %if.then, label %if.end if.then: ret void diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll @@ -71,8 +71,7 @@ ret void } -define void @br_undef() { -; WAVE64-LABEL: br_undef: +define void @br_undef( i1 %replaceUndef0) { ; WAVE64: ; %bb.0: ; %.exit ; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; WAVE64-NEXT: .LBB2_1: ; %bb0 @@ -84,7 +83,6 @@ ; WAVE64-NEXT: ; %bb.2: ; %.exit5 ; WAVE64-NEXT: s_setpc_b64 s[30:31] ; -; WAVE32-LABEL: br_undef: ; WAVE32: ; %bb.0: ; %.exit ; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 @@ -100,7 +98,7 @@ br label %bb0 bb0: - br i1 undef, label %.exit5, label %bb0 + br i1 %replaceUndef0, label %.exit5, label %bb0 .exit5: ret void diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll --- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll @@ -511,7 +511,7 @@ ret void } -define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg2, i64 %arg3, <2 x half> %arg4, <2 x half> %arg5) #3 { +define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg2, i64 %arg3, <2 x half> %arg4, <2 x half> %arg5, i1 %replaceUndef0) #3 { ; GFX908-LABEL: introduced_copy_to_sgpr: ; GFX908: ; %bb.0: ; %bb ; GFX908-NEXT: global_load_ushort v16, v[0:1], off glc @@ -840,7 +840,7 @@ bb9: ; preds = %bb12, %bb %i10 = phi i64 [ %arg3, %bb ], [ %i13, %bb12 ] - br i1 undef, label %bb14, label %bb12 + br i1 %replaceUndef0, label %bb14, label %bb12 bb12: ; preds = %bb58, %bb9 %i13 = add nuw nsw i64 %i10, %i8 diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll --- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll @@ -6,11 +6,11 @@ ; Test for compilation only. This generated an invalid machine instruction ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both ; of which were in SGPRs. -define amdgpu_vs float @main(i32 %v) { +define amdgpu_vs float @main(i32 %v, i1 %replaceUndef0) { main_body: %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 960, i32 0) %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 976, i32 0) - br i1 undef, label %ENDIF56, label %IF57 + br i1 %replaceUndef0, label %ENDIF56, label %IF57 IF57: ; preds = %ENDIF %v.1 = mul i32 %v, 2 diff --git a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll --- a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll @@ -225,7 +225,7 @@ br i1 false, label %for.body, label %for.exit } -define amdgpu_kernel void @loop_const_undef(ptr addrspace(3) %ptr, i32 %n) nounwind { +define amdgpu_kernel void @loop_const_undef(ptr addrspace(3) %ptr, i32 %n, i1 %replaceUndef0) nounwind { ; GCN-LABEL: loop_const_undef: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 @@ -286,7 +286,7 @@ %add = fadd float %vecload, 1.0 store float %add, ptr addrspace(3) %arrayidx, align 8 %inc = add i32 %indvar, 1 - br i1 undef, label %for.body, label %for.exit + br i1 %replaceUndef0, label %for.body, label %for.exit } define amdgpu_kernel void @loop_arg_0(ptr addrspace(3) %ptr, i32 %n) nounwind { diff --git a/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll b/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll --- a/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll @@ -35,10 +35,10 @@ ; GCN: buffer_store_dword ; GCN: s_endpgm -define amdgpu_kernel void @sink_ubfe_i32(ptr addrspace(1) %out, i32 %arg1) #0 { +define amdgpu_kernel void @sink_ubfe_i32(ptr addrspace(1) %out, i32 %arg1, i1 %replaceUndef0) #0 { entry: %shr = lshr i32 %arg1, 8 - br i1 undef, label %bb0, label %bb1 + br i1 %replaceUndef0, label %bb0, label %bb1 bb0: %val0 = and i32 %shr, 255 @@ -75,10 +75,10 @@ ; OPT: ret ; GCN-LABEL: {{^}}sink_sbfe_i32: -define amdgpu_kernel void @sink_sbfe_i32(ptr addrspace(1) %out, i32 %arg1) #0 { +define amdgpu_kernel void @sink_sbfe_i32(ptr addrspace(1) %out, i32 %arg1, i1 %replaceUndef0) #0 { entry: %shr = ashr i32 %arg1, 8 - br i1 undef, label %bb0, label %bb1 + br i1 %replaceUndef0, label %bb0, label %bb1 bb0: %val0 = and i32 %shr, 255 @@ -132,10 +132,10 @@ ; GCN: buffer_store_short ; GCN: s_endpgm -define amdgpu_kernel void @sink_ubfe_i16(ptr addrspace(1) %out, i16 %arg1) #0 { +define amdgpu_kernel void @sink_ubfe_i16(ptr addrspace(1) %out, i16 %arg1, i1 %replaceUndef0) #0 { entry: %shr = lshr i16 %arg1, 4 - br i1 undef, label %bb0, label %bb1 + br i1 %replaceUndef0, label %bb0, label %bb1 bb0: %val0 = and i16 %shr, 255 @@ -183,10 +183,10 @@ ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xff, v[[LO]] ; GCN: buffer_store_dwordx2 -define amdgpu_kernel void @sink_ubfe_i64_span_midpoint(ptr addrspace(1) %out, i64 %arg1) #0 { +define amdgpu_kernel void @sink_ubfe_i64_span_midpoint(ptr addrspace(1) %out, i64 %arg1, i1 %replaceUndef0) #0 { entry: %shr = lshr i64 %arg1, 30 - br i1 undef, label %bb0, label %bb1 + br i1 %replaceUndef0, label %bb0, label %bb1 bb0: %val0 = and i64 %shr, 255 @@ -231,10 +231,10 @@ ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f ; GCN: buffer_store_dwordx2 -define amdgpu_kernel void @sink_ubfe_i64_low32(ptr addrspace(1) %out, i64 %arg1) #0 { +define amdgpu_kernel void @sink_ubfe_i64_low32(ptr addrspace(1) %out, i64 %arg1, i1 %replaceUndef0) #0 { entry: %shr = lshr i64 %arg1, 15 - br i1 undef, label %bb0, label %bb1 + br i1 %replaceUndef0, label %bb0, label %bb1 bb0: %val0 = and i64 %shr, 255 @@ -277,10 +277,10 @@ ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003 ; GCN: buffer_store_dwordx2 -define amdgpu_kernel void @sink_ubfe_i64_high32(ptr addrspace(1) %out, i64 %arg1) #0 { +define amdgpu_kernel void @sink_ubfe_i64_high32(ptr addrspace(1) %out, i64 %arg1, i1 %replaceUndef0) #0 { entry: %shr = lshr i64 %arg1, 35 - br i1 undef, label %bb0, label %bb1 + br i1 %replaceUndef0, label %bb0, label %bb1 bb0: %val0 = and i64 %shr, 255 diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll --- a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll +++ b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll @@ -2,13 +2,13 @@ ; This testcase produces a situation with unused value numbers in subregister ; liveranges that get distributed by ConnectedVNInfoEqClasses. -define amdgpu_kernel void @hoge() { +define amdgpu_kernel void @hoge( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4) { bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() - br i1 undef, label %bb2, label %bb23 + br i1 %replaceUndef0, label %bb2, label %bb23 bb2: - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: %tmp7 = or i64 undef, undef @@ -20,7 +20,7 @@ br i1 %tmp10, label %bb11, label %bb23 bb11: - br i1 undef, label %bb20, label %bb17 + br i1 %replaceUndef2, label %bb20, label %bb17 bb17: br label %bb20 @@ -36,10 +36,10 @@ bb25: %tmp26 = phi i32 [ %tmp24, %bb23 ], [ undef, %bb25 ] - br i1 undef, label %bb25, label %bb30 + br i1 %replaceUndef3, label %bb25, label %bb30 bb30: - br i1 undef, label %bb32, label %bb34 + br i1 %replaceUndef4, label %bb32, label %bb34 bb32: %tmp33 = zext i32 %tmp26 to i64 diff --git a/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll b/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll --- a/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll @@ -4,7 +4,7 @@ ; Test that unused lanes in the s_xor result are masked out with v_cndmask. -define i32 @combine_add_zext_xor() { +define i32 @combine_add_zext_xor( i1 %replaceUndef0) { ; GFX1010-LABEL: combine_add_zext_xor: ; GFX1010: ; %bb.0: ; %.entry ; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -65,7 +65,7 @@ .a: ; preds = %bb9, %.entry %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ] - br i1 undef, label %bb9, label %bb + br i1 %replaceUndef0, label %bb9, label %bb bb: ; preds = %.a %.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1) @@ -86,7 +86,7 @@ ; Test that unused lanes in the s_xor result are masked out with v_cndmask. -define i32 @combine_sub_zext_xor() { +define i32 @combine_sub_zext_xor( i1 %replaceUndef0) { ; GFX1010-LABEL: combine_sub_zext_xor: ; GFX1010: ; %bb.0: ; %.entry ; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -147,7 +147,7 @@ .a: ; preds = %bb9, %.entry %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ] - br i1 undef, label %bb9, label %bb + br i1 %replaceUndef0, label %bb9, label %bb bb: ; preds = %.a %.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1) @@ -168,7 +168,7 @@ ; Test that unused lanes in the s_or result are masked out with v_cndmask. -define i32 @combine_add_zext_or() { +define i32 @combine_add_zext_or( i1 %replaceUndef0) { ; GFX1010-LABEL: combine_add_zext_or: ; GFX1010: ; %bb.0: ; %.entry ; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -227,7 +227,7 @@ .a: ; preds = %bb9, %.entry %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ] - br i1 undef, label %bb9, label %bb + br i1 %replaceUndef0, label %bb9, label %bb bb: ; preds = %.a %.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1) @@ -249,7 +249,7 @@ ; Test that unused lanes in the s_or result are masked out with v_cndmask. -define i32 @combine_sub_zext_or() { +define i32 @combine_sub_zext_or( i1 %replaceUndef0) { ; GFX1010-LABEL: combine_sub_zext_or: ; GFX1010: ; %bb.0: ; %.entry ; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -308,7 +308,7 @@ .a: ; preds = %bb9, %.entry %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ] - br i1 undef, label %bb9, label %bb + br i1 %replaceUndef0, label %bb9, label %bb bb: ; preds = %.a %.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1) @@ -330,7 +330,7 @@ ; Test that unused lanes in the s_and result are masked out with v_cndmask. -define i32 @combine_add_zext_and() { +define i32 @combine_add_zext_and( i1 %replaceUndef0) { ; GFX1010-LABEL: combine_add_zext_and: ; GFX1010: ; %bb.0: ; %.entry ; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -389,7 +389,7 @@ .a: ; preds = %bb9, %.entry %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ] - br i1 undef, label %bb9, label %bb + br i1 %replaceUndef0, label %bb9, label %bb bb: ; preds = %.a %.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1) @@ -411,7 +411,7 @@ ; Test that unused lanes in the s_and result are masked out with v_cndmask. -define i32 @combine_sub_zext_and() { +define i32 @combine_sub_zext_and( i1 %replaceUndef0) { ; GFX1010-LABEL: combine_sub_zext_and: ; GFX1010: ; %bb.0: ; %.entry ; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -470,7 +470,7 @@ .a: ; preds = %bb9, %.entry %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ] - br i1 undef, label %bb9, label %bb + br i1 %replaceUndef0, label %bb9, label %bb bb: ; preds = %.a %.i3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 %.2, i32 64, i32 1) diff --git a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll --- a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll @@ -10,9 +10,9 @@ ; ; GCN: s_endpgm -define amdgpu_ps void @main(i32 %in1) local_unnamed_addr { +define amdgpu_ps void @main(i32 %in1, i1 %replaceUndef0) local_unnamed_addr { .entry: - br i1 undef, label %bb12, label %bb + br i1 %replaceUndef0, label %bb12, label %bb bb: %__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> undef, i32 %in1, i32 3 diff --git a/llvm/test/CodeGen/AMDGPU/early-if-convert.ll b/llvm/test/CodeGen/AMDGPU/early-if-convert.ll --- a/llvm/test/CodeGen/AMDGPU/early-if-convert.ll +++ b/llvm/test/CodeGen/AMDGPU/early-if-convert.ll @@ -384,9 +384,9 @@ ; GCN: {{^}}; %bb.0: ; GCN-NEXT: s_load_dwordx2 ; GCN-NEXT: s_cselect_b32 s{{[0-9]+}}, 0, 1{{$}} -define amdgpu_kernel void @ifcvt_undef_scc(i32 %cond, ptr addrspace(1) %out) { +define amdgpu_kernel void @ifcvt_undef_scc(i32 %cond, ptr addrspace(1) %out, i1 %replaceUndef0) { entry: - br i1 undef, label %else, label %if + br i1 %replaceUndef0, label %else, label %if if: br label %done diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll --- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll @@ -2,7 +2,7 @@ ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { +define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { ; SI-LABEL: vec_8xi16_extract_4xi16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -114,7 +114,7 @@ ; GFX9-NEXT: v_perm_b32 v0, v0, v2, s4 ; GFX9-NEXT: v_perm_b32 v1, v3, v1, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] - br i1 undef, label %T, label %F + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x i16>, ptr addrspace(1) %p0 @@ -132,7 +132,7 @@ ret <4 x i16> %r2 } -define <4 x i16> @vec_8xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { +define <4 x i16> @vec_8xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { ; SI-LABEL: vec_8xi16_extract_4xi16_2: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -246,7 +246,7 @@ ; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4 ; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] - br i1 undef, label %T, label %F + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x i16>, ptr addrspace(1) %p0 @@ -264,7 +264,7 @@ ret <4 x i16> %r2 } -define <4 x half> @vec_8xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { +define <4 x half> @vec_8xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { ; SI-LABEL: vec_8xf16_extract_4xf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -383,7 +383,7 @@ ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v1, v5, v6 ; GFX9-NEXT: s_setpc_b64 s[30:31] - br i1 undef, label %T, label %F + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x half>, ptr addrspace(1) %p0 @@ -401,7 +401,7 @@ ret <4 x half> %r2 } -define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { +define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { ; ; SI-LABEL: vec_16xi16_extract_4xi16: ; SI: ; %bb.0: @@ -552,7 +552,7 @@ ; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4 ; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] - br i1 undef, label %T, label %F + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <16 x i16>, ptr addrspace(1) %p0 @@ -570,7 +570,7 @@ ret <4 x i16> %r2 } -define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { +define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { ; ; SI-LABEL: vec_16xi16_extract_4xi16_2: ; SI: ; %bb.0: @@ -723,7 +723,7 @@ ; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4 ; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] - br i1 undef, label %T, label %F + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <16 x i16>, ptr addrspace(1) %p0 @@ -741,7 +741,7 @@ ret <4 x i16> %r2 } -define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { +define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { ; ; SI-LABEL: vec_16xf16_extract_4xf16: ; SI: ; %bb.0: @@ -899,7 +899,7 @@ ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v1, v5, v6 ; GFX9-NEXT: s_setpc_b64 s[30:31] - br i1 undef, label %T, label %F + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <16 x half>, ptr addrspace(1) %p0 diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll --- a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll @@ -20,8 +20,8 @@ ; GCN: v_bfe_i32 ; GCN: v_bfe_i32 -define <2 x i16> @extract_2xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <2 x i16> @extract_2xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x i16>, ptr addrspace(1) %p0 @@ -41,8 +41,8 @@ ; GCN-LABEL: extract_2xi64 ; GCN-COUNT-2: v_cndmask_b32 -define <2 x i64> @extract_2xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <2 x i64> @extract_2xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x i64>, ptr addrspace(1) %p0 @@ -62,8 +62,8 @@ ; GCN-LABEL: extract_4xi64 ; GCN-COUNT-4: v_cndmask_b32 -define <4 x i64> @extract_4xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <4 x i64> @extract_4xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x i64>, ptr addrspace(1) %p0 @@ -83,8 +83,8 @@ ; GCN-LABEL: extract_8xi64 ; GCN-COUNT-8: v_cndmask_b32 -define <8 x i64> @extract_8xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <8 x i64> @extract_8xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <16 x i64>, ptr addrspace(1) %p0 @@ -104,8 +104,8 @@ ; GCN-LABEL: extract_2xf64 ; GCN-COUNT-2: v_cndmask_b32 -define <2 x double> @extract_2xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <2 x double> @extract_2xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x double>, ptr addrspace(1) %p0 @@ -125,8 +125,8 @@ ; GCN-LABEL: extract_4xf64 ; GCN-COUNT-4: v_cndmask_b32 -define <4 x double> @extract_4xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <4 x double> @extract_4xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <8 x double>, ptr addrspace(1) %p0 @@ -146,8 +146,8 @@ ; GCN-LABEL: extract_8xf64 ; GCN-COUNT-8: v_cndmask_b32 -define <8 x double> @extract_8xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1) { - br i1 undef, label %T, label %F +define <8 x double> @extract_8xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %replaceUndef0) { + br i1 %replaceUndef0, label %T, label %F T: %t = load volatile <16 x double>, ptr addrspace(1) %p0 diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll --- a/llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll +++ b/llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll @@ -5,9 +5,9 @@ ; SI-LABEL: {{^}}br_implicit_def: ; SI: %bb.0: ; SI-NEXT: s_cbranch_scc1 -define amdgpu_kernel void @br_implicit_def(ptr addrspace(1) %out, i32 %arg) #0 { +define amdgpu_kernel void @br_implicit_def(ptr addrspace(1) %out, i32 %arg, i1 %replaceUndef0) #0 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %replaceUndef0, label %bb1, label %bb2 bb1: store volatile i32 123, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll --- a/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll +++ b/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll @@ -42,9 +42,9 @@ ; SI-LABEL: {{^}}vcopy_i1_undef ; SI: v_cndmask_b32_e64 ; SI: v_cndmask_b32_e64 -define <2 x float> @vcopy_i1_undef(ptr addrspace(1) %p) { +define <2 x float> @vcopy_i1_undef(ptr addrspace(1) %p, i1 %replaceUndef0) { entry: - br i1 undef, label %exit, label %false + br i1 %replaceUndef0, label %exit, label %false false: %x = load <2 x float>, ptr addrspace(1) %p diff --git a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll --- a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll +++ b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll @@ -7,9 +7,9 @@ ; CHECK-NOT: COPY [[IMPDEF0]] ; CHECK-NOT: COPY [[IMPDEF1]] ; CHECK: .false: -define <2 x float> @vcopy_i1_undef(ptr addrspace(1) %p) { +define <2 x float> @vcopy_i1_undef(ptr addrspace(1) %p, i1 %replaceUndef0) { entry: - br i1 undef, label %exit, label %false + br i1 %replaceUndef0, label %exit, label %false false: %x = load <2 x float>, ptr addrspace(1) %p diff --git a/llvm/test/CodeGen/AMDGPU/infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/infinite-loop.ll --- a/llvm/test/CodeGen/AMDGPU/infinite-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/infinite-loop.ll @@ -81,7 +81,7 @@ ret void } -define amdgpu_kernel void @infinite_loops(ptr addrspace(1) %out) { +define amdgpu_kernel void @infinite_loops(ptr addrspace(1) %out, i1 %replaceUndef0) { ; SI-LABEL: infinite_loops: ; SI: ; %bb.0: ; %entry ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 @@ -122,7 +122,6 @@ ; SI-NEXT: s_endpgm ; IR-LABEL: @infinite_loops( ; IR-NEXT: entry: -; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]] ; IR: loop1: ; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4 ; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]] @@ -133,7 +132,7 @@ ; IR-NEXT: ret void ; entry: - br i1 undef, label %loop1, label %loop2 + br i1 %replaceUndef0, label %loop1, label %loop2 loop1: store volatile i32 999, ptr addrspace(1) %out, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll --- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll @@ -299,9 +299,9 @@ ; Check aggregate types are handled properly. ; CHECK-LABEL: mad_u64 ; CHECK: v_mad_u64_u32 -define void @mad_u64(i32 %x) { +define void @mad_u64(i32 %x, i1 %replaceUndef0) { entry: - br i1 undef, label %exit, label %false + br i1 %replaceUndef0, label %exit, label %false false: %s0 = tail call { i64, i64 } asm sideeffect "v_mad_u64_u32 $0, $1, $2, $3, $4", "=v,=s,v,v,v"(i32 -766435501, i32 %x, i64 0) diff --git a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll --- a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll @@ -26,7 +26,7 @@ declare void @llvm.lifetime.end.p5(i64 immarg, ptr addrspace(5) nocapture) #1 ; Function Attrs: norecurse -define internal fastcc void @svm_node_closure_bsdf(ptr addrspace(1) %sd, ptr %stack, <4 x i32> %node, ptr %offset, i32 %0, i8 %trunc, float %1, float %2, float %mul80, i1 %cmp412.old, <4 x i32> %3, float %4, i32 %5, i1 %cmp440, i1 %cmp442, i1 %or.cond1306, float %.op, ptr addrspace(1) %arrayidx.i.i2202, ptr addrspace(1) %retval.0.i.i22089, ptr addrspace(1) %retval.1.i221310, i1 %cmp575, ptr addrspace(1) %num_closure_left.i2215, i32 %6, i1 %cmp.i2216, i32 %7, i64 %idx.ext.i2223, i32 %sub5.i2221) #2 { +define internal fastcc void @svm_node_closure_bsdf(ptr addrspace(1) %sd, ptr %stack, <4 x i32> %node, ptr %offset, i32 %0, i8 %trunc, float %1, float %2, float %mul80, i1 %cmp412.old, <4 x i32> %3, float %4, i32 %5, i1 %cmp440, i1 %cmp442, i1 %or.cond1306, float %.op, ptr addrspace(1) %arrayidx.i.i2202, ptr addrspace(1) %retval.0.i.i22089, ptr addrspace(1) %retval.1.i221310, i1 %cmp575, ptr addrspace(1) %num_closure_left.i2215, i32 %6, i1 %cmp.i2216, i32 %7, i64 %idx.ext.i2223, i32 %sub5.i2221, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) #2 { ; GCN-LABEL: {{^}}svm_node_closure_bsdf: ; GCN-DAG: v_writelane_b32 [[CSR_VGPR:v[0-9]+]], s30, ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31, @@ -39,7 +39,7 @@ entry: %8 = extractelement <4 x i32> %node, i64 0 %cmp.i.not = icmp eq i32 undef, 0 - br i1 undef, label %common.ret.critedge, label %cond.true + br i1 %replaceUndef0, label %common.ret.critedge, label %cond.true cond.true: ; preds = %entry %9 = load float, ptr null, align 4 @@ -122,10 +122,10 @@ br label %if.end627.sink.split if.else568: ; preds = %if.then413 - br i1 undef, label %bsdf_alloc.exit2214, label %if.then.i2198 + br i1 %replaceUndef1, label %bsdf_alloc.exit2214, label %if.then.i2198 if.then.i2198: ; preds = %if.else568 - br i1 undef, label %closure_alloc.exit.i2210, label %if.end.i.i2207 + br i1 %replaceUndef2, label %closure_alloc.exit.i2210, label %if.end.i.i2207 if.end.i.i2207: ; preds = %if.then.i2198 %arrayidx.i.i22028 = getelementptr inbounds %struct.ShaderData, ptr addrspace(1) %sd, i64 0, i32 30, i64 undef diff --git a/llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll b/llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll --- a/llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll @@ -4,10 +4,10 @@ @gv = external unnamed_addr addrspace(4) constant [239 x i32], align 4 -define amdgpu_kernel void @opencv_cvtfloat_crash(ptr addrspace(1) %out, i32 %x) nounwind { +define amdgpu_kernel void @opencv_cvtfloat_crash(ptr addrspace(1) %out, i32 %x, i1 %replaceUndef0) nounwind { %val = load i32, ptr addrspace(4) getelementptr ([239 x i32], ptr addrspace(4) @gv, i64 0, i64 239), align 4 %mul12 = mul nsw i32 %val, 7 - br i1 undef, label %exit, label %bb + br i1 %replaceUndef0, label %exit, label %bb bb: %cmp = icmp slt i32 %x, 0 diff --git a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll --- a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll @@ -4,7 +4,7 @@ @_RSENC_gDcd_______________________________ = external protected addrspace(1) externally_initialized global [4096 x i8], align 16 -define protected amdgpu_kernel void @_RSENC_PRInit__________________________________() local_unnamed_addr #0 { +define protected amdgpu_kernel void @_RSENC_PRInit__________________________________( i1 %replaceUndef0) local_unnamed_addr #0 { entry: %runtimeVersionCopy = alloca [128 x i8], align 16, addrspace(5) %licenseVersionCopy = alloca [128 x i8], align 16, addrspace(5) @@ -18,7 +18,7 @@ br i1 %cmp13, label %cleanup.cont, label %if.end15 if.end15: ; preds = %if.end - br i1 undef, label %cleanup.cont, label %lor.lhs.false17 + br i1 %replaceUndef0, label %cleanup.cont, label %lor.lhs.false17 lor.lhs.false17: ; preds = %if.end15 br label %while.cond.i diff --git a/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll b/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll --- a/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll +++ b/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll @@ -78,12 +78,12 @@ ; GCN-LABEL: {{^}}test_mfma_f32_32x32x1f32_call_multi_bb: ; GCN: v_mfma_f32_32x32x1{{.*}} a[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9:]+}}, a[{{[0-9:]+}}] -define amdgpu_kernel void @test_mfma_f32_32x32x1f32_call_multi_bb(ptr addrspace(1) %arg) #0 { +define amdgpu_kernel void @test_mfma_f32_32x32x1f32_call_multi_bb(ptr addrspace(1) %arg, i1 %replaceUndef0) #0 { bb1: %in.1 = load <32 x float>, ptr addrspace(1) %arg %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %in.1, i32 1, i32 2, i32 3) store <32 x float> %mai.1, ptr addrspace(1) %arg - br i1 undef, label %bb2, label %bb3 + br i1 %replaceUndef0, label %bb2, label %bb3 br label %bb2 bb2: diff --git a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll --- a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll @@ -55,11 +55,10 @@ ; GCN: s_load_dword s ; GCN-NOT: global_load_dword ; GCN: global_store_dword -define amdgpu_kernel void @memory_phi_no_clobber(ptr addrspace(1) %arg) { +define amdgpu_kernel void @memory_phi_no_clobber(ptr addrspace(1) %arg, i1 %replaceUndef0) { ; CHECK-LABEL: @memory_phi_no_clobber( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0 -; CHECK-NEXT: br i1 undef, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !amdgpu.uniform !0 ; CHECK: if.then: ; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier() ; CHECK-NEXT: br label [[IF_END:%.*]], !amdgpu.uniform !0 @@ -76,7 +75,7 @@ ; bb: %i = load i32, ptr addrspace(1) %arg, align 4 - br i1 undef, label %if.then, label %if.else + br i1 %replaceUndef0, label %if.then, label %if.else if.then: tail call void @llvm.amdgcn.s.barrier() @@ -101,11 +100,10 @@ ; GCN: global_store_dword ; GCN: global_load_dword ; GCN: global_store_dword -define amdgpu_kernel void @memory_phi_clobber1(ptr addrspace(1) %arg) { +define amdgpu_kernel void @memory_phi_clobber1(ptr addrspace(1) %arg, i1 %replaceUndef0) { ; CHECK-LABEL: @memory_phi_clobber1( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0 -; CHECK-NEXT: br i1 undef, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !amdgpu.uniform !0 ; CHECK: if.then: ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 3 ; CHECK-NEXT: store i32 1, ptr addrspace(1) [[GEP]], align 4 @@ -123,7 +121,7 @@ ; bb: %i = load i32, ptr addrspace(1) %arg, align 4 - br i1 undef, label %if.then, label %if.else + br i1 %replaceUndef0, label %if.then, label %if.else if.then: %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 3 @@ -149,11 +147,10 @@ ; GCN: s_barrier ; GCN: global_load_dword ; GCN: global_store_dword -define amdgpu_kernel void @memory_phi_clobber2(ptr addrspace(1) %arg) { +define amdgpu_kernel void @memory_phi_clobber2(ptr addrspace(1) %arg, i1 %replaceUndef0) { ; CHECK-LABEL: @memory_phi_clobber2( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0 -; CHECK-NEXT: br i1 undef, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !amdgpu.uniform !0 ; CHECK: if.then: ; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier() ; CHECK-NEXT: br label [[IF_END:%.*]], !amdgpu.uniform !0 @@ -171,7 +168,7 @@ ; bb: %i = load i32, ptr addrspace(1) %arg, align 4 - br i1 undef, label %if.then, label %if.else + br i1 %replaceUndef0, label %if.then, label %if.else if.then: tail call void @llvm.amdgcn.s.barrier() diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll @@ -13,10 +13,10 @@ ; CHECK: endif: ; CHECK: %phi.ptr = phi ptr addrspace(3) [ %arrayidx0, %if ], [ %arrayidx1, %else ] ; CHECK: store i32 0, ptr addrspace(3) %phi.ptr, align 4 -define amdgpu_kernel void @branch_ptr_var_same_alloca(i32 %a, i32 %b) #0 { +define amdgpu_kernel void @branch_ptr_var_same_alloca(i32 %a, i32 %b, i1 %replaceUndef0) #0 { entry: %alloca = alloca [64 x i32], align 4, addrspace(5) - br i1 undef, label %if, label %else + br i1 %replaceUndef0, label %if, label %else if: %arrayidx0 = getelementptr inbounds [64 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a @@ -34,10 +34,10 @@ ; CHECK-LABEL: @branch_ptr_phi_alloca_null_0( ; CHECK: %phi.ptr = phi ptr addrspace(3) [ %arrayidx0, %if ], [ null, %entry ] -define amdgpu_kernel void @branch_ptr_phi_alloca_null_0(i32 %a, i32 %b) #0 { +define amdgpu_kernel void @branch_ptr_phi_alloca_null_0(i32 %a, i32 %b, i1 %replaceUndef0) #0 { entry: %alloca = alloca [64 x i32], align 4, addrspace(5) - br i1 undef, label %if, label %endif + br i1 %replaceUndef0, label %if, label %endif if: %arrayidx0 = getelementptr inbounds [64 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a @@ -51,10 +51,10 @@ ; CHECK-LABEL: @branch_ptr_phi_alloca_null_1( ; CHECK: %phi.ptr = phi ptr addrspace(3) [ null, %entry ], [ %arrayidx0, %if ] -define amdgpu_kernel void @branch_ptr_phi_alloca_null_1(i32 %a, i32 %b) #0 { +define amdgpu_kernel void @branch_ptr_phi_alloca_null_1(i32 %a, i32 %b, i1 %replaceUndef0) #0 { entry: %alloca = alloca [64 x i32], align 4, addrspace(5) - br i1 undef, label %if, label %endif + br i1 %replaceUndef0, label %if, label %endif if: %arrayidx0 = getelementptr inbounds [64 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a @@ -97,10 +97,10 @@ ; CHECK: endif: ; CHECK: %phi.ptr = phi ptr addrspace(5) [ %arrayidx0, %if ], [ %arrayidx1, %else ] ; CHECK: store i32 0, ptr addrspace(5) %phi.ptr, align 4 -define amdgpu_kernel void @branch_ptr_alloca_unknown_obj(i32 %a, i32 %b) #0 { +define amdgpu_kernel void @branch_ptr_alloca_unknown_obj(i32 %a, i32 %b, i1 %replaceUndef0) #0 { entry: %alloca = alloca [64 x i32], align 4, addrspace(5) - br i1 undef, label %if, label %else + br i1 %replaceUndef0, label %if, label %else if: %arrayidx0 = getelementptr inbounds [64 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll @@ -77,13 +77,13 @@ ret void } -define amdgpu_kernel void @lds_promoted_alloca_select_input_phi(i32 %a, i32 %b, i32 %c) #0 { +define amdgpu_kernel void @lds_promoted_alloca_select_input_phi(i32 %a, i32 %b, i32 %c, i1 %replaceUndef0) #0 { entry: %alloca = alloca [16 x i32], align 4, addrspace(5) %ptr0 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a %ptr1 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %b store i32 0, ptr addrspace(5) %ptr0 - br i1 undef, label %bb1, label %bb2 + br i1 %replaceUndef0, label %bb1, label %bb2 bb1: %ptr2 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %c diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll --- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll @@ -6,7 +6,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0 -define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3) #1 { +define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %replaceUndef0) #1 { bb: %id.x = call i32 @llvm.amdgcn.workitem.id.x() %cmp0 = icmp eq i32 %id.x, 0 @@ -18,7 +18,7 @@ bb4: ; preds = %bb6, %bb %tmp5 = phi <2 x i32> [ zeroinitializer, %bb ], [ %tmp13, %bb6 ] - br i1 undef, label %bb15, label %bb16 + br i1 %replaceUndef0, label %bb15, label %bb16 bb6: ; preds = %bb6, %bb3 %tmp7 = phi <2 x i32> [ zeroinitializer, %bb3 ], [ %tmp13, %bb6 ] diff --git a/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll b/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll --- a/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll @@ -3,23 +3,23 @@ ; definition on every path (there should at least be IMPLICIT_DEF instructions). target triple = "amdgcn--" -define amdgpu_kernel void @func() { +define amdgpu_kernel void @func( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { B0: - br i1 undef, label %B1, label %B2 + br i1 %replaceUndef0, label %B1, label %B2 B1: br label %B2 B2: %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ , %B0 ] - br i1 undef, label %B20.1, label %B20.2 + br i1 %replaceUndef1, label %B20.1, label %B20.2 B20.1: br label %B20.2 B20.2: %v2 = phi <4 x float> [ zeroinitializer, %B20.1 ], [ %v0, %B2 ] - br i1 undef, label %B30.1, label %B30.2 + br i1 %replaceUndef2, label %B30.1, label %B30.2 B30.1: %sub = fsub <4 x float> %v2, undef diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll @@ -9,7 +9,7 @@ ; GCN: s_cbranch_scc1 ; GCN-NOT: s_endpgm ; GCN: .Lfunc_end0 -define amdgpu_kernel void @annotate_unreachable_noloop(ptr addrspace(1) noalias nocapture readonly %arg) #0 { +define amdgpu_kernel void @annotate_unreachable_noloop(ptr addrspace(1) noalias nocapture readonly %arg, i1 %replaceUndef0) #0 { bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() br label %bb1 @@ -18,7 +18,7 @@ %tmp2 = sext i32 %tmp to i64 %tmp3 = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i64 %tmp2 %tmp4 = load <4 x float>, ptr addrspace(1) %tmp3, align 16 - br i1 undef, label %bb5, label %bb3 + br i1 %replaceUndef0, label %bb5, label %bb3 bb3: ; preds = %bb1 %tmp6 = extractelement <4 x float> %tmp4, i32 2 @@ -75,7 +75,7 @@ ; GCN: s_cbranch_scc1 ; GCN: s_endpgm ; GCN: .Lfunc_end -define amdgpu_kernel void @uniform_annotate_ret_noloop(ptr addrspace(1) noalias nocapture readonly %arg, i32 %tmp) #0 { +define amdgpu_kernel void @uniform_annotate_ret_noloop(ptr addrspace(1) noalias nocapture readonly %arg, i32 %tmp, i1 %replaceUndef0) #0 { bb: br label %bb1 @@ -83,7 +83,7 @@ %tmp2 = sext i32 %tmp to i64 %tmp3 = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i64 %tmp2 %tmp4 = load <4 x float>, ptr addrspace(1) %tmp3, align 16 - br i1 undef, label %bb5, label %bb3 + br i1 %replaceUndef0, label %bb5, label %bb3 bb3: ; preds = %bb1 %tmp6 = extractelement <4 x float> %tmp4, i32 2 diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll @@ -11,7 +11,7 @@ ; GCN: s_and_saveexec_b64 ; GCN-NOT: s_endpgm ; GCN: .Lfunc_end0 -define amdgpu_kernel void @annotate_unreachable(ptr addrspace(1) noalias nocapture readonly %arg) #0 { +define amdgpu_kernel void @annotate_unreachable(ptr addrspace(1) noalias nocapture readonly %arg, i1 %replaceUndef0) #0 { bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() br label %bb1 @@ -20,7 +20,7 @@ %tmp2 = sext i32 %tmp to i64 %tmp3 = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i64 %tmp2 %tmp4 = load <4 x float>, ptr addrspace(1) %tmp3, align 16 - br i1 undef, label %bb3, label %bb5 ; label order reversed + br i1 %replaceUndef0, label %bb3, label %bb5 ; label order reversed bb3: ; preds = %bb1 %tmp6 = extractelement <4 x float> %tmp4, i32 2 diff --git a/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll b/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll --- a/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll +++ b/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll @@ -7,7 +7,7 @@ ; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]] ; SI-NOT: v_readlane_b32 [[SAVED]] -define amdgpu_ps void @main() #0 { +define amdgpu_ps void @main( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11) #0 { main_body: %tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 16, i32 0) %tmp1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 32, i32 0) @@ -306,7 +306,7 @@ br label %ENDIF2564 ELSE2632: ; preds = %ELSE2596 - br i1 undef, label %ENDIF2594, label %ELSE2650 + br i1 %replaceUndef0, label %ENDIF2594, label %ELSE2650 ELSE2650: ; preds = %ELSE2632 %tmp226 = fcmp oeq float %temp292.11, %tmp110 @@ -315,7 +315,7 @@ br i1 %tmp228, label %IF2667, label %ELSE2668 IF2667: ; preds = %ELSE2650 - br i1 undef, label %ENDIF2594, label %ELSE2671 + br i1 %replaceUndef1, label %ENDIF2594, label %ELSE2671 ELSE2668: ; preds = %ELSE2650 %tmp229 = fcmp oeq float %temp292.11, %tmp128 @@ -339,13 +339,13 @@ br i1 %tmp237, label %ENDIF2594, label %ELSE2740 ELSE2740: ; preds = %ELSE2704 - br i1 undef, label %IF2757, label %ELSE2758 + br i1 %replaceUndef2, label %IF2757, label %ELSE2758 IF2757: ; preds = %ELSE2740 - br i1 undef, label %ENDIF2594, label %ELSE2761 + br i1 %replaceUndef3, label %ENDIF2594, label %ELSE2761 ELSE2758: ; preds = %ELSE2740 - br i1 undef, label %IF2775, label %ENDIF2594 + br i1 %replaceUndef4, label %IF2775, label %ENDIF2594 ELSE2761: ; preds = %IF2757 br label %ENDIF2594 @@ -355,10 +355,10 @@ br i1 %tmp238, label %ENDIF2594, label %ELSE2779 ELSE2779: ; preds = %IF2775 - br i1 undef, label %ENDIF2594, label %ELSE2782 + br i1 %replaceUndef5, label %ENDIF2594, label %ELSE2782 ELSE2782: ; preds = %ELSE2779 - br i1 undef, label %ENDIF2594, label %ELSE2785 + br i1 %replaceUndef6, label %ENDIF2594, label %ELSE2785 ELSE2785: ; preds = %ELSE2782 %tmp239 = fcmp olt float undef, 0.000000e+00 @@ -399,7 +399,7 @@ br label %LOOP ELSE2800: ; preds = %ELSE2797 - br i1 undef, label %ENDIF2795, label %ELSE2803 + br i1 %replaceUndef7, label %ENDIF2795, label %ELSE2803 ELSE2803: ; preds = %ELSE2800 %tmp264 = fsub float %tmp20, undef @@ -451,16 +451,16 @@ br i1 %tmp306, label %ENDIF2795, label %ELSE2809 ELSE2809: ; preds = %ELSE2806 - br i1 undef, label %ENDIF2795, label %ELSE2812 + br i1 %replaceUndef8, label %ENDIF2795, label %ELSE2812 ELSE2812: ; preds = %ELSE2809 - br i1 undef, label %ENDIF2795, label %ELSE2815 + br i1 %replaceUndef9, label %ENDIF2795, label %ELSE2815 ELSE2815: ; preds = %ELSE2812 - br i1 undef, label %ENDIF2795, label %ELSE2818 + br i1 %replaceUndef10, label %ENDIF2795, label %ELSE2818 ELSE2818: ; preds = %ELSE2815 - br i1 undef, label %ENDIF2795, label %ELSE2821 + br i1 %replaceUndef11, label %ENDIF2795, label %ELSE2821 ELSE2821: ; preds = %ELSE2818 %tmp307 = fsub float %tmp56, undef diff --git a/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll b/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll --- a/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll +++ b/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll @@ -19,7 +19,7 @@ declare float @llvm.fmuladd.f32(float, float, float) #0 ; CHECK: s_endpgm -define amdgpu_kernel void @foo(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture readonly %arg1, ptr addrspace(1) noalias nocapture %arg2, float %arg3) local_unnamed_addr !reqd_work_group_size !0 { +define amdgpu_kernel void @foo(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture readonly %arg1, ptr addrspace(1) noalias nocapture %arg2, float %arg3, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5) local_unnamed_addr !reqd_work_group_size !0 { bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.y() %tmp4 = tail call i32 @llvm.amdgcn.workitem.id.x() @@ -31,7 +31,7 @@ br label %bb12 bb11: ; preds = %bb30 - br i1 undef, label %bb37, label %bb38 + br i1 %replaceUndef0, label %bb37, label %bb38 bb12: ; preds = %bb30, %bb br i1 false, label %.preheader, label %.loopexit145 @@ -43,7 +43,7 @@ %tmp14 = phi i32 [ %tmp5, %.loopexit145 ], [ %tmp20, %.loopexit ] %tmp15 = add nsw i32 %tmp14, -3 %tmp16 = mul i32 %tmp14, 21 - br i1 undef, label %bb17, label %.loopexit + br i1 %replaceUndef1, label %bb17, label %.loopexit bb17: ; preds = %bb13 %tmp18 = mul i32 %tmp15, 224 @@ -52,7 +52,7 @@ .loopexit: ; preds = %bb21, %bb13 %tmp20 = add nuw nsw i32 %tmp14, 16 - br i1 undef, label %bb13, label %bb26 + br i1 %replaceUndef2, label %bb13, label %bb26 bb21: ; preds = %bb21, %bb17 %tmp22 = phi i32 [ %tmp4, %bb17 ], [ %tmp25, %bb21 ] @@ -60,7 +60,7 @@ %tmp24 = getelementptr inbounds float, ptr addrspace(3) @0, i32 %tmp23 store float undef, ptr addrspace(3) %tmp24, align 4 %tmp25 = add nuw i32 %tmp22, 8 - br i1 undef, label %bb21, label %.loopexit + br i1 %replaceUndef3, label %bb21, label %.loopexit bb26: ; preds = %.loopexit br label %bb31 @@ -72,7 +72,7 @@ br i1 %tmp29, label %.preheader, label %.loopexit145 bb30: ; preds = %bb31 - br i1 undef, label %bb11, label %bb12 + br i1 %replaceUndef4, label %bb11, label %bb12 bb31: ; preds = %bb31, %bb26 %tmp32 = phi i32 [ %tmp9, %bb26 ], [ undef, %bb31 ] @@ -80,7 +80,7 @@ %tmp34 = load float, ptr addrspace(3) %tmp33, align 4 %tmp35 = tail call float @llvm.fmuladd.f32(float %tmp34, float undef, float undef) %tmp36 = tail call float @llvm.fmuladd.f32(float undef, float undef, float %tmp35) - br i1 undef, label %bb30, label %bb31 + br i1 %replaceUndef5, label %bb30, label %bb31 bb37: ; preds = %bb11 br label %bb38 diff --git a/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll b/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll --- a/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll +++ b/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll @@ -9,10 +9,10 @@ ; GCN: image_sample ; GCN: exp null -define amdgpu_ps float @sinking_img_sample() { +define amdgpu_ps float @sinking_img_sample( i1 %replaceUndef0) { main_body: %i = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0) - br i1 undef, label %endif1, label %if1 + br i1 %replaceUndef0, label %endif1, label %if1 if1: ; preds = %main_body call void @llvm.amdgcn.kill(i1 false) #4 diff --git a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll --- a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll +++ b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll @@ -1137,7 +1137,7 @@ } ; bug 28550 -define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 { +define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i1 %replaceUndef0) #0 { ; SI-LABEL: phi_use_def_before_kill: ; SI: ; %bb.0: ; %bb ; SI-NEXT: v_add_f32_e64 v1, s0, 1.0 @@ -1269,7 +1269,7 @@ %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00 %cmp.tmp2 = fcmp olt float %tmp2, 0.0 call void @llvm.amdgcn.kill(i1 %cmp.tmp2) - br i1 undef, label %phibb, label %bb8 + br i1 %replaceUndef0, label %phibb, label %bb8 phibb: %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ] diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll --- a/llvm/test/CodeGen/AMDGPU/smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/smrd.ll @@ -686,9 +686,9 @@ ; GCN: buffer_load_dword v0, v0, ; GCN-NEXT: s_waitcnt ; GCN-NEXT: ; return to shader part epilog -define amdgpu_cs float @arg_divergence(i32 inreg %unused, <3 x i32> %arg4) #0 { +define amdgpu_cs float @arg_divergence(i32 inreg %unused, <3 x i32> %arg4, i1 %replaceUndef0) #0 { main_body: - br i1 undef, label %if1, label %endif1 + br i1 %replaceUndef0, label %if1, label %endif1 if1: ; preds = %main_body store i32 0, ptr addrspace(3) undef, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/split-smrd.ll b/llvm/test/CodeGen/AMDGPU/split-smrd.ll --- a/llvm/test/CodeGen/AMDGPU/split-smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/split-smrd.ll @@ -6,11 +6,11 @@ ; GCN-LABEL: {{^}}split_smrd_add_worklist: ; GCN: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 -define amdgpu_ps void @split_smrd_add_worklist(ptr addrspace(4) inreg %arg) #0 { +define amdgpu_ps void @split_smrd_add_worklist(ptr addrspace(4) inreg %arg, i1 %replaceUndef0) #0 { bb: %tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 96, i32 0) %tmp1 = bitcast float %tmp to i32 - br i1 undef, label %bb2, label %bb3 + br i1 %replaceUndef0, label %bb2, label %bb3 bb2: ; preds = %bb unreachable diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll --- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll @@ -2,19 +2,19 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL:{{^}}row_filter_C1_D0: -define amdgpu_kernel void @row_filter_C1_D0() #0 { +define amdgpu_kernel void @row_filter_C1_D0( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) #0 { entry: - br i1 undef, label %for.inc.1, label %do.body.preheader + br i1 %replaceUndef0, label %for.inc.1, label %do.body.preheader do.body.preheader: ; preds = %entry %tmp = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1 - br i1 undef, label %do.body56.1, label %do.body90 + br i1 %replaceUndef1, label %do.body56.1, label %do.body90 do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ %tmp, %do.body.preheader ] %tmp2 = insertelement <4 x i32> %tmp1, i32 undef, i32 2 %tmp3 = insertelement <4 x i32> %tmp2, i32 undef, i32 3 - br i1 undef, label %do.body124.1, label %do.body.1562.preheader + br i1 %replaceUndef2, label %do.body124.1, label %do.body.1562.preheader do.body.1562.preheader: ; preds = %do.body124.1, %do.body90 %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ] @@ -42,23 +42,23 @@ ; GCN-LABEL: {{^}}foo: ; GCN: s_endpgm -define amdgpu_ps void @foo() #0 { +define amdgpu_ps void @foo( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6) #0 { bb: - br i1 undef, label %bb2, label %bb1 + br i1 %replaceUndef0, label %bb2, label %bb1 bb1: ; preds = %bb - br i1 undef, label %bb4, label %bb6 + br i1 %replaceUndef1, label %bb4, label %bb6 bb2: ; preds = %bb4, %bb %tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ] - br i1 undef, label %bb9, label %bb13 + br i1 %replaceUndef2, label %bb9, label %bb13 bb4: ; preds = %bb7, %bb6, %bb1 %tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ] br label %bb2 bb6: ; preds = %bb1 - br i1 undef, label %bb7, label %bb4 + br i1 %replaceUndef3, label %bb7, label %bb4 bb7: ; preds = %bb6 %tmp8 = fmul float undef, undef @@ -71,7 +71,7 @@ br label %bb14 bb13: ; preds = %bb2 - br i1 undef, label %bb23, label %bb24 + br i1 %replaceUndef4, label %bb23, label %bb24 bb14: ; preds = %bb27, %bb24, %bb9 %tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ] @@ -82,11 +82,11 @@ ret void bb23: ; preds = %bb13 - br i1 undef, label %bb24, label %bb26 + br i1 %replaceUndef5, label %bb24, label %bb26 bb24: ; preds = %bb26, %bb23, %bb13 %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ] - br i1 undef, label %bb27, label %bb14 + br i1 %replaceUndef6, label %bb27, label %bb14 bb26: ; preds = %bb23 br label %bb24 diff --git a/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll b/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll --- a/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll +++ b/llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s -define void @test() #1 { +define void @test( i1 %replaceUndef0) #1 { ; Clean up the unreachable blocks introduced with LowerSwitch pass. ; This test ensures that, in the pass flow, UnreachableBlockElim pass ; follows the LowerSwitch. Otherwise, this testcase will crash @@ -22,7 +22,7 @@ ; GCN: bb.{{[0-9]+}}.UnifiedReturnBlock: entry: %idx = tail call i32 @llvm.amdgcn.workitem.id.x() #0 - br i1 undef, label %entry.true.blk, label %entry.false.blk + br i1 %replaceUndef0, label %entry.true.blk, label %entry.false.blk entry.true.blk: ; preds = %entry %exit.cmp = icmp ult i32 %idx, 3 diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll --- a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll +++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll @@ -5,7 +5,7 @@ ; We may have subregister live ranges that are undefined on some paths. The ; verifier should not complain about this. -define amdgpu_kernel void @func() #0 { +define amdgpu_kernel void @func( i1 %replaceUndef0, i1 %replaceUndef1) #0 { ; CHECK-LABEL: func: ; CHECK: ; %bb.0: ; %B0 ; CHECK-NEXT: s_mov_b32 s0, 0 @@ -18,14 +18,14 @@ ; CHECK-NEXT: ds_write_b32 v0, v0 ; CHECK-NEXT: s_endpgm B0: - br i1 undef, label %B1, label %B2 + br i1 %replaceUndef0, label %B1, label %B2 B1: br label %B2 B2: %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ , %B0 ] - br i1 undef, label %B30.1, label %B30.2 + br i1 %replaceUndef1, label %B30.1, label %B30.2 B30.1: %sub = fsub <4 x float> %v0, undef diff --git a/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll b/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll --- a/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll +++ b/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll @@ -5,7 +5,7 @@ ; SI hits an assertion at -O0, evergreen hits a not implemented unreachable. ; COMMON-LABEL: {{^}}branch_true: -define amdgpu_kernel void @branch_true(ptr addrspace(1) nocapture %main, i32 %main_stride) #0 { +define amdgpu_kernel void @branch_true(ptr addrspace(1) nocapture %main, i32 %main_stride, i1 %replaceUndef0) #0 { entry: br i1 true, label %for.end, label %for.body.lr.ph @@ -27,7 +27,7 @@ %add.ptr3 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr4.sum %4 = load i32, ptr addrspace(1) %add.ptr3, align 4 %add.ptr6 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 undef - br i1 undef, label %for.end, label %for.body + br i1 %replaceUndef0, label %for.end, label %for.body for.end: ; preds = %for.body, %entry ret void @@ -36,7 +36,7 @@ ; COMMON-LABEL: {{^}}branch_false: ; SI: s_cbranch_scc1 ; SI: s_endpgm -define amdgpu_kernel void @branch_false(ptr addrspace(1) nocapture %main, i32 %main_stride) #0 { +define amdgpu_kernel void @branch_false(ptr addrspace(1) nocapture %main, i32 %main_stride, i1 %replaceUndef0) #0 { entry: br i1 false, label %for.end, label %for.body.lr.ph @@ -58,19 +58,18 @@ %add.ptr3 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr4.sum %4 = load i32, ptr addrspace(1) %add.ptr3, align 4 %add.ptr6 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 undef - br i1 undef, label %for.end, label %for.body + br i1 %replaceUndef0, label %for.end, label %for.body for.end: ; preds = %for.body, %entry ret void } -; COMMON-LABEL: {{^}}branch_undef: ; SI: s_cbranch_scc1 ; SI: s_cbranch_scc1 ; SI: s_endpgm -define amdgpu_kernel void @branch_undef(ptr addrspace(1) nocapture %main, i32 %main_stride) #0 { +define amdgpu_kernel void @branch_undef(ptr addrspace(1) nocapture %main, i32 %main_stride, i1 %replaceUndef0, i1 %replaceUndef1) #0 { entry: - br i1 undef, label %for.end, label %for.body.lr.ph + br i1 %replaceUndef0, label %for.end, label %for.body.lr.ph for.body.lr.ph: ; preds = %entry %add.ptr.sum = shl i32 %main_stride, 1 @@ -90,7 +89,7 @@ %add.ptr3 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr4.sum %4 = load i32, ptr addrspace(1) %add.ptr3, align 4 %add.ptr6 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 undef - br i1 undef, label %for.end, label %for.body + br i1 %replaceUndef1, label %for.end, label %for.body for.end: ; preds = %for.body, %entry ret void diff --git a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll --- a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -1134,7 +1134,7 @@ ret void } -define void @move_to_valu_vgpr_operand_phi(ptr addrspace(3) %out) { +define void @move_to_valu_vgpr_operand_phi(ptr addrspace(3) %out, i1 %replaceUndef0) { ; SI-LABEL: move_to_valu_vgpr_operand_phi: ; SI: ; %bb.0: ; %bb0 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1187,7 +1187,7 @@ %tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ] %tmp1 = add nsw i32 %tmp0, -1 %tmp2 = getelementptr inbounds i32, ptr addrspace(3) %out, i32 %tmp1 - br i1 undef, label %bb2, label %bb3 + br i1 %replaceUndef0, label %bb2, label %bb3 bb2: ; preds = %bb1 store volatile i32 1, ptr addrspace(3) %tmp2, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/uniform-crash.ll b/llvm/test/CodeGen/AMDGPU/uniform-crash.ll --- a/llvm/test/CodeGen/AMDGPU/uniform-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-crash.ll @@ -25,7 +25,7 @@ ; GCN: {{^}}[[LOOP:.L[A-Z0-9_]+]]: ; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: {{^}}[[BB0]]: -define amdgpu_kernel void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1) { +define amdgpu_kernel void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1, i1 %replaceUndef0) { bb: %cnd = trunc i32 %arg to i1 br i1 %cnd, label %bb2, label %bb5 @@ -45,7 +45,7 @@ br i1 %tmp10, label %bb11, label %bb12 bb11: ; preds = %bb11, %bb5 - br i1 undef, label %bb11, label %bb12 + br i1 %replaceUndef0, label %bb11, label %bb12 bb12: ; preds = %bb11, %bb5 ret void diff --git a/llvm/test/CodeGen/AMDGPU/v1024.ll b/llvm/test/CodeGen/AMDGPU/v1024.ll --- a/llvm/test/CodeGen/AMDGPU/v1024.ll +++ b/llvm/test/CodeGen/AMDGPU/v1024.ll @@ -6,11 +6,11 @@ ; GCN-NOT: v_accvgpr ; GCN-COUNT-32: v_mov_b32_e32 ; GCN-NOT: v_accvgpr -define amdgpu_kernel void @test_v1024() { +define amdgpu_kernel void @test_v1024( i1 %replaceUndef0) { entry: %alloca = alloca <32 x i32>, align 16, addrspace(5) call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 128, i1 false) - br i1 undef, label %if.then.i.i, label %if.else.i + br i1 %replaceUndef0, label %if.then.i.i, label %if.else.i if.then.i.i: ; preds = %entry call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) align 16 %alloca, ptr addrspace(5) align 4 undef, i64 128, i1 false) diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll --- a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll @@ -460,7 +460,7 @@ ret float %r2 } -define amdgpu_kernel void @livevariables_update_missed_block(ptr addrspace(1) %src1) { +define amdgpu_kernel void @livevariables_update_missed_block(ptr addrspace(1) %src1, i1 %replaceUndef0) { ; SI-LABEL: name: livevariables_update_missed_block ; SI: bb.0.entry: ; SI-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000) @@ -541,7 +541,7 @@ ret void if.then9: ; preds = %entry - br i1 undef, label %sw.bb18, label %sw.bb + br i1 %replaceUndef0, label %sw.bb18, label %sw.bb sw.bb: ; preds = %if.then9 %i17 = load i8, ptr addrspace(1) null, align 1 diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -891,7 +891,7 @@ ; GCN-LABEL: {{^}}test_branch_true: ; GFX1032: s_mov_b32 vcc_lo, exec_lo ; GFX1064: s_mov_b64 vcc, exec -define amdgpu_kernel void @test_branch_true() #2 { +define amdgpu_kernel void @test_branch_true( i1 %replaceUndef0) #2 { entry: br i1 true, label %for.end, label %for.body.lr.ph @@ -899,7 +899,7 @@ br label %for.body for.body: ; preds = %for.body, %for.body.lr.ph - br i1 undef, label %for.end, label %for.body + br i1 %replaceUndef0, label %for.end, label %for.body for.end: ; preds = %for.body, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll --- a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll @@ -4,7 +4,7 @@ declare i32 @printf(ptr nocapture, ...) nounwind -define i32 @main() nounwind { +define i32 @main( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10) nounwind { entry: br label %bb.i1.i @@ -12,10 +12,10 @@ br label %bb.i.i.i bb.i.i.i: ; preds = %bb.i.i.i, %bb.i1.i - br i1 undef, label %Cos.exit.i.i, label %bb.i.i.i + br i1 %replaceUndef0, label %Cos.exit.i.i, label %bb.i.i.i Cos.exit.i.i: ; preds = %bb.i.i.i - br i1 undef, label %bb2.i.i, label %bb.i1.i + br i1 %replaceUndef1, label %bb2.i.i, label %bb.i1.i bb2.i.i: ; preds = %Cos.exit.i.i br label %bb3.i.i @@ -24,13 +24,13 @@ br label %bb4.i.i bb4.i.i: ; preds = %bb4.i.i, %bb3.i.i - br i1 undef, label %bb5.i.i, label %bb4.i.i + br i1 %replaceUndef2, label %bb5.i.i, label %bb4.i.i bb5.i.i: ; preds = %bb4.i.i - br i1 undef, label %bb.i, label %bb3.i.i + br i1 %replaceUndef3, label %bb.i, label %bb3.i.i bb.i: ; preds = %bb.i, %bb5.i.i - br i1 undef, label %bb1.outer2.i.i.outer, label %bb.i + br i1 %replaceUndef4, label %bb1.outer2.i.i.outer, label %bb.i bb1.outer2.i.i.outer: ; preds = %Fft.exit.i, %bb5.i12.i, %bb.i br label %bb1.outer2.i.i @@ -39,22 +39,22 @@ br label %bb1.i.i bb1.i.i: ; preds = %bb1.i.i, %bb1.outer2.i.i - br i1 undef, label %bb2.i9.i, label %bb1.i.i + br i1 %replaceUndef5, label %bb2.i9.i, label %bb1.i.i bb2.i9.i: ; preds = %bb1.i.i - br i1 undef, label %bb4.i11.i, label %bb1.outer2.i.i + br i1 %replaceUndef6, label %bb4.i11.i, label %bb1.outer2.i.i bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i - br i1 undef, label %bb5.i12.i, label %bb4.i11.i + br i1 %replaceUndef7, label %bb5.i12.i, label %bb4.i11.i bb5.i12.i: ; preds = %bb4.i11.i - br i1 undef, label %bb7.i.i, label %bb1.outer2.i.i.outer + br i1 %replaceUndef8, label %bb7.i.i, label %bb1.outer2.i.i.outer bb7.i.i: ; preds = %bb7.i.i, %bb5.i12.i - br i1 undef, label %Fft.exit.i, label %bb7.i.i + br i1 %replaceUndef9, label %Fft.exit.i, label %bb7.i.i Fft.exit.i: ; preds = %bb7.i.i - br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer + br i1 %replaceUndef10, label %bb5.i, label %bb1.outer2.i.i.outer bb5.i: ; preds = %Fft.exit.i %0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", double undef, double undef) nounwind ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll --- a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll +++ b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll @@ -10,18 +10,18 @@ declare fastcc i32 @qtm_read_input(ptr nocapture) nounwind -define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes) nounwind { +define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18, i1 %replaceUndef19, i1 %replaceUndef20, i1 %replaceUndef21, i1 %replaceUndef22, i1 %replaceUndef23, i1 %replaceUndef24, i1 %replaceUndef25, i1 %replaceUndef26, i1 %replaceUndef27, i1 %replaceUndef28, i1 %replaceUndef29, i1 %replaceUndef30, i1 %replaceUndef31, i1 %replaceUndef32, i1 %replaceUndef33, i1 %replaceUndef34, i1 %replaceUndef35, i1 %replaceUndef36, i1 %replaceUndef37, i1 %replaceUndef38, i1 %replaceUndef39) nounwind { entry: - br i1 undef, label %bb245, label %bb3 + br i1 %replaceUndef0, label %bb245, label %bb3 bb3: ; preds = %entry - br i1 undef, label %bb5, label %bb4 + br i1 %replaceUndef1, label %bb5, label %bb4 bb4: ; preds = %bb3 ret i32 undef bb5: ; preds = %bb3 - br i1 undef, label %bb245, label %bb14 + br i1 %replaceUndef2, label %bb245, label %bb14 bb14: ; preds = %bb5 br label %bb238 @@ -30,34 +30,34 @@ br label %bb31 bb29: ; preds = %bb31 - br i1 undef, label %bb31, label %bb32 + br i1 %replaceUndef3, label %bb31, label %bb32 bb31: ; preds = %bb29, %bb28 - br i1 undef, label %bb29, label %bb32 + br i1 %replaceUndef4, label %bb29, label %bb32 bb32: ; preds = %bb31, %bb29 br label %bb33 bb33: ; preds = %bb33, %bb32 - br i1 undef, label %bb34, label %bb33 + br i1 %replaceUndef5, label %bb34, label %bb33 bb34: ; preds = %bb33 - br i1 undef, label %bb35, label %bb36 + br i1 %replaceUndef6, label %bb35, label %bb36 bb35: ; preds = %bb34 br label %bb36 bb36: ; preds = %bb46, %bb35, %bb34 - br i1 undef, label %bb40, label %bb37 + br i1 %replaceUndef7, label %bb40, label %bb37 bb37: ; preds = %bb36 - br i1 undef, label %bb77, label %bb60 + br i1 %replaceUndef8, label %bb77, label %bb60 bb40: ; preds = %bb36 - br i1 undef, label %bb46, label %bb41 + br i1 %replaceUndef9, label %bb46, label %bb41 bb41: ; preds = %bb40 - br i1 undef, label %bb45, label %bb42 + br i1 %replaceUndef10, label %bb45, label %bb42 bb42: ; preds = %bb41 ret i32 undef @@ -81,25 +81,25 @@ br label %bb111 bb109: ; preds = %bb111 - br i1 undef, label %bb111, label %bb112 + br i1 %replaceUndef11, label %bb111, label %bb112 bb111: ; preds = %bb109, %bb108 - br i1 undef, label %bb109, label %bb112 + br i1 %replaceUndef12, label %bb109, label %bb112 bb112: ; preds = %bb111, %bb109 br label %bb113 bb113: ; preds = %bb113, %bb112 - br i1 undef, label %bb114, label %bb113 + br i1 %replaceUndef13, label %bb114, label %bb113 bb114: ; preds = %bb113 - br i1 undef, label %bb115, label %bb116 + br i1 %replaceUndef14, label %bb115, label %bb116 bb115: ; preds = %bb114 br label %bb116 bb116: ; preds = %bb115, %bb114 - br i1 undef, label %bb120, label %bb117 + br i1 %replaceUndef15, label %bb120, label %bb117 bb117: ; preds = %bb116 br label %bb136 @@ -108,13 +108,13 @@ ret i32 undef bb128: ; preds = %bb136 - br i1 undef, label %bb134, label %bb129 + br i1 %replaceUndef16, label %bb134, label %bb129 bb129: ; preds = %bb128 - br i1 undef, label %bb133, label %bb130 + br i1 %replaceUndef17, label %bb133, label %bb130 bb130: ; preds = %bb129 - br i1 undef, label %bb132, label %bb131 + br i1 %replaceUndef18, label %bb132, label %bb131 bb131: ; preds = %bb130 ret i32 undef @@ -129,7 +129,7 @@ br label %bb136 bb136: ; preds = %bb134, %bb117 - br i1 undef, label %bb198, label %bb128 + br i1 %replaceUndef19, label %bb198, label %bb128 bb138: ; preds = %bb77 %0 = trunc i32 undef to i16 ; [#uses=1] @@ -141,34 +141,34 @@ br i1 %1, label %bb141, label %bb142 bb141: ; preds = %bb139, %bb138 - br i1 undef, label %bb139, label %bb142 + br i1 %replaceUndef20, label %bb139, label %bb142 bb142: ; preds = %bb141, %bb139 br label %bb143 bb143: ; preds = %bb143, %bb142 - br i1 undef, label %bb144, label %bb143 + br i1 %replaceUndef21, label %bb144, label %bb143 bb144: ; preds = %bb143 - br i1 undef, label %bb145, label %bb146 + br i1 %replaceUndef22, label %bb145, label %bb146 bb145: ; preds = %bb144 unreachable bb146: ; preds = %bb156, %bb144 - br i1 undef, label %bb150, label %bb147 + br i1 %replaceUndef23, label %bb150, label %bb147 bb147: ; preds = %bb146 - br i1 undef, label %bb157, label %bb148 + br i1 %replaceUndef24, label %bb157, label %bb148 bb148: ; preds = %bb147 - br i1 undef, label %bb149, label %bb157 + br i1 %replaceUndef25, label %bb149, label %bb157 bb149: ; preds = %bb148 br label %bb150 bb150: ; preds = %bb149, %bb146 - br i1 undef, label %bb156, label %bb152 + br i1 %replaceUndef26, label %bb156, label %bb152 bb152: ; preds = %bb150 unreachable @@ -177,7 +177,7 @@ br label %bb146 bb157: ; preds = %bb148, %bb147 - br i1 undef, label %bb167, label %bb160 + br i1 %replaceUndef27, label %bb167, label %bb160 bb160: ; preds = %bb157 ret i32 undef @@ -186,31 +186,31 @@ br label %bb170 bb168: ; preds = %bb170 - br i1 undef, label %bb170, label %bb171 + br i1 %replaceUndef28, label %bb170, label %bb171 bb170: ; preds = %bb168, %bb167 - br i1 undef, label %bb168, label %bb171 + br i1 %replaceUndef29, label %bb168, label %bb171 bb171: ; preds = %bb170, %bb168 br label %bb172 bb172: ; preds = %bb172, %bb171 - br i1 undef, label %bb173, label %bb172 + br i1 %replaceUndef30, label %bb173, label %bb172 bb173: ; preds = %bb172 - br i1 undef, label %bb174, label %bb175 + br i1 %replaceUndef31, label %bb174, label %bb175 bb174: ; preds = %bb173 unreachable bb175: ; preds = %bb179, %bb173 - br i1 undef, label %bb179, label %bb176 + br i1 %replaceUndef32, label %bb179, label %bb176 bb176: ; preds = %bb175 - br i1 undef, label %bb186, label %bb177 + br i1 %replaceUndef33, label %bb186, label %bb177 bb177: ; preds = %bb176 - br i1 undef, label %bb178, label %bb186 + br i1 %replaceUndef34, label %bb178, label %bb186 bb178: ; preds = %bb177 br label %bb179 @@ -222,7 +222,7 @@ br label %bb195 bb187: ; preds = %bb195 - br i1 undef, label %bb193, label %bb189 + br i1 %replaceUndef35, label %bb193, label %bb189 bb189: ; preds = %bb187 %2 = tail call fastcc i32 @qtm_read_input(ptr %qtm) nounwind ; [#uses=0] @@ -232,25 +232,25 @@ br label %bb195 bb195: ; preds = %bb193, %bb186 - br i1 undef, label %bb198, label %bb187 + br i1 %replaceUndef36, label %bb198, label %bb187 bb197: ; preds = %bb77 ret i32 -124 bb198: ; preds = %bb195, %bb136 - br i1 undef, label %bb211.preheader, label %bb214 + br i1 %replaceUndef37, label %bb211.preheader, label %bb214 bb211.preheader: ; preds = %bb198 br label %bb211 bb211: ; preds = %bb211, %bb211.preheader - br i1 undef, label %bb214, label %bb211 + br i1 %replaceUndef38, label %bb214, label %bb211 bb214: ; preds = %bb211, %bb198 br label %bb215 bb215: ; preds = %bb238, %bb214 - br i1 undef, label %bb28, label %bb216 + br i1 %replaceUndef39, label %bb28, label %bb216 bb216: ; preds = %bb215 br label %bb238 diff --git a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll @@ -4,9 +4,9 @@ declare fastcc ptr @memory_Malloc(i32) nounwind -define fastcc ptr @t1() nounwind { +define fastcc ptr @t1( i1 %replaceUndef0) nounwind { entry: - br i1 undef, label %bb, label %bb1 + br i1 %replaceUndef0, label %bb, label %bb1 bb: ; preds = %entry ret ptr undef @@ -18,12 +18,12 @@ } -define i32 @t2(i32 %argc, ptr nocapture %argv) nounwind { +define i32 @t2(i32 %argc, ptr nocapture %argv, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18, i1 %replaceUndef19, i1 %replaceUndef20, i1 %replaceUndef21, i1 %replaceUndef22, i1 %replaceUndef23, i1 %replaceUndef24, i1 %replaceUndef25, i1 %replaceUndef26, i1 %replaceUndef27, i1 %replaceUndef28, i1 %replaceUndef29, i1 %replaceUndef30, i1 %replaceUndef31, i1 %replaceUndef32, i1 %replaceUndef33, i1 %replaceUndef34, i1 %replaceUndef35, i1 %replaceUndef36, i1 %replaceUndef37, i1 %replaceUndef38, i1 %replaceUndef39, i1 %replaceUndef40, i1 %replaceUndef41, i1 %replaceUndef42, i1 %replaceUndef43, i1 %replaceUndef44, i1 %replaceUndef45, i1 %replaceUndef46, i1 %replaceUndef47, i1 %replaceUndef48, i1 %replaceUndef49, i1 %replaceUndef50, i1 %replaceUndef51, i1 %replaceUndef52, i1 %replaceUndef53, i1 %replaceUndef54, i1 %replaceUndef55) nounwind { entry: br label %bb6.i8 bb6.i8: ; preds = %memory_CalculateRealBlockSize1374.exit.i, %entry - br i1 undef, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9 + br i1 %replaceUndef0, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9 bb.i.i9: ; preds = %bb6.i8 br label %memory_CalculateRealBlockSize1374.exit.i @@ -34,40 +34,40 @@ %1 = urem i32 8184, %0 ; [#uses=1] %2 = sub i32 8188, %1 ; [#uses=1] store i32 %2, ptr undef, align 4 - br i1 undef, label %memory_Init.exit, label %bb6.i8 + br i1 %replaceUndef1, label %memory_Init.exit, label %bb6.i8 memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i br label %bb.i.i bb.i.i: ; preds = %bb.i.i, %memory_Init.exit - br i1 undef, label %symbol_Init.exit, label %bb.i.i + br i1 %replaceUndef2, label %symbol_Init.exit, label %bb.i.i symbol_Init.exit: ; preds = %bb.i.i br label %bb.i.i67 bb.i.i67: ; preds = %bb.i.i67, %symbol_Init.exit - br i1 undef, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67 + br i1 %replaceUndef3, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67 symbol_CreatePrecedence3522.exit: ; preds = %bb.i.i67 br label %bb.i.i8.i bb.i.i8.i: ; preds = %bb.i.i8.i, %symbol_CreatePrecedence3522.exit - br i1 undef, label %cont_Create.exit9.i, label %bb.i.i8.i + br i1 %replaceUndef4, label %cont_Create.exit9.i, label %bb.i.i8.i cont_Create.exit9.i: ; preds = %bb.i.i8.i br label %bb.i.i.i72 bb.i.i.i72: ; preds = %bb.i.i.i72, %cont_Create.exit9.i - br i1 undef, label %cont_Init.exit, label %bb.i.i.i72 + br i1 %replaceUndef5, label %cont_Init.exit, label %bb.i.i.i72 cont_Init.exit: ; preds = %bb.i.i.i72 br label %bb.i103 bb.i103: ; preds = %bb.i103, %cont_Init.exit - br i1 undef, label %subs_Init.exit, label %bb.i103 + br i1 %replaceUndef6, label %subs_Init.exit, label %bb.i103 subs_Init.exit: ; preds = %bb.i103 - br i1 undef, label %bb1.i.i.i80, label %cc_Init.exit + br i1 %replaceUndef7, label %bb1.i.i.i80, label %cc_Init.exit bb1.i.i.i80: ; preds = %subs_Init.exit unreachable @@ -76,22 +76,22 @@ br label %bb.i.i375 bb.i.i375: ; preds = %bb.i.i375, %cc_Init.exit - br i1 undef, label %bb.i439, label %bb.i.i375 + br i1 %replaceUndef8, label %bb.i439, label %bb.i.i375 bb.i439: ; preds = %bb.i439, %bb.i.i375 - br i1 undef, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439 + br i1 %replaceUndef9, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439 opts_DeclareSPASSFlagsAsOptions.exit: ; preds = %bb.i439 - br i1 undef, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82 + br i1 %replaceUndef10, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82 bb.i.i82: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit unreachable opts_TranslateShortOptDeclarations.exit.i: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit - br i1 undef, label %list_Length.exit.i.thread.i, label %bb.i.i4.i + br i1 %replaceUndef11, label %list_Length.exit.i.thread.i, label %bb.i.i4.i list_Length.exit.i.thread.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i - br i1 undef, label %bb18.i.i.i, label %bb26.i.i.i + br i1 %replaceUndef12, label %bb18.i.i.i, label %bb26.i.i.i bb.i.i4.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i unreachable @@ -100,7 +100,7 @@ unreachable bb26.i.i.i: ; preds = %list_Length.exit.i.thread.i - br i1 undef, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i + br i1 %replaceUndef13, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i opts_GetOptLongOnly.exit.thread97.i: ; preds = %bb26.i.i.i br label %bb27.i142 @@ -109,49 +109,49 @@ br label %bb1.i3.i bb1.i3.i: ; preds = %bb1.i3.i, %bb27.i142 - br i1 undef, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i + br i1 %replaceUndef14, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i opts_FreeLongOptsArray.exit.i: ; preds = %bb1.i3.i br label %bb.i443 bb.i443: ; preds = %bb.i443, %opts_FreeLongOptsArray.exit.i - br i1 undef, label %flag_InitStoreByDefaults3542.exit, label %bb.i443 + br i1 %replaceUndef15, label %flag_InitStoreByDefaults3542.exit, label %bb.i443 flag_InitStoreByDefaults3542.exit: ; preds = %bb.i443 - br i1 undef, label %bb6.i449, label %bb.i503 + br i1 %replaceUndef16, label %bb6.i449, label %bb.i503 bb6.i449: ; preds = %flag_InitStoreByDefaults3542.exit unreachable bb.i503: ; preds = %bb.i503, %flag_InitStoreByDefaults3542.exit - br i1 undef, label %flag_CleanStore3464.exit, label %bb.i503 + br i1 %replaceUndef17, label %flag_CleanStore3464.exit, label %bb.i503 flag_CleanStore3464.exit: ; preds = %bb.i503 - br i1 undef, label %bb1.i81.i.preheader, label %bb.i173 + br i1 %replaceUndef18, label %bb1.i81.i.preheader, label %bb.i173 bb.i173: ; preds = %flag_CleanStore3464.exit unreachable bb1.i81.i.preheader: ; preds = %flag_CleanStore3464.exit - br i1 undef, label %bb1.i64.i.preheader, label %bb5.i179 + br i1 %replaceUndef19, label %bb1.i64.i.preheader, label %bb5.i179 bb5.i179: ; preds = %bb1.i81.i.preheader unreachable bb1.i64.i.preheader: ; preds = %bb1.i81.i.preheader - br i1 undef, label %dfg_DeleteProofList.exit.i, label %bb.i9.i + br i1 %replaceUndef20, label %dfg_DeleteProofList.exit.i, label %bb.i9.i bb.i9.i: ; preds = %bb1.i64.i.preheader unreachable dfg_DeleteProofList.exit.i: ; preds = %bb1.i64.i.preheader - br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i + br i1 %replaceUndef21, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i bb.i.i62.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i - br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i + br i1 %replaceUndef22, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i term_DeleteTermList621.exit.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i - br i1 undef, label %dfg_DFGParser.exit, label %bb.i.i211 + br i1 %replaceUndef23, label %dfg_DFGParser.exit, label %bb.i.i211 bb.i.i211: ; preds = %term_DeleteTermList621.exit.i unreachable @@ -160,34 +160,34 @@ br label %bb.i513 bb.i513: ; preds = %bb2.i516, %dfg_DFGParser.exit - br i1 undef, label %bb2.i516, label %bb1.i514 + br i1 %replaceUndef24, label %bb2.i516, label %bb1.i514 bb1.i514: ; preds = %bb.i513 unreachable bb2.i516: ; preds = %bb.i513 - br i1 undef, label %bb.i509, label %bb.i513 + br i1 %replaceUndef25, label %bb.i509, label %bb.i513 bb.i509: ; preds = %bb.i509, %bb2.i516 - br i1 undef, label %symbol_TransferPrecedence3468.exit511, label %bb.i509 + br i1 %replaceUndef26, label %symbol_TransferPrecedence3468.exit511, label %bb.i509 symbol_TransferPrecedence3468.exit511: ; preds = %bb.i509 - br i1 undef, label %bb20, label %bb21 + br i1 %replaceUndef27, label %bb20, label %bb21 bb20: ; preds = %symbol_TransferPrecedence3468.exit511 unreachable bb21: ; preds = %symbol_TransferPrecedence3468.exit511 - br i1 undef, label %cnf_Init.exit, label %bb.i498 + br i1 %replaceUndef28, label %cnf_Init.exit, label %bb.i498 bb.i498: ; preds = %bb21 unreachable cnf_Init.exit: ; preds = %bb21 - br i1 undef, label %bb23, label %bb22 + br i1 %replaceUndef29, label %bb23, label %bb22 bb22: ; preds = %cnf_Init.exit - br i1 undef, label %bb2.i.i496, label %bb.i.i494 + br i1 %replaceUndef30, label %bb2.i.i496, label %bb.i.i494 bb.i.i494: ; preds = %bb22 unreachable @@ -196,49 +196,49 @@ unreachable bb23: ; preds = %cnf_Init.exit - br i1 undef, label %bb28, label %bb24 + br i1 %replaceUndef31, label %bb28, label %bb24 bb24: ; preds = %bb23 unreachable bb28: ; preds = %bb23 - br i1 undef, label %bb31, label %bb29 + br i1 %replaceUndef32, label %bb31, label %bb29 bb29: ; preds = %bb28 unreachable bb31: ; preds = %bb28 - br i1 undef, label %bb34, label %bb32 + br i1 %replaceUndef33, label %bb34, label %bb32 bb32: ; preds = %bb31 unreachable bb34: ; preds = %bb31 - br i1 undef, label %bb83, label %bb66 + br i1 %replaceUndef34, label %bb83, label %bb66 bb66: ; preds = %bb34 unreachable bb83: ; preds = %bb34 - br i1 undef, label %bb2.i1668, label %bb.i1667 + br i1 %replaceUndef35, label %bb2.i1668, label %bb.i1667 bb.i1667: ; preds = %bb83 unreachable bb2.i1668: ; preds = %bb83 - br i1 undef, label %bb5.i205, label %bb3.i204 + br i1 %replaceUndef36, label %bb5.i205, label %bb3.i204 bb3.i204: ; preds = %bb2.i1668 unreachable bb5.i205: ; preds = %bb2.i1668 - br i1 undef, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i + br i1 %replaceUndef37, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i bb.i206.i: ; preds = %bb5.i205 - br i1 undef, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i + br i1 %replaceUndef38, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i bb1.i207.i: ; preds = %bb.i206.i - br i1 undef, label %bb25.i1801.thread, label %bb.i1688 + br i1 %replaceUndef39, label %bb25.i1801.thread, label %bb.i1688 bb.i1688: ; preds = %bb1.i207.i unreachable @@ -247,10 +247,10 @@ unreachable ana_AnalyzeSortStructure.exit.i: ; preds = %bb.i206.i, %bb5.i205 - br i1 undef, label %bb7.i207, label %bb.i1806 + br i1 %replaceUndef40, label %bb7.i207, label %bb.i1806 bb.i1806: ; preds = %ana_AnalyzeSortStructure.exit.i - br i1 undef, label %bb2.i.i.i1811, label %bb.i.i.i1809 + br i1 %replaceUndef41, label %bb2.i.i.i1811, label %bb.i.i.i1809 bb.i.i.i1809: ; preds = %bb.i1806 unreachable @@ -259,58 +259,58 @@ unreachable bb7.i207: ; preds = %ana_AnalyzeSortStructure.exit.i - br i1 undef, label %bb9.i, label %bb8.i + br i1 %replaceUndef42, label %bb9.i, label %bb8.i bb8.i: ; preds = %bb7.i207 unreachable bb9.i: ; preds = %bb7.i207 - br i1 undef, label %bb23.i, label %bb26.i + br i1 %replaceUndef43, label %bb23.i, label %bb26.i bb23.i: ; preds = %bb9.i - br i1 undef, label %bb25.i, label %bb24.i + br i1 %replaceUndef44, label %bb25.i, label %bb24.i bb24.i: ; preds = %bb23.i - br i1 undef, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093 + br i1 %replaceUndef45, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093 bb.i2093: ; preds = %bb.i2093, %bb24.i br label %bb.i2093 sort_SortTheoryIsTrivial.exit.i: ; preds = %bb24.i - br i1 undef, label %bb3.i2141, label %bb4.i2143 + br i1 %replaceUndef46, label %bb3.i2141, label %bb4.i2143 bb3.i2141: ; preds = %sort_SortTheoryIsTrivial.exit.i unreachable bb4.i2143: ; preds = %sort_SortTheoryIsTrivial.exit.i - br i1 undef, label %bb8.i2178, label %bb5.i2144 + br i1 %replaceUndef47, label %bb8.i2178, label %bb5.i2144 bb5.i2144: ; preds = %bb4.i2143 - br i1 undef, label %bb7.i2177, label %bb1.i28.i + br i1 %replaceUndef48, label %bb7.i2177, label %bb1.i28.i bb1.i28.i: ; preds = %bb5.i2144 - br i1 undef, label %bb4.i43.i, label %bb2.i.i2153 + br i1 %replaceUndef49, label %bb4.i43.i, label %bb2.i.i2153 bb2.i.i2153: ; preds = %bb1.i28.i - br i1 undef, label %bb4.i.i33.i, label %bb.i.i30.i + br i1 %replaceUndef50, label %bb4.i.i33.i, label %bb.i.i30.i bb.i.i30.i: ; preds = %bb2.i.i2153 unreachable bb4.i.i33.i: ; preds = %bb2.i.i2153 - br i1 undef, label %bb9.i.i36.i, label %bb5.i.i34.i + br i1 %replaceUndef51, label %bb9.i.i36.i, label %bb5.i.i34.i bb5.i.i34.i: ; preds = %bb4.i.i33.i unreachable bb9.i.i36.i: ; preds = %bb4.i.i33.i - br i1 undef, label %bb14.i.i.i2163, label %bb10.i.i37.i + br i1 %replaceUndef52, label %bb14.i.i.i2163, label %bb10.i.i37.i bb10.i.i37.i: ; preds = %bb9.i.i36.i unreachable bb14.i.i.i2163: ; preds = %bb9.i.i36.i - br i1 undef, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164 + br i1 %replaceUndef53, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164 bb15.i.i.i2164: ; preds = %bb14.i.i.i2163 unreachable @@ -325,13 +325,13 @@ unreachable bb8.i2178: ; preds = %bb4.i2143 - br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader + br i1 %replaceUndef54, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader bb.i5.i2185.preheader: ; preds = %bb8.i2178 br label %bb.i5.i2185 bb.i5.i2185: ; preds = %bb.i5.i2185, %bb.i5.i2185.preheader - br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185 + br i1 %replaceUndef55, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185 sort_ApproxStaticSortTheory.exit: ; preds = %bb.i5.i2185, %bb8.i2178 br label %bb25.i diff --git a/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll @@ -1,21 +1,21 @@ ; RUN: llc < %s -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard ; PR4419 -define float @__ieee754_acosf(float %x) nounwind { +define float @__ieee754_acosf(float %x, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) nounwind { entry: - br i1 undef, label %bb, label %bb4 + br i1 %replaceUndef0, label %bb, label %bb4 bb: ; preds = %entry ret float undef bb4: ; preds = %entry - br i1 undef, label %bb5, label %bb6 + br i1 %replaceUndef1, label %bb5, label %bb6 bb5: ; preds = %bb4 ret float undef bb6: ; preds = %bb4 - br i1 undef, label %bb11, label %bb12 + br i1 %replaceUndef2, label %bb11, label %bb12 bb11: ; preds = %bb6 %0 = tail call float @__ieee754_sqrtf(float undef) nounwind ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll --- a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -3,7 +3,7 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define void @simplify_unary_real(ptr nocapture %p) nounwind { +define void @simplify_unary_real(ptr nocapture %p, i1 %replaceUndef0) nounwind { entry: %tmp121 = load i64, ptr null, align 4 ; [#uses=1] %0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] @@ -25,7 +25,7 @@ ret void bb21: ; preds = %entry - br i1 undef, label %bb82, label %bb29 + br i1 %replaceUndef0, label %bb82, label %bb29 bb29: ; preds = %bb21 %tmp18.i = and i192 %3, 1208907372870555465154560 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -12,24 +12,24 @@ declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %replaceUndef0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %replaceUndef2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %replaceUndef3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable @@ -55,67 +55,67 @@ %11 = sub i32 %10, %9 ; [#uses=1] %12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; [#uses=0] %13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] - br i1 undef, label %bb15, label %bb12 + br i1 %replaceUndef4, label %bb15, label %bb12 bb12: ; preds = %bb11 br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %replaceUndef5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %replaceUndef6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %replaceUndef7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %replaceUndef8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %replaceUndef9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i bb158.i: ; preds = %bb218.i, %bb.nph.i98 - br i1 undef, label %bb168.i, label %bb160.i + br i1 %replaceUndef10, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %replaceUndef11, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %replaceUndef12, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %replaceUndef13, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i - br i1 undef, label %bb211.i, label %bb218.i + br i1 %replaceUndef14, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %replaceUndef15, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - br i1 undef, label %bb221.i, label %bb228.i + br i1 %replaceUndef16, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %replaceUndef17, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %replaceUndef18, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -10,24 +10,24 @@ declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %replaceUndef0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %replaceUndef2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %replaceUndef3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable @@ -46,70 +46,70 @@ %6 = load i32, ptr @no_mis, align 4 ; [#uses=1] %7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; [#uses=0] %8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] - br i1 undef, label %bb15, label %bb12 + br i1 %replaceUndef4, label %bb15, label %bb12 bb12: ; preds = %bb11 br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %replaceUndef5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %replaceUndef6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %replaceUndef7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %replaceUndef8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %replaceUndef9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i bb158.i: ; preds = %bb218.i, %bb.nph.i98 - br i1 undef, label %bb168.i, label %bb160.i + br i1 %replaceUndef10, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %replaceUndef11, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %replaceUndef12, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %replaceUndef13, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i - br i1 undef, label %bb211.i, label %bb218.i + br i1 %replaceUndef14, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %replaceUndef15, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - br i1 undef, label %bb221.i, label %bb228.i + br i1 %replaceUndef16, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %replaceUndef17, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 %indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; [#uses=2] %tmp13 = add i32 %indvar11, 1 ; [#uses=2] %count.0 = sub i32 undef, %indvar11 ; [#uses=0] - br i1 undef, label %return, label %bb9 + br i1 %replaceUndef18, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -2,47 +2,47 @@ @JJ = external global ptr ; [#uses=1] -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %replaceUndef0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %replaceUndef2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %replaceUndef3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - br i1 undef, label %bb15, label %bb12 + br i1 %replaceUndef4, label %bb15, label %bb12 bb12: ; preds = %bb11 %0 = load ptr, ptr @JJ, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %replaceUndef5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i %cflag.0.i = phi i16 [ 0, %bb228.i ], [ 0, %bb74.i ], [ 1, %bb138.i ] ; [#uses=1] - br i1 undef, label %bb146.i, label %bb151.i + br i1 %replaceUndef6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %replaceUndef7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i %.not297 = icmp ne i16 %cflag.0.i, 0 ; [#uses=1] @@ -50,7 +50,7 @@ br i1 %or.cond298, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %replaceUndef8, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -65,13 +65,13 @@ %i.121.i = sub i32 undef, undef ; [#uses=3] %tmp105.i = sub i32 undef, undef ; [#uses=1] %1 = sub i32 %c.1020.i, undef ; [#uses=0] - br i1 undef, label %bb168.i, label %bb160.i + br i1 %replaceUndef9, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %replaceUndef10, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %replaceUndef11, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i %2 = icmp slt i32 %fj.515.i, undef ; [#uses=1] @@ -100,7 +100,7 @@ store i32 %ci.12.i, ptr %scevgep88.i, align 4 store i32 %cj.11.i100, ptr %scevgep89.i, align 4 store i32 %4, ptr undef, align 4 - br i1 undef, label %bb211.i, label %bb218.i + br i1 %replaceUndef12, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i @@ -112,16 +112,16 @@ bb220.i: ; preds = %bb218.i, %bb153.i %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; [#uses=0] - br i1 undef, label %bb221.i, label %bb228.i + br i1 %replaceUndef13, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %replaceUndef14, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %replaceUndef15, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -8,25 +8,25 @@ declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %replaceUndef0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %replaceUndef2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 %0 = load ptr, ptr @name1, align 4 ; [#uses=0] br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %replaceUndef3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable @@ -36,7 +36,7 @@ %1 = getelementptr i8, ptr %A, i32 0 ; [#uses=1] %2 = getelementptr i8, ptr %B, i32 0 ; [#uses=1] tail call void @diff(ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind - br i1 undef, label %bb15, label %bb12 + br i1 %replaceUndef4, label %bb15, label %bb12 bb12: ; preds = %bb11 %3 = load ptr, ptr @II, align 4 ; [#uses=1] @@ -45,23 +45,23 @@ br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %replaceUndef5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %replaceUndef6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %replaceUndef7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %replaceUndef8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i %6 = add i32 undef, -1 ; [#uses=3] - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %replaceUndef9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -80,13 +80,13 @@ br i1 %9, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %replaceUndef10, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %replaceUndef11, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %replaceUndef12, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i @@ -101,27 +101,27 @@ %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] %10 = load i32, ptr %scevgep88.i, align 4 ; [#uses=1] - br i1 undef, label %bb211.i, label %bb218.i + br i1 %replaceUndef13, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %replaceUndef14, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i %11 = getelementptr i32, ptr null, i32 %6 ; [#uses=1] store i32 undef, ptr %11, align 4 - br i1 undef, label %bb221.i, label %bb228.i + br i1 %replaceUndef15, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %replaceUndef16, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %replaceUndef17, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -2,52 +2,52 @@ @XX = external global ptr ; [#uses=1] -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13, i1 %replaceUndef14, i1 %replaceUndef15, i1 %replaceUndef16, i1 %replaceUndef17, i1 %replaceUndef18) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %replaceUndef0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %replaceUndef2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %replaceUndef3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - br i1 undef, label %bb15, label %bb12 + br i1 %replaceUndef4, label %bb15, label %bb12 bb12: ; preds = %bb11 %0 = load ptr, ptr @XX, align 4 ; [#uses=0] br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %replaceUndef5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i - br i1 undef, label %bb146.i, label %bb151.i + br i1 %replaceUndef6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %replaceUndef7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i - br i1 undef, label %bb153.i, label %bb228.i + br i1 %replaceUndef8, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %replaceUndef9, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -55,16 +55,16 @@ bb158.i: ; preds = %bb218.i, %bb.nph.i98 %1 = sub i32 undef, undef ; [#uses=4] %2 = sub i32 undef, undef ; [#uses=1] - br i1 undef, label %bb168.i, label %bb160.i + br i1 %replaceUndef10, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %replaceUndef11, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %replaceUndef12, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %replaceUndef13, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i @@ -74,25 +74,25 @@ %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] store i32 %c.14.i, ptr undef, align 4 store i32 undef, ptr null, align 4 - br i1 undef, label %bb211.i, label %bb218.i + br i1 %replaceUndef14, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i bb218.i: ; preds = %bb211.i, %bb168.i - br i1 undef, label %bb220.i, label %bb158.i + br i1 %replaceUndef15, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - br i1 undef, label %bb221.i, label %bb228.i + br i1 %replaceUndef16, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 - br i1 undef, label %bb74.i, label %bb145.i + br i1 %replaceUndef17, label %bb74.i, label %bb145.i bb15: ; preds = %bb11, %bb8 - br i1 undef, label %return, label %bb9 + br i1 %replaceUndef18, label %return, label %bb9 return: ; preds = %bb15 ret void diff --git a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll --- a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -4,30 +4,30 @@ @II = external global ptr ; [#uses=1] @JJ = external global ptr ; [#uses=1] -define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12, i1 %replaceUndef13) nounwind { entry: - br i1 undef, label %bb5, label %bb + br i1 %replaceUndef0, label %bb5, label %bb bb: ; preds = %bb, %entry br label %bb bb5: ; preds = %entry - br i1 undef, label %bb6, label %bb8 + br i1 %replaceUndef1, label %bb6, label %bb8 bb6: ; preds = %bb6, %bb5 - br i1 undef, label %bb8, label %bb6 + br i1 %replaceUndef2, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 br label %bb15 bb9: ; preds = %bb15 - br i1 undef, label %bb10, label %bb11 + br i1 %replaceUndef3, label %bb10, label %bb11 bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - br i1 undef, label %bb15, label %bb12 + br i1 %replaceUndef4, label %bb15, label %bb12 bb12: ; preds = %bb11 %0 = load ptr, ptr @II, align 4 ; [#uses=1] @@ -36,17 +36,17 @@ br label %bb228.i bb74.i: ; preds = %bb228.i - br i1 undef, label %bb138.i, label %bb145.i + br i1 %replaceUndef5, label %bb138.i, label %bb145.i bb138.i: ; preds = %bb74.i br label %bb145.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i %cflag.0.i = phi i16 [ %cflag.1.i, %bb228.i ], [ %cflag.1.i, %bb74.i ], [ 1, %bb138.i ] ; [#uses=2] - br i1 undef, label %bb146.i, label %bb151.i + br i1 %replaceUndef6, label %bb146.i, label %bb151.i bb146.i: ; preds = %bb145.i - br i1 undef, label %bb228.i, label %bb151.i + br i1 %replaceUndef7, label %bb228.i, label %bb151.i bb151.i: ; preds = %bb146.i, %bb145.i %.not297 = icmp ne i16 %cflag.0.i, 0 ; [#uses=1] @@ -54,7 +54,7 @@ br i1 %or.cond298, label %bb153.i, label %bb228.i bb153.i: ; preds = %bb151.i - br i1 undef, label %bb220.i, label %bb.nph.i98 + br i1 %replaceUndef8, label %bb220.i, label %bb.nph.i98 bb.nph.i98: ; preds = %bb153.i br label %bb158.i @@ -75,13 +75,13 @@ br i1 %5, label %bb168.i, label %bb160.i bb160.i: ; preds = %bb158.i - br i1 undef, label %bb161.i, label %bb168.i + br i1 %replaceUndef9, label %bb161.i, label %bb168.i bb161.i: ; preds = %bb160.i - br i1 undef, label %bb168.i, label %bb163.i + br i1 %replaceUndef10, label %bb168.i, label %bb163.i bb163.i: ; preds = %bb161.i - br i1 undef, label %bb167.i, label %bb168.i + br i1 %replaceUndef11, label %bb167.i, label %bb168.i bb167.i: ; preds = %bb163.i br label %bb168.i @@ -101,7 +101,7 @@ %7 = load i32, ptr %scevgep89.i, align 4 ; [#uses=1] store i32 %ci.12.i, ptr %scevgep88.i, align 4 store i32 %cj.11.i100, ptr %scevgep89.i, align 4 - br i1 undef, label %bb211.i, label %bb218.i + br i1 %replaceUndef12, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i br label %bb218.i @@ -113,7 +113,7 @@ bb220.i: ; preds = %bb218.i, %bb153.i %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; [#uses=2] - br i1 undef, label %bb221.i, label %bb228.i + br i1 %replaceUndef13, label %bb221.i, label %bb228.i bb221.i: ; preds = %bb220.i br label %bb228.i diff --git a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -8,34 +8,34 @@ declare i32 @strlen(ptr nocapture) nounwind readonly -define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11, i1 %replaceUndef12) nounwind { entry: - br i1 undef, label %bb126, label %bb1 + br i1 %replaceUndef0, label %bb126, label %bb1 bb1: ; preds = %entry - br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit + br i1 %replaceUndef1, label %cli_calloc.exit.thread, label %cli_calloc.exit cli_calloc.exit.thread: ; preds = %bb1 ret i32 -114 cli_calloc.exit: ; preds = %bb1 store i16 %parts, ptr undef, align 4 - br i1 undef, label %bb52, label %bb4 + br i1 %replaceUndef2, label %bb52, label %bb4 bb4: ; preds = %cli_calloc.exit - br i1 undef, label %bb.i, label %bb1.i3 + br i1 %replaceUndef3, label %bb.i, label %bb1.i3 bb.i: ; preds = %bb4 unreachable bb1.i3: ; preds = %bb4 - br i1 undef, label %bb2.i4, label %cli_strdup.exit + br i1 %replaceUndef4, label %bb2.i4, label %cli_strdup.exit bb2.i4: ; preds = %bb1.i3 ret i32 -114 cli_strdup.exit: ; preds = %bb1.i3 - br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 + br i1 %replaceUndef5, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 cli_calloc.exit54.thread: ; preds = %cli_strdup.exit ret i32 -114 @@ -47,31 +47,31 @@ unreachable cli_calloc.exit70: ; preds = %bb45 - br i1 undef, label %bb.i83, label %bb1.i84 + br i1 %replaceUndef6, label %bb.i83, label %bb1.i84 bb.i83: ; preds = %cli_calloc.exit70 unreachable bb1.i84: ; preds = %cli_calloc.exit70 - br i1 undef, label %bb2.i85, label %bb17 + br i1 %replaceUndef7, label %bb2.i85, label %bb17 bb2.i85: ; preds = %bb1.i84 unreachable bb17: ; preds = %bb1.i84 - br i1 undef, label %bb22, label %bb.nph + br i1 %replaceUndef8, label %bb22, label %bb.nph bb.nph: ; preds = %bb17 br label %bb18 bb18: ; preds = %bb18, %bb.nph - br i1 undef, label %bb18, label %bb22 + br i1 %replaceUndef9, label %bb18, label %bb22 bb22: ; preds = %bb18, %bb17 - br i1 undef, label %bb25, label %bb43.preheader + br i1 %replaceUndef10, label %bb25, label %bb43.preheader bb43.preheader: ; preds = %bb22 - br i1 undef, label %bb28, label %bb45 + br i1 %replaceUndef11, label %bb28, label %bb45 bb25: ; preds = %bb22 unreachable @@ -80,7 +80,7 @@ unreachable bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 - br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 + br i1 %replaceUndef12, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit %0 = load i16, ptr undef, align 4 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -6,33 +6,33 @@ %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 } %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 } -define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8, i1 %replaceUndef9, i1 %replaceUndef10, i1 %replaceUndef11) nounwind { entry: - br i1 undef, label %bb126, label %bb1 + br i1 %replaceUndef0, label %bb126, label %bb1 bb1: ; preds = %entry - br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit + br i1 %replaceUndef1, label %cli_calloc.exit.thread, label %cli_calloc.exit cli_calloc.exit.thread: ; preds = %bb1 ret i32 -114 cli_calloc.exit: ; preds = %bb1 - br i1 undef, label %bb52, label %bb4 + br i1 %replaceUndef2, label %bb52, label %bb4 bb4: ; preds = %cli_calloc.exit - br i1 undef, label %bb.i, label %bb1.i3 + br i1 %replaceUndef3, label %bb.i, label %bb1.i3 bb.i: ; preds = %bb4 unreachable bb1.i3: ; preds = %bb4 - br i1 undef, label %bb2.i4, label %cli_strdup.exit + br i1 %replaceUndef4, label %bb2.i4, label %cli_strdup.exit bb2.i4: ; preds = %bb1.i3 ret i32 -114 cli_strdup.exit: ; preds = %bb1.i3 - br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 + br i1 %replaceUndef5, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 cli_calloc.exit54.thread: ; preds = %cli_strdup.exit ret i32 -114 @@ -44,25 +44,25 @@ unreachable cli_calloc.exit70: ; preds = %bb45 - br i1 undef, label %bb.i83, label %bb1.i84 + br i1 %replaceUndef6, label %bb.i83, label %bb1.i84 bb.i83: ; preds = %cli_calloc.exit70 unreachable bb1.i84: ; preds = %cli_calloc.exit70 - br i1 undef, label %bb2.i85, label %bb17 + br i1 %replaceUndef7, label %bb2.i85, label %bb17 bb2.i85: ; preds = %bb1.i84 unreachable bb17: ; preds = %bb1.i84 - br i1 undef, label %bb22, label %bb.nph + br i1 %replaceUndef8, label %bb22, label %bb.nph bb.nph: ; preds = %bb17 br label %bb18 bb18: ; preds = %bb18, %bb.nph - br i1 undef, label %bb18, label %bb22 + br i1 %replaceUndef9, label %bb18, label %bb22 bb22: ; preds = %bb18, %bb17 %0 = getelementptr i8, ptr null, i32 10 ; [#uses=1] @@ -75,7 +75,7 @@ br i1 %6, label %bb25, label %bb43.preheader bb43.preheader: ; preds = %bb22 - br i1 undef, label %bb28, label %bb45 + br i1 %replaceUndef10, label %bb28, label %bb45 bb25: ; preds = %bb22 unreachable @@ -84,7 +84,7 @@ unreachable bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 - br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 + br i1 %replaceUndef11, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit unreachable diff --git a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll --- a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -4,17 +4,17 @@ declare double @llvm.exp.f64(double) nounwind readonly -define void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind { +define void @findratio(ptr nocapture %res1, ptr nocapture %res2, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) nounwind { entry: br label %bb bb: ; preds = %bb, %entry - br i1 undef, label %bb28, label %bb + br i1 %replaceUndef0, label %bb28, label %bb bb28: ; preds = %bb %0 = load double, ptr @a, align 4 ; [#uses=2] %1 = fadd double %0, undef ; [#uses=2] - br i1 undef, label %bb59, label %bb60 + br i1 %replaceUndef1, label %bb59, label %bb60 bb59: ; preds = %bb28 %2 = fsub double -0.000000e+00, undef ; [#uses=2] @@ -94,7 +94,7 @@ %.pn2 = fadd double %.pn6, %.pn7 ; [#uses=1] %N1.0 = fsub double %.pn4, undef ; [#uses=1] %D1.0 = fsub double %.pn2, undef ; [#uses=2] - br i1 undef, label %bb62, label %bb64 + br i1 %replaceUndef2, label %bb62, label %bb64 bb62: ; preds = %bb61 %7 = fadd double %D1.0, undef ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll --- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll +++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll @@ -4,9 +4,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-elf" -define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) nounwind optsize { entry: - br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i + br i1 %replaceUndef0, label %fault_in_pages_writeable.exit, label %bb5.i bb5.i: ; preds = %entry %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; [#uses=1] @@ -14,13 +14,13 @@ br i1 %0, label %bb6.i, label %fault_in_pages_writeable.exit bb6.i: ; preds = %bb5.i - br i1 undef, label %fault_in_pages_writeable.exit, label %bb7.i + br i1 %replaceUndef1, label %fault_in_pages_writeable.exit, label %bb7.i bb7.i: ; preds = %bb6.i unreachable fault_in_pages_writeable.exit: ; preds = %bb6.i, %bb5.i, %entry - br i1 undef, label %bb2, label %bb3 + br i1 %replaceUndef2, label %bb2, label %bb3 bb2: ; preds = %fault_in_pages_writeable.exit unreachable diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 -define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size, i1 %replaceUndef0) nounwind optsize { entry: - br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i + br i1 %replaceUndef0, label %fault_in_pages_writeable.exit, label %bb5.i bb5.i: ; preds = %entry %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll --- a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -6,12 +6,12 @@ %struct.device_dma_parameters = type { i32, i32 } %struct.iovec = type { ptr, i32 } -define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags) nounwind optsize { +define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags, i1 %replaceUndef0, i1 %replaceUndef1) nounwind optsize { entry: br label %bb8 bb: ; preds = %bb8 - br i1 undef, label %bb10, label %bb2 + br i1 %replaceUndef0, label %bb10, label %bb2 bb2: ; preds = %bb %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1] @@ -20,7 +20,7 @@ br i1 %0, label %bb7, label %bb4 bb4: ; preds = %bb2 - br i1 undef, label %bb10, label %bb9 + br i1 %replaceUndef1, label %bb10, label %bb9 bb7: ; preds = %bb2 %1 = add i32 %2, 1 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -7,10 +7,10 @@ %struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr } @g = common global ptr null -define ptr @tsp(ptr %t, i32 %nproc) nounwind { +define ptr @tsp(ptr %t, i32 %nproc, i1 %replaceUndef0, i1 %replaceUndef1) nounwind { entry: %t.idx51.val.i = load double, ptr null ; [#uses=1] - br i1 undef, label %bb4.i, label %bb.i + br i1 %replaceUndef0, label %bb4.i, label %bb.i bb.i: ; preds = %entry unreachable @@ -27,7 +27,7 @@ %4 = fmul double %3, %3 ; [#uses=1] %5 = fadd double %2, %4 ; [#uses=1] %6 = tail call double @llvm.sqrt.f64(double %5) nounwind ; [#uses=1] - br i1 undef, label %bb7.i4, label %bb6.i + br i1 %replaceUndef1, label %bb7.i4, label %bb6.i bb6.i: ; preds = %bb4.i br label %bb7.i4 diff --git a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll --- a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll +++ b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll @@ -9,9 +9,9 @@ %quux = type { ptr, ptr, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define void @aaaa(ptr %this, ptr %block) { +define void @aaaa(ptr %this, ptr %block, i1 %replaceUndef0, i1 %replaceUndef1) { entry: - br i1 undef, label %bb.nph269, label %bb201 + br i1 %replaceUndef0, label %bb.nph269, label %bb201 bb.nph269: br label %bb12 @@ -21,7 +21,7 @@ %1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> zeroinitializer %3 = fadd <4 x float> undef, %2 - br i1 undef, label %bb194, label %bb186 + br i1 %replaceUndef1, label %bb194, label %bb186 bb186: br label %bb194 diff --git a/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll --- a/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll +++ b/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define void @foo() nounwind { +define void @foo( i1 %replaceUndef0) nounwind { entry: %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; [#uses=1] @@ -13,7 +13,7 @@ unreachable bb7: ; preds = %entry - br i1 undef, label %bb8, label %bb9 + br i1 %replaceUndef0, label %bb8, label %bb9 bb8: ; preds = %bb7 unreachable diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll @@ -11,7 +11,7 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone -define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind { +define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box, i1 %replaceUndef0) nounwind { entry: %val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1] %val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1] @@ -51,7 +51,7 @@ br i1 %26, label %bb41, label %bb33 bb33: ; preds = %bb, %entry - br i1 undef, label %bb34, label %bb + br i1 %replaceUndef0, label %bb34, label %bb bb34: ; preds = %bb33 ret i8 undef diff --git a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll --- a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll @@ -2,9 +2,9 @@ ; PR4986 -define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems, i1 %replaceUndef0, i1 %replaceUndef1) nounwind { entry: - br i1 undef, label %return, label %bb.preheader + br i1 %replaceUndef0, label %return, label %bb.preheader bb.preheader: ; preds = %entry br label %bb @@ -17,7 +17,7 @@ %4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1] %5 = extractelement <4 x float> %4, i32 3 ; [#uses=1] store float %5, ptr undef, align 4 - br i1 undef, label %return, label %bb + br i1 %replaceUndef1, label %return, label %bb return: ; preds = %bb, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll --- a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll @@ -9,9 +9,9 @@ declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind -define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems, i1 %replaceUndef0) nounwind { entry: - br i1 undef, label %return, label %bb.nph + br i1 %replaceUndef0, label %return, label %bb.nph bb.nph: ; preds = %entry %0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll --- a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s ; PR5367 -define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems, i1 %replaceUndef0, i1 %replaceUndef1) nounwind { entry: - br i1 undef, label %return, label %bb + br i1 %replaceUndef0, label %return, label %bb bb: ; preds = %bb, %entry %0 = load float, ptr undef, align 4 ; [#uses=1] @@ -54,7 +54,7 @@ store float 0.000000e+00, ptr null, align 4 %44 = extractelement <4 x float> %43, i32 1 ; [#uses=1] store float %44, ptr undef, align 4 - br i1 undef, label %return, label %bb + br i1 %replaceUndef1, label %return, label %bb return: ; preds = %bb, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll --- a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -2,9 +2,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" -define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { +define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems, i1 %replaceUndef0, i1 %replaceUndef1) nounwind { entry: - br i1 undef, label %return, label %bb + br i1 %replaceUndef0, label %return, label %bb bb: ; preds = %bb, %entry ; CHECK: vld1.16 {d16[], d17[]} @@ -14,7 +14,7 @@ %3 = mul <8 x i16> %2, %2 %4 = extractelement <8 x i16> %3, i32 2 store i16 %4, ptr undef, align 2 - br i1 undef, label %return, label %bb + br i1 %replaceUndef1, label %return, label %bb return: ; preds = %bb, %entry ret void diff --git a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll @@ -5,9 +5,9 @@ %pln = type { %vec, float } %vec = type { [4 x float] } -define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint) { +define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint, i1 %replaceUndef0) { entry: - br i1 undef, label %bb81, label %bb48 + br i1 %replaceUndef0, label %bb81, label %bb48 bb48: ; preds = %entry %0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll @@ -8,9 +8,9 @@ %quux = type { %quad, %quad } %quuz = type { [4 x ptr], [4 x float], i32 } -define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %replaceUndef0) { entry: - br i1 undef, label %bb85, label %bb + br i1 %replaceUndef0, label %bb85, label %bb bb: ; preds = %entry %0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; [#uses=2] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll @@ -8,12 +8,12 @@ %quux = type { [4 x ptr], [4 x float], i32 } %quuz = type { %quad, %quad } -define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %replaceUndef0, i1 %replaceUndef1) { entry: - br i1 undef, label %bb85, label %bb + br i1 %replaceUndef0, label %bb85, label %bb bb: ; preds = %entry - br i1 undef, label %bb3.i, label %bb2.i + br i1 %replaceUndef1, label %bb3.i, label %bb2.i bb2.i: ; preds = %bb br label %bb3.i diff --git a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll --- a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll @@ -9,13 +9,13 @@ %quux = type { [4 x ptr], [4 x float], i32 } %quuz = type { %quad, %quad } -define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { +define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %replaceUndef0) { entry: %0 = load ptr, ptr undef, align 4 ; [#uses=2] br i1 false, label %bb85, label %bb bb: ; preds = %entry - br i1 undef, label %bb3.i, label %bb2.i + br i1 %replaceUndef0, label %bb3.i, label %bb2.i bb2.i: ; preds = %bb br label %bb3.i diff --git a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll --- a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { +define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4) { %1 = load i32, ptr undef ; [#uses=1] %2 = sub i32 %1, 48 ; [#uses=1] - br i1 undef, label %stack_overflow, label %no_overflow + br i1 %replaceUndef0, label %stack_overflow, label %no_overflow stack_overflow: ; preds = %0 unreachable @@ -16,13 +16,13 @@ %6 = load ptr, ptr %5 ; [#uses=1] %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; [#uses=1] %8 = load i32, ptr %7 ; [#uses=1] - br i1 undef, label %bci_13, label %bci_4 + br i1 %replaceUndef1, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow - br i1 undef, label %bci_30, label %bci_21 + br i1 %replaceUndef2, label %bci_30, label %bci_21 bci_30: ; preds = %bci_13 - br i1 undef, label %bci_46, label %bci_35 + br i1 %replaceUndef3, label %bci_46, label %bci_35 bci_46: ; preds = %bci_30 %9 = sub i32 %4, %3 ; [#uses=1] @@ -42,7 +42,7 @@ store i32 %16, ptr undef store ptr %6, ptr undef call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread) - br i1 undef, label %no_exception, label %exception + br i1 %replaceUndef4, label %no_exception, label %exception exception: ; preds = %bci_46 ret void diff --git a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll --- a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=arm-eabi %s -o /dev/null -define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { +define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) { %1 = sub i32 undef, 48 ; [#uses=1] - br i1 undef, label %stack_overflow, label %no_overflow + br i1 %replaceUndef0, label %stack_overflow, label %no_overflow stack_overflow: ; preds = %0 unreachable @@ -13,10 +13,10 @@ %3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; [#uses=1] %4 = load i32, ptr %3 ; [#uses=2] %5 = load ptr, ptr undef ; [#uses=2] - br i1 undef, label %bci_13, label %bci_4 + br i1 %replaceUndef1, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow - br i1 undef, label %bci_30, label %bci_21 + br i1 %replaceUndef2, label %bci_30, label %bci_21 bci_30: ; preds = %bci_13 %6 = icmp sle i32 %2, %4 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll --- a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values. -define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction, i1 %replaceUndef0) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] @@ -12,7 +12,7 @@ %5 = fadd <4 x float> undef, %4 ; <<4 x float>> [#uses=1] %6 = fadd <4 x float> undef, %5 ; <<4 x float>> [#uses=1] %7 = fadd <4 x float> undef, %6 ; <<4 x float>> [#uses=1] - br i1 undef, label %bb4, label %bb3 + br i1 %replaceUndef0, label %bb4, label %bb3 bb3: ; preds = %entry %8 = shufflevector <4 x float> undef, <4 x float> %7, <4 x i32> ; <<4 x float>> [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll --- a/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll +++ b/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=arm1136jf-s %s -o /dev/null ; Radar 7854640 -define void @test() nounwind { +define void @test( i1 %replaceUndef0) nounwind { bb: - br i1 undef, label %bb9, label %bb10 + br i1 %replaceUndef0, label %bb9, label %bb10 bb9: %tmp63 = bitcast <4 x float> zeroinitializer to i128 diff --git a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll --- a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll @@ -14,7 +14,7 @@ declare fastcc i32 @FirstOne() -define fastcc void @Evaluate() { +define fastcc void @Evaluate( i1 %replaceUndef0) { entry: br i1 false, label %cond_false186, label %cond_true @@ -94,7 +94,7 @@ %tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1] %tmp1599 = load i32, ptr %tmp1598 ; [#uses=1] %tmp1602 = sub i32 0, %tmp1599 ; [#uses=1] - br i1 undef, label %cond_next1637, label %cond_true1607 + br i1 %replaceUndef0, label %cond_next1637, label %cond_true1607 cond_true1607: ; preds = %bb1567 ret void diff --git a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll --- a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -10,7 +10,7 @@ @.str = external constant [1 x i8] ; [#uses=1] -define void @yy(ptr %qq) nounwind { +define void @yy(ptr %qq, i1 %replaceUndef0) nounwind { entry: %vla6 = alloca i8, i32 undef, align 1 ; [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; [#uses=1] @@ -20,7 +20,7 @@ %0 = mul i32 1, %tmp21 ; [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] call void (...) @zz(ptr @.str, i32 2, i32 1) - br i1 undef, label %if.then, label %if.end36 + br i1 %replaceUndef0, label %if.then, label %if.end36 if.then: ; preds = %entry %call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll --- a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -10,7 +10,7 @@ @.str2708 = external constant [14 x i8], align 4 ; [#uses=1] -define void @TW_oldinput(ptr nocapture %fp) nounwind { +define void @TW_oldinput(ptr nocapture %fp, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) nounwind { entry: %xcenter = alloca i32, align 4 ; [#uses=2] %0 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; [#uses=1] @@ -26,7 +26,7 @@ br i1 %5, label %bb10, label %bb445 bb10: ; preds = %bb - br i1 undef, label %bb11, label %bb445 + br i1 %replaceUndef0, label %bb11, label %bb445 bb11: ; preds = %bb10 %6 = load ptr, ptr undef, align 4 ; [#uses=3] @@ -48,7 +48,7 @@ %15 = fptosi double %14 to i32 ; [#uses=1] %iftmp.41.0.in = add i32 0, %15 ; [#uses=1] %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; [#uses=3] - br i1 undef, label %bb43.loopexit, label %bb21 + br i1 %replaceUndef1, label %bb43.loopexit, label %bb21 bb21: ; preds = %bb13 %16 = fptosi double undef to i32 ; [#uses=1] @@ -98,7 +98,7 @@ br i1 %43, label %bb52.loopexit, label %bb36 bb43.loopexit: ; preds = %bb21, %bb13 - br i1 undef, label %bb52.loopexit, label %bb36 + br i1 %replaceUndef2, label %bb52.loopexit, label %bb36 bb52.loopexit: ; preds = %bb43.loopexit, %bb36 %44 = icmp eq i32 %4, 0 ; [#uses=1] @@ -134,7 +134,7 @@ unreachable bb322: ; preds = %bb248 - br i1 undef, label %bb248, label %bb445 + br i1 %replaceUndef3, label %bb248, label %bb445 bb445: ; preds = %bb322, %bb10, %bb %49 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll --- a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll +++ b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll @@ -2,9 +2,9 @@ declare noalias ptr @malloc(i32) nounwind -define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels) nounwind { +define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7) nounwind { entry: - br i1 undef, label %bb3.i, label %bb3 + br i1 %replaceUndef0, label %bb3.i, label %bb3 bb3.i: ; preds = %entry unreachable @@ -19,7 +19,7 @@ br label %bb5 bb5: ; preds = %bb4, %bb3 - br i1 undef, label %bb19, label %bb22 + br i1 %replaceUndef1, label %bb19, label %bb22 bb19: ; preds = %bb5 switch i32 %type, label %bb3.i6.i [ @@ -35,13 +35,13 @@ unreachable bb1.i13: ; preds = %bb9.i.i6, %bb19, %bb19 - br i1 undef, label %bb3.i17, label %bb2.i16 + br i1 %replaceUndef2, label %bb3.i17, label %bb2.i16 bb2.i16: ; preds = %bb1.i13 unreachable bb3.i17: ; preds = %bb1.i13 - br i1 undef, label %bb4.i18, label %bb23.i + br i1 %replaceUndef3, label %bb4.i18, label %bb23.i bb4.i18: ; preds = %bb3.i17 %0 = mul nsw i32 %height, %width @@ -50,13 +50,13 @@ %2 = zext i1 %not..i to i32 %storemerge2.i = add i32 0, %2 %3 = call noalias ptr @malloc(i32 %storemerge2.i) nounwind - br i1 undef, label %bb3.i9, label %bb9.i + br i1 %replaceUndef4, label %bb3.i9, label %bb9.i bb9.i: ; preds = %bb4.i18 - br i1 undef, label %bb13.i19, label %bb.i24.i + br i1 %replaceUndef5, label %bb13.i19, label %bb.i24.i bb13.i19: ; preds = %bb9.i - br i1 undef, label %bb14.i20, label %bb15.i + br i1 %replaceUndef6, label %bb14.i20, label %bb15.i bb14.i20: ; preds = %bb13.i19 unreachable @@ -77,7 +77,7 @@ unreachable bb22: ; preds = %bb.i24.i, %bb5 - br i1 undef, label %gl_error.exit, label %bb23 + br i1 %replaceUndef7, label %gl_error.exit, label %bb23 bb23: ; preds = %bb22 ret void diff --git a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll --- a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -13,24 +13,24 @@ %0 = type { i32, i32 } -define void @foo(ptr %in) nounwind { +define void @foo(ptr %in, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) nounwind { entry: br label %bb.i bb.i: ; preds = %bb.i, %entry - br i1 undef, label %bb10.preheader.i, label %bb.i + br i1 %replaceUndef0, label %bb10.preheader.i, label %bb.i bb10.preheader.i: ; preds = %bb.i br label %bb10.i bb10.i: ; preds = %bb10.i, %bb10.preheader.i - br i1 undef, label %bb27.i, label %bb10.i + br i1 %replaceUndef1, label %bb27.i, label %bb10.i bb27.i: ; preds = %bb10.i br label %bb28.i bb28.i: ; preds = %bb28.i, %bb27.i - br i1 undef, label %presymmetry.exit, label %bb28.i + br i1 %replaceUndef2, label %presymmetry.exit, label %bb28.i presymmetry.exit: ; preds = %bb28.i %tmp175387 = or i32 undef, 12 diff --git a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll --- a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll +++ b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll @@ -6,13 +6,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" target triple = "armv5e-none-linux-gnueabi" -define hidden fastcc void @storeAtts() nounwind { +define hidden fastcc void @storeAtts( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3, i1 %replaceUndef4, i1 %replaceUndef5, i1 %replaceUndef6, i1 %replaceUndef7, i1 %replaceUndef8) nounwind { entry: %.SV116 = alloca ptr - br i1 undef, label %meshBB520, label %meshBB464 + br i1 %replaceUndef0, label %meshBB520, label %meshBB464 bb15: ; preds = %meshBB424 - br i1 undef, label %bb216, label %meshBB396 + br i1 %replaceUndef1, label %bb216, label %meshBB396 bb22: ; preds = %meshBB396 br label %cBB564 @@ -27,13 +27,13 @@ unreachable bb129: ; preds = %meshBB540 - br i1 undef, label %bb131.loopexit, label %meshBB540 + br i1 %replaceUndef2, label %bb131.loopexit, label %meshBB540 bb131.loopexit: ; preds = %bb129 br label %bb131 bb131: ; preds = %bb135, %bb131.loopexit - br i1 undef, label %bb134, label %meshBB396 + br i1 %replaceUndef3, label %bb134, label %meshBB396 bb134: ; preds = %bb131 unreachable @@ -64,16 +64,16 @@ ret void meshBB396: ; preds = %bb131, %bb15 - br i1 undef, label %bb135, label %bb22 + br i1 %replaceUndef4, label %bb135, label %bb22 meshBB412: ; preds = %meshBB464 - br i1 undef, label %meshBB504, label %bb78 + br i1 %replaceUndef5, label %meshBB504, label %bb78 meshBB424: ; preds = %meshBB464 - br i1 undef, label %poolStoreString.exit.thread, label %bb15 + br i1 %replaceUndef6, label %poolStoreString.exit.thread, label %bb15 meshBB464: ; preds = %entry - br i1 undef, label %meshBB424, label %meshBB412 + br i1 %replaceUndef7, label %meshBB424, label %meshBB412 meshBB472: ; preds = %meshBB504, %bb135 unreachable @@ -85,5 +85,5 @@ br label %meshBB540 meshBB540: ; preds = %meshBB520, %bb129 - br i1 undef, label %bb212, label %bb129 + br i1 %replaceUndef8, label %bb212, label %bb129 } diff --git a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll --- a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll +++ b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll @@ -7,9 +7,9 @@ %struct.ui = type { ptr, ptr, i32, ptr, ptr, i64, ptr, ptr, ptr } -define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize) nounwind { +define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2) nounwind { entry: - br i1 undef, label %bb1, label %bb + br i1 %replaceUndef0, label %bb1, label %bb bb: ; preds = %entry unreachable @@ -21,13 +21,13 @@ %1 = getelementptr inbounds %struct.ui, ptr %0, i32 0, i32 5 %2 = load i64, ptr %1, align 4 %3 = call i32 @mo_create_nnm(ptr undef, i64 %2, ptr undef) nounwind - br i1 undef, label %bb3, label %bb2 + br i1 %replaceUndef1, label %bb3, label %bb2 bb2: ; preds = %bb1 unreachable bb3: ; preds = %bb1 - br i1 undef, label %bb4, label %bb6 + br i1 %replaceUndef2, label %bb4, label %bb6 bb4: ; preds = %bb3 %4 = call i32 @vn_size(ptr %vp, ptr %1, ptr undef) nounwind diff --git a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll --- a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll +++ b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll @@ -9,15 +9,15 @@ %struct.hc = type { i32, i32, i32, i32 } -define i32 @t(i32 %type) optsize { +define i32 @t(i32 %type, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) optsize { entry: - br i1 undef, label %if.then, label %if.else + br i1 %replaceUndef0, label %if.then, label %if.else if.then: unreachable if.else: - br i1 undef, label %if.then15, label %if.else18 + br i1 %replaceUndef1, label %if.then15, label %if.else18 if.then15: unreachable @@ -29,7 +29,7 @@ ] if.then102: - br i1 undef, label %cond.true10.i, label %t.exit + br i1 %replaceUndef2, label %cond.true10.i, label %t.exit cond.true10.i: br label %t.exit @@ -38,7 +38,7 @@ unreachable if.then115: - br i1 undef, label %if.else163, label %if.else145 + br i1 %replaceUndef3, label %if.else163, label %if.else145 if.else145: %call150 = call fastcc ptr @foo(ptr undef, i32 34865152) optsize diff --git a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll --- a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll +++ b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -2,10 +2,10 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" -define void @compdecomp() nounwind { +define void @compdecomp( i1 %replaceUndef0) nounwind { entry: %heap = alloca [256 x i32], align 4 - br i1 undef, label %bb25.lr.ph, label %bb17 + br i1 %replaceUndef0, label %bb25.lr.ph, label %bb17 bb17: ; preds = %bb17, %entry br label %bb17 diff --git a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll --- a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll +++ b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll @@ -10,7 +10,7 @@ declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind -define hidden fastcc i32 @sqlite3VdbeExec(ptr %p) nounwind { +define hidden fastcc i32 @sqlite3VdbeExec(ptr %p, i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) nounwind { entry: br label %sqlite3VarintLen.exit7424 @@ -18,21 +18,21 @@ br label %do.body.i do.body.i: ; preds = %do.body.i, %sqlite3VarintLen.exit7424 - br i1 undef, label %do.body.i, label %sqlite3VarintLen.exit + br i1 %replaceUndef0, label %do.body.i, label %sqlite3VarintLen.exit sqlite3VarintLen.exit: ; preds = %do.body.i %sub2322 = add i64 undef, undef - br i1 undef, label %too_big, label %if.end2327 + br i1 %replaceUndef1, label %too_big, label %if.end2327 if.end2327: ; preds = %sqlite3VarintLen.exit - br i1 undef, label %if.end2341, label %no_mem + br i1 %replaceUndef2, label %if.end2341, label %no_mem if.end2341: ; preds = %if.end2327 br label %for.body2355 for.body2355: ; preds = %for.body2355, %if.end2341 %add2366 = add nsw i32 undef, undef - br i1 undef, label %for.body2377, label %for.body2355 + br i1 %replaceUndef3, label %for.body2377, label %for.body2355 for.body2377: ; preds = %for.body2355 %conv23836154 = zext i32 %add2366 to i64 diff --git a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll --- a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -5,7 +5,7 @@ target triple = "thumbv7-apple-ios4.0.0" ; STATS-NOT: machine-sink -define i32 @foo(i32 %h, i32 %arg1) nounwind readonly ssp { +define i32 @foo(i32 %h, i32 %arg1, i1 %replaceUndef0) nounwind readonly ssp { entry: br label %for.cond @@ -31,7 +31,7 @@ %abs = select i1 %cmp112, i32 %sub115, i32 %sub111 %add95 = add i32 %v.5, %v.8 %add117 = add i32 %add95, %abs - br i1 undef, label %for.cond, label %if.end299 + br i1 %replaceUndef0, label %for.cond, label %if.end299 if.end299: ; preds = %for.body, %for.cond %s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ] diff --git a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll --- a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -3,9 +3,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target triple = "armv7-none-linux-gnueabi" -define arm_aapcs_vfpcc void @foo(ptr nocapture %arg) nounwind uwtable align 2 { +define arm_aapcs_vfpcc void @foo(ptr nocapture %arg, i1 %replaceUndef0) nounwind uwtable align 2 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %replaceUndef0, label %bb1, label %bb2 bb1: ; preds = %bb unreachable diff --git a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll --- a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -38,9 +38,9 @@ ret void } -define arm_aapcs_vfpcc void @foo2() nounwind uwtable { +define arm_aapcs_vfpcc void @foo2( i1 %replaceUndef0) nounwind uwtable { entry: - br i1 undef, label %for.end, label %cond.end295 + br i1 %replaceUndef0, label %for.end, label %cond.end295 cond.end295: ; preds = %entry %shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll --- a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -6,15 +6,15 @@ ; This test case exercises the MachineCopyPropagation pass by disabling the ; RegisterCoalescer. -define arm_aapcs_vfpcc void @foo(ptr %arg) nounwind uwtable align 2 { +define arm_aapcs_vfpcc void @foo(ptr %arg, i1 %replaceUndef0, i1 %replaceUndef1) nounwind uwtable align 2 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %replaceUndef0, label %bb1, label %bb2 bb1: ; preds = %bb unreachable bb2: ; preds = %bb - br i1 undef, label %bb92, label %bb3 + br i1 %replaceUndef1, label %bb92, label %bb3 bb3: ; preds = %bb2 %tmp = or <4 x i32> undef, undef diff --git a/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll b/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll --- a/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll +++ b/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll @@ -3,17 +3,17 @@ target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:32" target triple = "arm-none-linux" -define hidden void @_strtod_r() nounwind { - br i1 undef, label %1, label %2 +define hidden void @_strtod_r( i1 %replaceUndef0, i1 %replaceUndef1, i1 %replaceUndef2, i1 %replaceUndef3) nounwind { + br i1 %replaceUndef0, label %1, label %2 ;