diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -45,12 +45,29 @@ } } +// Define classes to define list containing all SchedWrites for each (name, LMUL) +// pair for each LMUL in each of the SchedMxList variants above and name in +// argument `names`. These classes can be used to construct a list of existing +// definitions of writes corresponding to each (name, LMUL) pair, that are needed +// by the ReadAdvance. For example: +// ``` +// defm "" : LMULReadAdvance<"ReadVIALUX", 1, +// LMULSchedWriteList<["WriteVIMovVX"]>.value>; +// ``` +class LMULSchedWriteListImpl names, list MxList> { + list value = !foldl([], + !foreach(name, names, + !foreach(mx, MxList, !cast(name # "_" # mx))), + all, writes, !listconcat(all, writes)); +} + multiclass LMULSchedWrites : LMULSchedWritesImpl; multiclass LMULSchedReads : LMULSchedReadsImpl; multiclass LMULWriteRes resources> : LMULWriteResImpl; multiclass LMULReadAdvance writes = []> : LMULReadAdvanceImpl; +class LMULSchedWriteList names> : LMULSchedWriteListImpl; multiclass LMULSchedWritesW : LMULSchedWritesImpl; multiclass LMULSchedReadsW : LMULSchedReadsImpl; @@ -58,6 +75,7 @@ : LMULWriteResImpl; multiclass LMULReadAdvanceW writes = []> : LMULReadAdvanceImpl; +class LMULSchedWriteListW names> : LMULSchedWriteListImpl; multiclass LMULSchedWritesFW : LMULSchedWritesImpl; multiclass LMULSchedReadsFW : LMULSchedReadsImpl; @@ -65,10 +83,12 @@ : LMULWriteResImpl; multiclass LMULReadAdvanceFW writes = []> : LMULReadAdvanceImpl; +class LMULSchedWriteListFW names> : LMULSchedWriteListImpl; multiclass LMULSchedWritesFWRed : LMULSchedWritesImpl; multiclass LMULWriteResFWRed resources> : LMULWriteResImpl; +class LMULSchedWriteListFWRed names> : LMULSchedWriteListImpl; // 3.6 Vector Byte Length vlenb