diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19123,11 +19123,15 @@
   SDValue NewChain = getMergeStoreChains(StoreNodes, NumStores);
 
   // make sure we use trunc store if it's necessary to be legal.
+  // When generate the new widen store, discard the pointer info except the
+  // address space because now the widen store can not be represented by the
+  // original pointer info which is for the narrow memory object.
   SDValue NewStore;
   if (!UseTrunc) {
-    NewStore = DAG.getStore(NewChain, DL, StoredVal, FirstInChain->getBasePtr(),
-                            FirstInChain->getPointerInfo(),
-                            FirstInChain->getAlign(), *Flags, AAInfo);
+    NewStore = DAG.getStore(
+        NewChain, DL, StoredVal, FirstInChain->getBasePtr(),
+        MachinePointerInfo(FirstInChain->getPointerInfo().getAddrSpace()),
+        FirstInChain->getAlign(), *Flags, AAInfo);
   } else { // Must be realized as a trunc store
     EVT LegalizedStoredValTy =
         TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
@@ -19138,8 +19142,9 @@
                         LegalizedStoredValTy);
     NewStore = DAG.getTruncStore(
         NewChain, DL, ExtendedStoreVal, FirstInChain->getBasePtr(),
-        FirstInChain->getPointerInfo(), StoredVal.getValueType() /*TVT*/,
-        FirstInChain->getAlign(), *Flags, AAInfo);
+        MachinePointerInfo(FirstInChain->getPointerInfo().getAddrSpace()),
+        StoredVal.getValueType() /*TVT*/, FirstInChain->getAlign(), *Flags,
+        AAInfo);
   }
 
   // Replace all merged stores with the new store.
diff --git a/llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll b/llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
--- a/llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
+++ b/llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
@@ -15,7 +15,7 @@
 define void @blam0(<3 x float>* %g0, <3 x float>* %g1) {
 ; MIR-LABEL: name: blam0
 ; MIR: LDRDui %0, 0 :: (load (s64) from %ir.g0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
-; MIR: STRDui killed %5, %1, 0 :: (store (s64) into %ir.tmp41, align 4, !alias.scope ![[SET1]], !noalias ![[SET0]])
+; MIR: STRDui killed %5, %1, 0 :: (store (s64), align 4, !alias.scope ![[SET1]], !noalias ![[SET0]])
   %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* %g1, i64 0, i64 0
   %tmp5 = load <3 x float>, <3 x float>* %g0, align 4, !alias.scope !0, !noalias !1
   %tmp6 = extractelement <3 x float> %tmp5, i64 0
@@ -35,7 +35,7 @@
 ; MIR-DAG: ![[MMSET1:[0-9]+]] = !{}
 ; MIR: body:
 ; MIR: LDRDui %0, 0 :: (load (s64) from %ir.g0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
-; MIR: STRDui killed %5, %1, 0 :: (store (s64) into %ir.tmp41, align 4, !alias.scope ![[MMSET0]], !noalias ![[MMSET1]])
+; MIR: STRDui killed %5, %1, 0 :: (store (s64), align 4, !alias.scope ![[MMSET0]], !noalias ![[MMSET1]])
   %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* %g1, i64 0, i64 0
   %tmp5 = load <3 x float>, <3 x float>* %g0, align 4, !alias.scope !0, !noalias !1
   %tmp6 = extractelement <3 x float> %tmp5, i64 0
diff --git a/llvm/test/CodeGen/PowerPC/const-splat-array-init.ll b/llvm/test/CodeGen/PowerPC/const-splat-array-init.ll
--- a/llvm/test/CodeGen/PowerPC/const-splat-array-init.ll
+++ b/llvm/test/CodeGen/PowerPC/const-splat-array-init.ll
@@ -80,8 +80,8 @@
 ; P8-BE-NEXT:    lxvw4x 0, 0, 4
 ; P8-BE-NEXT:    lis 4, 3333
 ; P8-BE-NEXT:    ori 4, 4, 3333
-; P8-BE-NEXT:    stw 4, 16(3)
 ; P8-BE-NEXT:    stxvw4x 0, 0, 3
+; P8-BE-NEXT:    stw 4, 16(3)
 ; P8-BE-NEXT:    blr
 ;
 ; P9-BE-LABEL: foo2:
@@ -144,13 +144,13 @@
 ; P8-BE-LABEL: foo3:
 ; P8-BE:       # %bb.0: # %entry
 ; P8-BE-NEXT:    ld 4, L..C2(2) # %const.0
+; P8-BE-NEXT:    li 5, 3333
+; P8-BE-NEXT:    sth 5, 20(3)
 ; P8-BE-NEXT:    lxvw4x 0, 0, 4
 ; P8-BE-NEXT:    lis 4, 3333
 ; P8-BE-NEXT:    ori 4, 4, 3333
-; P8-BE-NEXT:    stw 4, 16(3)
-; P8-BE-NEXT:    li 4, 3333
 ; P8-BE-NEXT:    stxvw4x 0, 0, 3
-; P8-BE-NEXT:    sth 4, 20(3)
+; P8-BE-NEXT:    stw 4, 16(3)
 ; P8-BE-NEXT:    blr
 ;
 ; P9-BE-LABEL: foo3:
diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll
--- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll
+++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll
@@ -591,38 +591,40 @@
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
 ; CHECK-BE-NEXT:    lxvw4x vs35, 0, r3
 ; CHECK-BE-NEXT:    li r3, 16
-; CHECK-BE-NEXT:    stxsiwx vs34, r5, r3
-; CHECK-BE-NEXT:    stfiwx f0, r5, r4
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxvw4x vs35, 0, r5
+; CHECK-BE-NEXT:    stxsiwx vs34, r5, r3
+; CHECK-BE-NEXT:    stfiwx f0, r5, r4
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-NEXT:    xxsldwi vs1, vs34, vs34, 1
+; CHECK-P9-NEXT:    vmr v3, v2
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
 ; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    li r3, 16
+; CHECK-P9-NEXT:    xxperm vs35, vs34, vs0
+; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1
+; CHECK-P9-NEXT:    stxv vs35, 0(r5)
+; CHECK-P9-NEXT:    stfiwx f0, r5, r3
 ; CHECK-P9-NEXT:    li r3, 20
 ; CHECK-P9-NEXT:    stxsiwx vs34, r5, r3
-; CHECK-P9-NEXT:    li r3, 16
-; CHECK-P9-NEXT:    stfiwx f1, r5, r3
-; CHECK-P9-NEXT:    xxperm vs34, vs34, vs0
-; CHECK-P9-NEXT:    stxv vs34, 0(r5)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-BE-NEXT:    xxsldwi vs1, vs34, vs34, 1
+; CHECK-P9-BE-NEXT:    vmr v3, v2
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
 ; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-P9-BE-NEXT:    li r3, 16
+; CHECK-P9-BE-NEXT:    xxperm vs35, vs34, vs0
+; CHECK-P9-BE-NEXT:    xxsldwi vs0, vs34, vs34, 1
+; CHECK-P9-BE-NEXT:    stxv vs35, 0(r5)
 ; CHECK-P9-BE-NEXT:    stxsiwx vs34, r5, r3
 ; CHECK-P9-BE-NEXT:    li r3, 20
-; CHECK-P9-BE-NEXT:    stfiwx f1, r5, r3
-; CHECK-P9-BE-NEXT:    xxperm vs34, vs34, vs0
-; CHECK-P9-BE-NEXT:    stxv vs34, 0(r5)
+; CHECK-P9-BE-NEXT:    stfiwx f0, r5, r3
 ; CHECK-P9-BE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 2
diff --git a/llvm/test/CodeGen/X86/merge-store-dependency.ll b/llvm/test/CodeGen/X86/merge-store-dependency.ll
--- a/llvm/test/CodeGen/X86/merge-store-dependency.ll
+++ b/llvm/test/CodeGen/X86/merge-store-dependency.ll
@@ -4,14 +4,14 @@
 
 ;; MOVUPSmr is a merged store from stack objects %ir.arg1, %ir.arg2, %ir.arg3,
 ;; %ir.arg4.
-;; FIXME: the merged store should have dependency with %ir.arg4.
+;; Check that the merged store has dependency with %ir.arg4.
 
 ; CHECK:       ********** MI Scheduling **********
 ; CHECK-LABEL: f:%bb.0 bb
 ; CHECK:       SU([[ARG4:[0-9]+]]):{{.*}}MOV32rm{{.*}}load (s32) from %ir.arg4
 ; CHECK:       SU([[#WIDEN:]]):{{.*}}MOVUPSmr{{.*}}store (s128) into
 ; CHECK:         Predecessors:
-; CHECK-NOT:       SU([[ARG4]]):{{.*}}Memory
+; CHECKT:          SU([[ARG4]]):{{.*}}Memory
 ; CHECK:       SU([[#WIDEN+1]])
 ;