diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -1896,11 +1896,38 @@ } } + std::tuple getFirst2Regs() const { + return std::make_tuple(getOperand(0).getReg(), getOperand(1).getReg()); + } + + std::tuple getFirst3Regs() const { + return std::make_tuple(getOperand(0).getReg(), getOperand(1).getReg(), + getOperand(2).getReg()); + } + + std::tuple getFirst4Regs() const { + return std::make_tuple(getOperand(0).getReg(), getOperand(1).getReg(), + getOperand(2).getReg(), getOperand(3).getReg()); + } + + std::tuple + getFirst5Regs() const { + return std::make_tuple(getOperand(0).getReg(), getOperand(1).getReg(), + getOperand(2).getReg(), getOperand(3).getReg(), + getOperand(4).getReg()); + } + + std::tuple getFirst2LLTs() const; + std::tuple getFirst3LLTs() const; + std::tuple getFirst4LLTs() const; + std::tuple getFirst5LLTs() const; + private: /// If this instruction is embedded into a MachineFunction, return the /// MachineRegisterInfo object for the current function, otherwise /// return null. MachineRegisterInfo *getRegInfo(); + const MachineRegisterInfo *getRegInfo() const; /// Unlink all of the register operands in this instruction from their /// respective use lists. This requires that the operands already be on their diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1506,13 +1506,12 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); + auto [DstReg, Src1Reg] = MI.getFirst2Regs(); + auto [DstTy, Src1Ty] = MI.getFirst2LLTs(); if (DstTy.isVector()) return UnableToLegalize; - Register Src1 = MI.getOperand(1).getReg(); - LLT SrcTy = MRI.getType(Src1); + LLT SrcTy = MRI.getType(Src1Reg); const int DstSize = DstTy.getSizeInBits(); const int SrcSize = SrcTy.getSizeInBits(); const int WideSize = WideTy.getSizeInBits(); @@ -1524,7 +1523,7 @@ if (WideSize >= DstSize) { // Directly pack the bits in the target type. - Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); + Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1Reg).getReg(0); for (unsigned I = 2; I != NumOps; ++I) { const unsigned Offset = (I - 1) * PartSize; @@ -1755,11 +1754,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT SrcTy = MRI.getType(SrcReg); - - LLT DstTy = MRI.getType(DstReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned Offset = MI.getOperand(2).getImm(); if (TypeIdx == 0) { @@ -1980,10 +1976,7 @@ } bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; - Register Result = MI.getOperand(0).getReg(); - Register OriginalOverflow = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + auto [Result, OriginalOverflow, LHS, RHS] = MI.getFirst4Regs(); LLT SrcTy = MRI.getType(LHS); LLT OverflowTy = MRI.getType(OriginalOverflow); unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); @@ -2660,11 +2653,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerBitcast(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); - + auto [Dst, Src] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); if (SrcTy.isVector()) { LLT SrcEltTy = SrcTy.getElementType(); SmallVector SrcRegs; @@ -2760,11 +2750,8 @@ if (TypeIdx != 1) return UnableToLegalize; - Register Dst = MI.getOperand(0).getReg(); - Register SrcVec = MI.getOperand(1).getReg(); - Register Idx = MI.getOperand(2).getReg(); - LLT SrcVecTy = MRI.getType(SrcVec); - LLT IdxTy = MRI.getType(Idx); + auto [Dst, SrcVec, Idx] = MI.getFirst3Regs(); + auto [DstTy, SrcVecTy, IdxTy] = MI.getFirst3LLTs(); LLT SrcEltTy = SrcVecTy.getElementType(); unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; @@ -2900,13 +2887,9 @@ if (TypeIdx != 0) return UnableToLegalize; - Register Dst = MI.getOperand(0).getReg(); - Register SrcVec = MI.getOperand(1).getReg(); - Register Val = MI.getOperand(2).getReg(); - Register Idx = MI.getOperand(3).getReg(); - - LLT VecTy = MRI.getType(Dst); - LLT IdxTy = MRI.getType(Idx); + auto [Dst, SrcVec, Val, Idx] = MI.getFirst4Regs(); + auto [DstTy, SrcVecTy, ValTy, IdxTy] = MI.getFirst4LLTs(); + LLT VecTy = DstTy; LLT VecEltTy = VecTy.getElementType(); LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; @@ -3304,10 +3287,7 @@ case TargetOpcode::G_UMULO: { // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the // result. - Register Res = MI.getOperand(0).getReg(); - Register Overflow = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + auto [Res, Overflow, LHS, RHS] = MI.getFirst4Regs(); LLT Ty = MRI.getType(Res); unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO @@ -3338,7 +3318,7 @@ return Legalized; } case TargetOpcode::G_FNEG: { - Register Res = MI.getOperand(0).getReg(); + auto [Res, SubByReg] = MI.getFirst2Regs(); LLT Ty = MRI.getType(Res); // TODO: Handle vector types once we are able to @@ -3347,14 +3327,13 @@ return UnableToLegalize; auto SignMask = MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); - Register SubByReg = MI.getOperand(1).getReg(); MIRBuilder.buildXor(Res, SubByReg, SignMask); MI.eraseFromParent(); return Legalized; } case TargetOpcode::G_FSUB: case TargetOpcode::G_STRICT_FSUB: { - Register Res = MI.getOperand(0).getReg(); + auto [Res, LHS, RHS] = MI.getFirst3Regs(); LLT Ty = MRI.getType(Res); // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). @@ -3362,8 +3341,6 @@ // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) return UnableToLegalize; - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); auto Neg = MIRBuilder.buildFNeg(Ty, RHS); if (MI.getOpcode() == TargetOpcode::G_STRICT_FSUB) @@ -3387,11 +3364,7 @@ return Legalized; } case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { - Register OldValRes = MI.getOperand(0).getReg(); - Register SuccessRes = MI.getOperand(1).getReg(); - Register Addr = MI.getOperand(2).getReg(); - Register CmpVal = MI.getOperand(3).getReg(); - Register NewVal = MI.getOperand(4).getReg(); + auto [OldValRes, SuccessRes, Addr, CmpVal, NewVal] = MI.getFirst5Regs(); MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, **MI.memoperands_begin()); MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); @@ -3411,10 +3384,7 @@ case TargetOpcode::G_CTPOP: return lowerBitCount(MI); case G_UADDO: { - Register Res = MI.getOperand(0).getReg(); - Register CarryOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + auto [Res, CarryOut, LHS, RHS] = MI.getFirst4Regs(); MIRBuilder.buildAdd(Res, LHS, RHS); MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); @@ -3423,11 +3393,7 @@ return Legalized; } case G_UADDE: { - Register Res = MI.getOperand(0).getReg(); - Register CarryOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); - Register CarryIn = MI.getOperand(4).getReg(); + auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs(); LLT Ty = MRI.getType(Res); auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); @@ -3439,10 +3405,7 @@ return Legalized; } case G_USUBO: { - Register Res = MI.getOperand(0).getReg(); - Register BorrowOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + auto [Res, BorrowOut, LHS, RHS] = MI.getFirst4Regs(); MIRBuilder.buildSub(Res, LHS, RHS); MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); @@ -3451,11 +3414,7 @@ return Legalized; } case G_USUBE: { - Register Res = MI.getOperand(0).getReg(); - Register BorrowOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); - Register BorrowIn = MI.getOperand(4).getReg(); + auto [Res, BorrowOut, LHS, RHS, BorrowIn] = MI.getFirst5Regs(); const LLT CondTy = MRI.getType(BorrowOut); const LLT Ty = MRI.getType(Res); @@ -3500,8 +3459,7 @@ assert(MI.getOperand(2).isImm() && "Expected immediate"); int64_t SizeInBits = MI.getOperand(2).getImm(); - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); LLT DstTy = MRI.getType(DstReg); Register TmpRes = MRI.createGenericVirtualRegister(DstTy); @@ -3899,9 +3857,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); // Requires compatible types. Otherwise user of DstReg did not perform unmerge // that should have been artifact combined. Most likely instruction that uses // DstReg has to do more/fewer elements legalization compatible with NarrowTy. @@ -3988,8 +3945,7 @@ LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT NarrowVecTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcVec = MI.getOperand(1).getReg(); + auto [DstReg, SrcVec] = MI.getFirst2Regs(); Register InsertVal; bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; @@ -4308,13 +4264,9 @@ if (TypeIdx != 0) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register Src1Reg = MI.getOperand(1).getReg(); - Register Src2Reg = MI.getOperand(2).getReg(); + auto [DstReg, Src1Reg, Src2Reg] = MI.getFirst3Regs(); + auto [DstTy, Src1Ty, Src2Ty] = MI.getFirst3LLTs(); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); - LLT DstTy = MRI.getType(DstReg); - LLT Src1Ty = MRI.getType(Src1Reg); - LLT Src2Ty = MRI.getType(Src2Reg); // The shuffle should be canonicalized by now. if (DstTy != Src1Ty) return UnableToLegalize; @@ -4504,10 +4456,8 @@ // The semantics of the normal non-sequential reductions allow us to freely // re-associate the operation. - Register SrcReg = MI.getOperand(1).getReg(); - LLT SrcTy = MRI.getType(SrcReg); - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); if (NarrowTy.isVector() && (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0)) @@ -4917,10 +4867,8 @@ Observer.changedInstr(MI); return Legalized; case TargetOpcode::G_SELECT: { - Register DstReg = MI.getOperand(0).getReg(); - Register CondReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT CondTy = MRI.getType(CondReg); + auto [DstReg, CondReg] = MI.getFirst2Regs(); + auto [DstTy, CondTy] = MI.getFirst2LLTs(); if (TypeIdx == 1) { if (!CondTy.isScalar() || DstTy.getElementCount() != MoreTy.getElementCount()) @@ -4981,14 +4929,11 @@ /// Expand source vectors to the size of destination vector. static LegalizerHelper::LegalizeResult equalizeVectorShuffleLengths(MachineInstr &MI, MachineIRBuilder &MIRBuilder) { - MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); - - LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); - LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); unsigned MaskNumElts = Mask.size(); unsigned SrcNumElts = SrcTy.getNumElements(); - Register DstReg = MI.getOperand(0).getReg(); LLT DestEltTy = DstTy.getElementType(); // TODO: Normalize the shuffle vector since mask and vector length don't @@ -5044,13 +4989,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI, unsigned int TypeIdx, LLT MoreTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register Src1Reg = MI.getOperand(1).getReg(); - Register Src2Reg = MI.getOperand(2).getReg(); + auto [DstTy, Src1Ty, Src2Ty] = MI.getFirst3LLTs(); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); - LLT DstTy = MRI.getType(DstReg); - LLT Src1Ty = MRI.getType(Src1Reg); - LLT Src2Ty = MRI.getType(Src2Reg); unsigned NumElts = DstTy.getNumElements(); unsigned WidenNumElts = MoreTy.getNumElements(); @@ -5248,9 +5188,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register Src1 = MI.getOperand(1).getReg(); - Register Src2 = MI.getOperand(2).getReg(); + auto [DstReg, Src1, Src2] = MI.getFirst3Regs(); LLT Ty = MRI.getType(DstReg); if (Ty.isVector()) @@ -5501,8 +5439,7 @@ if (TypeIdx != 0) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); LLT DstTy = MRI.getType(DstReg); if (DstTy.isVector()) @@ -5569,10 +5506,8 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned NarrowSize = NarrowTy.getSizeInBits(); if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { @@ -5605,10 +5540,8 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned NarrowSize = NarrowTy.getSizeInBits(); if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { @@ -5641,9 +5574,8 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned NarrowSize = NarrowTy.getSizeInBits(); if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { @@ -5679,10 +5611,8 @@ return Legalized; } case TargetOpcode::G_CTLZ: { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned Len = SrcTy.getSizeInBits(); if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { @@ -5729,10 +5659,8 @@ return Legalized; } case TargetOpcode::G_CTTZ: { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned Len = SrcTy.getSizeInBits(); if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { @@ -5838,10 +5766,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register X = MI.getOperand(1).getReg(); - Register Y = MI.getOperand(2).getReg(); - Register Z = MI.getOperand(3).getReg(); + auto [Dst, X, Y, Z] = MI.getFirst4Regs(); LLT Ty = MRI.getType(Dst); LLT ShTy = MRI.getType(Z); @@ -5880,10 +5805,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register X = MI.getOperand(1).getReg(); - Register Y = MI.getOperand(2).getReg(); - Register Z = MI.getOperand(3).getReg(); + auto [Dst, X, Y, Z] = MI.getFirst4Regs(); LLT Ty = MRI.getType(Dst); LLT ShTy = MRI.getType(Z); @@ -5962,10 +5884,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Amt = MI.getOperand(2).getReg(); - LLT AmtTy = MRI.getType(Amt); + auto [Dst, Src, Amt] = MI.getFirst3Regs(); + auto [DstTy, SrcTy, AmtTy] = MI.getFirst3LLTs(); auto Zero = MIRBuilder.buildConstant(AmtTy, 0); bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; @@ -5976,12 +5896,8 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Amt = MI.getOperand(2).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); - LLT AmtTy = MRI.getType(Amt); + auto [Dst, Src, Amt] = MI.getFirst3Regs(); + auto [DstTy, SrcTy, AmtTy] = MI.getFirst3LLTs(); unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; @@ -6051,8 +5967,7 @@ // representation. LegalizerHelper::LegalizeResult LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); + auto [Dst, Src] = MI.getFirst2Regs(); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); const LLT S1 = LLT::scalar(1); @@ -6107,10 +6022,8 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + auto [Dst, Src] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); if (SrcTy == LLT::scalar(1)) { auto True = MIRBuilder.buildFConstant(DstTy, 1.0); @@ -6135,10 +6048,8 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + auto [Dst, Src] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); @@ -6181,10 +6092,8 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + auto [Dst, Src] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); @@ -6224,10 +6133,8 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + auto [Dst, Src] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); @@ -6293,9 +6200,7 @@ // f64 -> f16 conversion using round-to-nearest-even rounding mode. LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - + auto [Dst, Src] = MI.getFirst2Regs(); if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. return UnableToLegalize; @@ -6398,11 +6303,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); const LLT S64 = LLT::scalar(64); const LLT S16 = LLT::scalar(16); @@ -6415,9 +6316,7 @@ // TODO: If RHS is a constant SelectionDAGBuilder expands this into a // multiplication tree. LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); + auto [Dst, Src0, Src1] = MI.getFirst3Regs(); LLT Ty = MRI.getType(Dst); auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); @@ -6442,9 +6341,7 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); + auto [Dst, Src0, Src1] = MI.getFirst3Regs(); const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); LLT CmpType = MRI.getType(Dst).changeElementSize(1); @@ -6458,12 +6355,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFCopySign(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); - - const LLT Src0Ty = MRI.getType(Src0); - const LLT Src1Ty = MRI.getType(Src1); + auto [Dst, Src0, Src1] = MI.getFirst3Regs(); + auto [DstTy, Src0Ty, Src1Ty] = MI.getFirst3LLTs(); const int Src0Size = Src0Ty.getScalarSizeInBits(); const int Src1Size = Src1Ty.getScalarSizeInBits(); @@ -6505,9 +6398,7 @@ unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); + auto [Dst, Src0, Src1] = MI.getFirst3Regs(); LLT Ty = MRI.getType(Dst); if (!MI.getFlag(MachineInstr::FmNoNans)) { @@ -6546,8 +6437,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register X = MI.getOperand(1).getReg(); + auto [DstReg, X] = MI.getFirst2Regs(); const unsigned Flags = MI.getFlags(); const LLT Ty = MRI.getType(DstReg); const LLT CondTy = Ty.changeElementSize(1); @@ -6577,10 +6467,8 @@ return Legalized; } -LegalizerHelper::LegalizeResult -LegalizerHelper::lowerFFloor(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); +LegalizerHelper::LegalizeResult LegalizerHelper::lowerFFloor(MachineInstr &MI) { + auto [DstReg, SrcReg] = MI.getFirst2Regs(); unsigned Flags = MI.getFlags(); LLT Ty = MRI.getType(DstReg); const LLT CondTy = Ty.changeElementSize(1); @@ -6607,11 +6495,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerMergeValues(MachineInstr &MI) { const unsigned NumOps = MI.getNumOperands(); - Register DstReg = MI.getOperand(0).getReg(); - Register Src0Reg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(Src0Reg); - unsigned PartSize = SrcTy.getSizeInBits(); + auto [DstReg, Src0Reg] = MI.getFirst2Regs(); + auto [DstTy, Src0Ty] = MI.getFirst2LLTs(); + unsigned PartSize = Src0Ty.getSizeInBits(); LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); @@ -6759,11 +6645,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register Src0Reg = MI.getOperand(1).getReg(); - Register Src1Reg = MI.getOperand(2).getReg(); - LLT Src0Ty = MRI.getType(Src0Reg); - LLT DstTy = MRI.getType(DstReg); + auto [DstReg, Src0Reg, Src1Reg] = MI.getFirst3Regs(); + auto [DstTy, Src0Ty, Src1Ty] = MI.getFirst3LLTs(); LLT IdxTy = LLT::scalar(32); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); @@ -6852,13 +6735,10 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerExtract(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); unsigned Offset = MI.getOperand(2).getImm(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); - // Extract sub-vector or one element if (SrcTy.isVector()) { unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits(); @@ -6867,7 +6747,7 @@ if ((Offset % SrcEltSize == 0) && (DstSize % SrcEltSize == 0) && (Offset + DstSize <= SrcTy.getSizeInBits())) { // Unmerge and allow access to each Src element for the artifact combiner. - auto Unmerge = MIRBuilder.buildUnmerge(SrcTy.getElementType(), Src); + auto Unmerge = MIRBuilder.buildUnmerge(SrcTy.getElementType(), SrcReg); // Take element(s) we need to extract and copy it (merge them). SmallVector SubVectorElts; @@ -6876,9 +6756,9 @@ SubVectorElts.push_back(Unmerge.getReg(Idx)); } if (SubVectorElts.size() == 1) - MIRBuilder.buildCopy(Dst, SubVectorElts[0]); + MIRBuilder.buildCopy(DstReg, SubVectorElts[0]); else - MIRBuilder.buildMergeLikeInstr(Dst, SubVectorElts); + MIRBuilder.buildMergeLikeInstr(DstReg, SubVectorElts); MI.eraseFromParent(); return Legalized; @@ -6891,15 +6771,15 @@ LLT SrcIntTy = SrcTy; if (!SrcTy.isScalar()) { SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); - Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); + SrcReg = MIRBuilder.buildBitcast(SrcIntTy, SrcReg).getReg(0); } if (Offset == 0) - MIRBuilder.buildTrunc(Dst, Src); + MIRBuilder.buildTrunc(DstReg, SrcReg); else { auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); - auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); - MIRBuilder.buildTrunc(Dst, Shr); + auto Shr = MIRBuilder.buildLShr(SrcIntTy, SrcReg, ShiftAmt); + MIRBuilder.buildTrunc(DstReg, Shr); } MI.eraseFromParent(); @@ -6910,9 +6790,7 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register InsertSrc = MI.getOperand(2).getReg(); + auto [Dst, Src, InsertSrc] = MI.getFirst3Regs(); uint64_t Offset = MI.getOperand(3).getImm(); LLT DstTy = MRI.getType(Src); @@ -7002,14 +6880,12 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { - Register Dst0 = MI.getOperand(0).getReg(); - Register Dst1 = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + auto [Dst0, Dst1, LHS, RHS] = MI.getFirst4Regs(); + auto [Dst0Ty, Dst1Ty, LHSTy, RHSTy] = MI.getFirst4LLTs(); const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; - LLT Ty = MRI.getType(Dst0); - LLT BoolTy = MRI.getType(Dst1); + LLT Ty = Dst0Ty; + LLT BoolTy = Dst1Ty; if (IsAdd) MIRBuilder.buildAdd(Dst0, LHS, RHS); @@ -7038,9 +6914,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { - Register Res = MI.getOperand(0).getReg(); - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); + auto [Res, LHS, RHS] = MI.getFirst3Regs(); LLT Ty = MRI.getType(Res); bool IsSigned; bool IsAdd; @@ -7115,9 +6989,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { - Register Res = MI.getOperand(0).getReg(); - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); + auto [Res, LHS, RHS] = MI.getFirst3Regs(); LLT Ty = MRI.getType(Res); LLT BoolTy = Ty.changeElementSize(1); bool IsSigned; @@ -7187,9 +7059,7 @@ MI.getOpcode() == TargetOpcode::G_USHLSAT) && "Expected shlsat opcode!"); bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; - Register Res = MI.getOperand(0).getReg(); - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); + auto [Res, LHS, RHS] = MI.getFirst3Regs(); LLT Ty = MRI.getType(Res); LLT BoolTy = Ty.changeElementSize(1); @@ -7215,10 +7085,8 @@ return Legalized; } -LegalizerHelper::LegalizeResult -LegalizerHelper::lowerBswap(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); +LegalizerHelper::LegalizeResult LegalizerHelper::lowerBswap(MachineInstr &MI) { + auto [Dst, Src] = MI.getFirst2Regs(); const LLT Ty = MRI.getType(Src); unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; @@ -7263,8 +7131,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerBitreverse(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); + auto [Dst, Src] = MI.getFirst2Regs(); const LLT Ty = MRI.getType(Src); unsigned Size = Ty.getSizeInBits(); @@ -7342,10 +7209,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + auto [DstReg, SrcReg] = MI.getFirst2Regs(); + auto [DstTy, SrcTy] = MI.getFirst2LLTs(); uint64_t Mask = MI.getOperand(2).getImm(); if (Mask == 0) { @@ -7388,8 +7253,10 @@ MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_NE, DstTy, AsInt, Abs); auto Res = MIRBuilder.buildConstant(DstTy, 0); + // Clang doesn't support capture of structured bindings: + LLT DstTyCopy = DstTy; const auto appendToRes = [&](MachineInstrBuilder ToAppend) { - Res = MIRBuilder.buildOr(DstTy, Res, ToAppend); + Res = MIRBuilder.buildOr(DstTyCopy, Res, ToAppend); }; // Tests that involve more than one class should be processed first. @@ -7502,12 +7369,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { // Implement vector G_SELECT in terms of XOR, AND, OR. - Register DstReg = MI.getOperand(0).getReg(); - Register MaskReg = MI.getOperand(1).getReg(); - Register Op1Reg = MI.getOperand(2).getReg(); - Register Op2Reg = MI.getOperand(3).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT MaskTy = MRI.getType(MaskReg); + auto [DstReg, MaskReg, Op1Reg, Op2Reg] = MI.getFirst4Regs(); + auto [DstTy, MaskTy, Op1Ty, Op2Ty] = MI.getFirst4LLTs(); + if (!DstTy.isVector()) return UnableToLegalize; @@ -7856,9 +7720,7 @@ LegalizerHelper::lowerMemcpyInline(MachineInstr &MI) { assert(MI.getOpcode() == TargetOpcode::G_MEMCPY_INLINE); - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Len = MI.getOperand(2).getReg(); + auto [Dst, Src, Len] = MI.getFirst3Regs(); const auto *MMOIt = MI.memoperands_begin(); const MachineMemOperand *MemOp = *MMOIt; @@ -8121,9 +7983,7 @@ Align DstAlign = MemOp->getBaseAlign(); Align SrcAlign; - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Len = MI.getOperand(2).getReg(); + auto [Dst, Src, Len] = MI.getFirst3Regs(); if (Opc != TargetOpcode::G_MEMSET) { assert(MMOIt != MI.memoperands_end() && "Expected a second MMO on MI"); diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -149,6 +149,12 @@ return nullptr; } +const MachineRegisterInfo *MachineInstr::getRegInfo() const { + if (const MachineBasicBlock *MBB = getParent()) + return &MBB->getParent()->getRegInfo(); + return nullptr; +} + void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) { for (MachineOperand &MO : operands()) if (MO.isReg()) @@ -2378,3 +2384,29 @@ DebugInstrNum = MF.getNewDebugInstrNum(); return DebugInstrNum; } + +std::tuple MachineInstr::getFirst2LLTs() const { + return std::make_tuple(getRegInfo()->getType(getOperand(0).getReg()), + getRegInfo()->getType(getOperand(1).getReg())); +} + +std::tuple MachineInstr::getFirst3LLTs() const { + return std::make_tuple(getRegInfo()->getType(getOperand(0).getReg()), + getRegInfo()->getType(getOperand(1).getReg()), + getRegInfo()->getType(getOperand(2).getReg())); +} + +std::tuple MachineInstr::getFirst4LLTs() const { + return std::make_tuple(getRegInfo()->getType(getOperand(0).getReg()), + getRegInfo()->getType(getOperand(1).getReg()), + getRegInfo()->getType(getOperand(2).getReg()), + getRegInfo()->getType(getOperand(3).getReg())); +} + +std::tuple MachineInstr::getFirst5LLTs() const { + return std::make_tuple(getRegInfo()->getType(getOperand(0).getReg()), + getRegInfo()->getType(getOperand(1).getReg()), + getRegInfo()->getType(getOperand(2).getReg()), + getRegInfo()->getType(getOperand(3).getReg()), + getRegInfo()->getType(getOperand(4).getReg())); +}