diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -49,6 +49,44 @@ class ConstantFP; class APFloat; +// Convenience macros for extracting common registers from a MachineInstr. +#define Get2RegsFromMI(A, B, MI) \ + Register A = MI.getOperand(0).getReg(); \ + Register B = MI.getOperand(1).getReg(); + +#define Get3RegsFromMI(A, B, C, MI) \ + Get2RegsFromMI(A, B, MI); \ + Register C = MI.getOperand(2).getReg(); + +#define Get4RegsFromMI(A, B, C, D, MI) \ + Get3RegsFromMI(A, B, C, MI); \ + Register D = MI.getOperand(3).getReg(); + +#define Get5RegsFromMI(A, B, C, D, E, MI) \ + Get4RegsFromMI(A, B, C, D, MI); \ + Register E = MI.getOperand(4).getReg(); + +#define Get2RegsTypesFromMI(A, B, MI, MRI) \ + Register A##Reg = MI.getOperand(0).getReg(); \ + Register B##Reg = MI.getOperand(1).getReg(); \ + [[maybe_unused]] LLT A##Ty = MRI.getType(A##Reg); \ + [[maybe_unused]] LLT B##Ty = MRI.getType(B##Reg); + +#define Get3RegsTypesFromMI(A, B, C, MI, MRI) \ + Get2RegsTypesFromMI(A, B, MI, MRI); \ + Register C##Reg = MI.getOperand(2).getReg(); \ + [[maybe_unused]] LLT C##Ty = MRI.getType(C##Reg); + +#define Get4RegsTypesFromMI(A, B, C, D, MI, MRI) \ + Get3RegsTypesFromMI(A, B, C, MI, MRI); \ + Register D##Reg = MI.getOperand(3).getReg(); \ + [[maybe_unused]] LLT D##Ty = MRI.getType(D##Reg); + +#define Get5RegsTypes(A, B, C, D, E, MI, MRI) \ + Get4RegsTypesFromMI(A, B, C, D, MI, MRI); \ + Register E##Reg = MI.getOperand(4).getReg(); \ + [[maybe_unused]] LLT E##Ty = MRI.getType(E##Reg); + // Convenience macros for dealing with vector reduction opcodes. #define GISEL_VECREDUCE_CASES_ALL \ case TargetOpcode::G_VECREDUCE_SEQ_FADD: \ diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1506,13 +1506,11 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); + Get2RegsTypesFromMI(Dst, Src1, MI, MRI); if (DstTy.isVector()) return UnableToLegalize; - Register Src1 = MI.getOperand(1).getReg(); - LLT SrcTy = MRI.getType(Src1); + LLT SrcTy = MRI.getType(Src1Reg); const int DstSize = DstTy.getSizeInBits(); const int SrcSize = SrcTy.getSizeInBits(); const int WideSize = WideTy.getSizeInBits(); @@ -1524,7 +1522,7 @@ if (WideSize >= DstSize) { // Directly pack the bits in the target type. - Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); + Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1Reg).getReg(0); for (unsigned I = 2; I != NumOps; ++I) { const unsigned Offset = (I - 1) * PartSize; @@ -1755,11 +1753,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT SrcTy = MRI.getType(SrcReg); - - LLT DstTy = MRI.getType(DstReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned Offset = MI.getOperand(2).getImm(); if (TypeIdx == 0) { @@ -1980,10 +1974,7 @@ } bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; - Register Result = MI.getOperand(0).getReg(); - Register OriginalOverflow = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + Get4RegsFromMI(Result, OriginalOverflow, LHS, RHS, MI); LLT SrcTy = MRI.getType(LHS); LLT OverflowTy = MRI.getType(OriginalOverflow); unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); @@ -2660,10 +2651,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerBitcast(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); if (SrcTy.isVector()) { LLT SrcEltTy = SrcTy.getElementType(); @@ -2704,21 +2692,21 @@ DstCastTy = DstEltTy; } - getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); + getUnmergePieces(SrcRegs, MIRBuilder, SrcReg, SrcPartTy); for (Register &SrcReg : SrcRegs) SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); } else - getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); + getUnmergePieces(SrcRegs, MIRBuilder, SrcReg, SrcEltTy); - MIRBuilder.buildMergeLikeInstr(Dst, SrcRegs); + MIRBuilder.buildMergeLikeInstr(DstReg, SrcRegs); MI.eraseFromParent(); return Legalized; } if (DstTy.isVector()) { SmallVector SrcRegs; - getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); - MIRBuilder.buildMergeLikeInstr(Dst, SrcRegs); + getUnmergePieces(SrcRegs, MIRBuilder, SrcReg, DstTy.getElementType()); + MIRBuilder.buildMergeLikeInstr(DstReg, SrcRegs); MI.eraseFromParent(); return Legalized; } @@ -2760,18 +2748,14 @@ if (TypeIdx != 1) return UnableToLegalize; - Register Dst = MI.getOperand(0).getReg(); - Register SrcVec = MI.getOperand(1).getReg(); - Register Idx = MI.getOperand(2).getReg(); - LLT SrcVecTy = MRI.getType(SrcVec); - LLT IdxTy = MRI.getType(Idx); + Get3RegsTypesFromMI(Dst, SrcVec, Idx, MI, MRI); LLT SrcEltTy = SrcVecTy.getElementType(); unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; unsigned OldNumElts = SrcVecTy.getNumElements(); LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; - Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); + Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVecReg).getReg(0); const unsigned NewEltSize = NewEltTy.getSizeInBits(); const unsigned OldEltSize = SrcEltTy.getSizeInBits(); @@ -2797,7 +2781,7 @@ auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); SmallVector NewOps(NewEltsPerOldElt); - auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); + auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, IdxReg, NewEltsPerOldEltK); for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); @@ -2807,7 +2791,7 @@ } auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); - MIRBuilder.buildBitcast(Dst, NewVec); + MIRBuilder.buildBitcast(DstReg, NewVec); MI.eraseFromParent(); return Legalized; } @@ -2839,7 +2823,7 @@ auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); // Divide to get the index in the wider element type. - auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); + auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, IdxReg, Log2Ratio); Register WideElt = CastVec; if (CastTy.isVector()) { @@ -2849,11 +2833,11 @@ // Compute the bit offset into the register of the target element. Register OffsetBits = getBitcastWiderVectorElementOffset( - MIRBuilder, Idx, NewEltSize, OldEltSize); + MIRBuilder, IdxReg, NewEltSize, OldEltSize); // Shift the wide element to get the target element. auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); - MIRBuilder.buildTrunc(Dst, ExtractedBits); + MIRBuilder.buildTrunc(DstReg, ExtractedBits); MI.eraseFromParent(); return Legalized; } @@ -2900,13 +2884,8 @@ if (TypeIdx != 0) return UnableToLegalize; - Register Dst = MI.getOperand(0).getReg(); - Register SrcVec = MI.getOperand(1).getReg(); - Register Val = MI.getOperand(2).getReg(); - Register Idx = MI.getOperand(3).getReg(); - - LLT VecTy = MRI.getType(Dst); - LLT IdxTy = MRI.getType(Idx); + Get4RegsTypesFromMI(Dst, SrcVec, Val, Idx, MI, MRI); + LLT VecTy = DstTy; LLT VecEltTy = VecTy.getElementType(); LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; @@ -2916,7 +2895,7 @@ unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; unsigned OldNumElts = VecTy.getNumElements(); - Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); + Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVecReg).getReg(0); if (NewNumElts < OldNumElts) { if (NewEltSize % OldEltSize != 0) return UnableToLegalize; @@ -2931,7 +2910,7 @@ auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); // Divide to get the index in the wider element type. - auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); + auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, IdxReg, Log2Ratio); Register ExtractedElt = CastVec; if (CastTy.isVector()) { @@ -2941,16 +2920,16 @@ // Compute the bit offset into the register of the target element. Register OffsetBits = getBitcastWiderVectorElementOffset( - MIRBuilder, Idx, NewEltSize, OldEltSize); + MIRBuilder, IdxReg, NewEltSize, OldEltSize); Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, - Val, OffsetBits); + ValReg, OffsetBits); if (CastTy.isVector()) { InsertedElt = MIRBuilder.buildInsertVectorElement( CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); } - MIRBuilder.buildBitcast(Dst, InsertedElt); + MIRBuilder.buildBitcast(DstReg, InsertedElt); MI.eraseFromParent(); return Legalized; } @@ -3304,10 +3283,7 @@ case TargetOpcode::G_UMULO: { // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the // result. - Register Res = MI.getOperand(0).getReg(); - Register Overflow = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + Get4RegsFromMI(Res, Overflow, LHS, RHS, MI); LLT Ty = MRI.getType(Res); unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO @@ -3338,7 +3314,7 @@ return Legalized; } case TargetOpcode::G_FNEG: { - Register Res = MI.getOperand(0).getReg(); + Get2RegsFromMI(Res, SubByReg, MI); LLT Ty = MRI.getType(Res); // TODO: Handle vector types once we are able to @@ -3347,14 +3323,13 @@ return UnableToLegalize; auto SignMask = MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); - Register SubByReg = MI.getOperand(1).getReg(); MIRBuilder.buildXor(Res, SubByReg, SignMask); MI.eraseFromParent(); return Legalized; } case TargetOpcode::G_FSUB: case TargetOpcode::G_STRICT_FSUB: { - Register Res = MI.getOperand(0).getReg(); + Get3RegsFromMI(Res, LHS, RHS, MI); LLT Ty = MRI.getType(Res); // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). @@ -3362,8 +3337,6 @@ // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) return UnableToLegalize; - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); auto Neg = MIRBuilder.buildFNeg(Ty, RHS); if (MI.getOpcode() == TargetOpcode::G_STRICT_FSUB) @@ -3387,11 +3360,7 @@ return Legalized; } case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { - Register OldValRes = MI.getOperand(0).getReg(); - Register SuccessRes = MI.getOperand(1).getReg(); - Register Addr = MI.getOperand(2).getReg(); - Register CmpVal = MI.getOperand(3).getReg(); - Register NewVal = MI.getOperand(4).getReg(); + Get5RegsFromMI(OldValRes, SuccessRes, Addr, CmpVal, NewVal, MI); MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, **MI.memoperands_begin()); MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); @@ -3411,10 +3380,7 @@ case TargetOpcode::G_CTPOP: return lowerBitCount(MI); case G_UADDO: { - Register Res = MI.getOperand(0).getReg(); - Register CarryOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + Get4RegsFromMI(Res, CarryOut, LHS, RHS, MI); MIRBuilder.buildAdd(Res, LHS, RHS); MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); @@ -3423,11 +3389,7 @@ return Legalized; } case G_UADDE: { - Register Res = MI.getOperand(0).getReg(); - Register CarryOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); - Register CarryIn = MI.getOperand(4).getReg(); + Get5RegsFromMI(Res, CarryOut, LHS, RHS, CarryIn, MI); LLT Ty = MRI.getType(Res); auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); @@ -3439,10 +3401,7 @@ return Legalized; } case G_USUBO: { - Register Res = MI.getOperand(0).getReg(); - Register BorrowOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + Get4RegsFromMI(Res, BorrowOut, LHS, RHS, MI); MIRBuilder.buildSub(Res, LHS, RHS); MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); @@ -3451,11 +3410,7 @@ return Legalized; } case G_USUBE: { - Register Res = MI.getOperand(0).getReg(); - Register BorrowOut = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); - Register BorrowIn = MI.getOperand(4).getReg(); + Get5RegsFromMI(Res, BorrowOut, LHS, RHS, BorrowIn, MI); const LLT CondTy = MRI.getType(BorrowOut); const LLT Ty = MRI.getType(Res); @@ -3500,8 +3455,7 @@ assert(MI.getOperand(2).isImm() && "Expected immediate"); int64_t SizeInBits = MI.getOperand(2).getImm(); - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); + Get2RegsFromMI(DstReg, SrcReg, MI); LLT DstTy = MRI.getType(DstReg); Register TmpRes = MRI.createGenericVirtualRegister(DstTy); @@ -3899,9 +3853,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); // Requires compatible types. Otherwise user of DstReg did not perform unmerge // that should have been artifact combined. Most likely instruction that uses // DstReg has to do more/fewer elements legalization compatible with NarrowTy. @@ -3988,8 +3940,7 @@ LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT NarrowVecTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcVec = MI.getOperand(1).getReg(); + Get2RegsFromMI(DstReg, SrcVec, MI); Register InsertVal; bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; @@ -4308,13 +4259,8 @@ if (TypeIdx != 0) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register Src1Reg = MI.getOperand(1).getReg(); - Register Src2Reg = MI.getOperand(2).getReg(); + Get3RegsTypesFromMI(Dst, Src1, Src2, MI, MRI); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); - LLT DstTy = MRI.getType(DstReg); - LLT Src1Ty = MRI.getType(Src1Reg); - LLT Src2Ty = MRI.getType(Src2Reg); // The shuffle should be canonicalized by now. if (DstTy != Src1Ty) return UnableToLegalize; @@ -4504,10 +4450,7 @@ // The semantics of the normal non-sequential reductions allow us to freely // re-associate the operation. - Register SrcReg = MI.getOperand(1).getReg(); - LLT SrcTy = MRI.getType(SrcReg); - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); if (NarrowTy.isVector() && (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0)) @@ -4917,10 +4860,7 @@ Observer.changedInstr(MI); return Legalized; case TargetOpcode::G_SELECT: { - Register DstReg = MI.getOperand(0).getReg(); - Register CondReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT CondTy = MRI.getType(CondReg); + Get2RegsTypesFromMI(Dst, Cond, MI, MRI); if (TypeIdx == 1) { if (!CondTy.isScalar() || DstTy.getElementCount() != MoreTy.getElementCount()) @@ -4983,12 +4923,10 @@ equalizeVectorShuffleLengths(MachineInstr &MI, MachineIRBuilder &MIRBuilder) { MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); - LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); - LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); unsigned MaskNumElts = Mask.size(); unsigned SrcNumElts = SrcTy.getNumElements(); - Register DstReg = MI.getOperand(0).getReg(); LLT DestEltTy = DstTy.getElementType(); // TODO: Normalize the shuffle vector since mask and vector length don't @@ -5044,13 +4982,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI, unsigned int TypeIdx, LLT MoreTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register Src1Reg = MI.getOperand(1).getReg(); - Register Src2Reg = MI.getOperand(2).getReg(); + Get3RegsTypesFromMI(Dst, Src1, Src2, MI, MRI); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); - LLT DstTy = MRI.getType(DstReg); - LLT Src1Ty = MRI.getType(Src1Reg); - LLT Src2Ty = MRI.getType(Src2Reg); unsigned NumElts = DstTy.getNumElements(); unsigned WidenNumElts = MoreTy.getNumElements(); @@ -5248,9 +5181,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { - Register DstReg = MI.getOperand(0).getReg(); - Register Src1 = MI.getOperand(1).getReg(); - Register Src2 = MI.getOperand(2).getReg(); + Get3RegsFromMI(DstReg, Src1, Src2, MI); LLT Ty = MRI.getType(DstReg); if (Ty.isVector()) @@ -5501,8 +5432,7 @@ if (TypeIdx != 0) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); + Get2RegsFromMI(DstReg, SrcReg, MI); LLT DstTy = MRI.getType(DstReg); if (DstTy.isVector()) @@ -5569,10 +5499,7 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned NarrowSize = NarrowTy.getSizeInBits(); if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { @@ -5605,10 +5532,7 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned NarrowSize = NarrowTy.getSizeInBits(); if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { @@ -5641,9 +5565,7 @@ if (TypeIdx != 1) return UnableToLegalize; - Register DstReg = MI.getOperand(0).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned NarrowSize = NarrowTy.getSizeInBits(); if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { @@ -5679,10 +5601,7 @@ return Legalized; } case TargetOpcode::G_CTLZ: { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned Len = SrcTy.getSizeInBits(); if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { @@ -5729,10 +5648,7 @@ return Legalized; } case TargetOpcode::G_CTTZ: { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned Len = SrcTy.getSizeInBits(); if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { @@ -5838,10 +5754,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register X = MI.getOperand(1).getReg(); - Register Y = MI.getOperand(2).getReg(); - Register Z = MI.getOperand(3).getReg(); + Get4RegsFromMI(Dst, X, Y, Z, MI); LLT Ty = MRI.getType(Dst); LLT ShTy = MRI.getType(Z); @@ -5880,10 +5793,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register X = MI.getOperand(1).getReg(); - Register Y = MI.getOperand(2).getReg(); - Register Z = MI.getOperand(3).getReg(); + Get4RegsFromMI(Dst, X, Y, Z, MI); LLT Ty = MRI.getType(Dst); LLT ShTy = MRI.getType(Z); @@ -5962,26 +5872,18 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Amt = MI.getOperand(2).getReg(); - LLT AmtTy = MRI.getType(Amt); + Get3RegsTypesFromMI(Dst, Src, Amt, MI, MRI); auto Zero = MIRBuilder.buildConstant(AmtTy, 0); bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; - auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt); - MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); + auto Neg = MIRBuilder.buildSub(AmtTy, Zero, AmtReg); + MIRBuilder.buildInstr(RevRot, {DstReg}, {SrcReg, Neg}); MI.eraseFromParent(); return Legalized; } LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Amt = MI.getOperand(2).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); - LLT AmtTy = MRI.getType(Amt); + Get3RegsTypesFromMI(Dst, Src, Amt, MI, MRI); unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; @@ -6008,10 +5910,10 @@ }; // If a funnel shift in the other direction is supported, use it. if (IsFShLegal) { - return buildFunnelShift(FShOpc, Dst, Src, Amt); + return buildFunnelShift(FShOpc, DstReg, SrcReg, AmtReg); } else if (isPowerOf2_32(EltSizeInBits)) { - Amt = MIRBuilder.buildNeg(DstTy, Amt).getReg(0); - return buildFunnelShift(RevFsh, Dst, Src, Amt); + AmtReg = MIRBuilder.buildNeg(DstTy, AmtReg).getReg(0); + return buildFunnelShift(RevFsh, DstReg, SrcReg, AmtReg); } } @@ -6024,25 +5926,25 @@ if (isPowerOf2_32(EltSizeInBits)) { // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) - auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, Amt); - auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC); - ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); + auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, AmtReg); + auto ShAmt = MIRBuilder.buildAnd(AmtTy, AmtReg, BitWidthMinusOneC); + ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {SrcReg, ShAmt}).getReg(0); auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC); RevShiftVal = - MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, RevAmt}).getReg(0); + MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {SrcReg, RevAmt}).getReg(0); } else { // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits); - auto ShAmt = MIRBuilder.buildURem(AmtTy, Amt, BitWidthC); - ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); + auto ShAmt = MIRBuilder.buildURem(AmtTy, AmtReg, BitWidthC); + ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {SrcReg, ShAmt}).getReg(0); auto RevAmt = MIRBuilder.buildSub(AmtTy, BitWidthMinusOneC, ShAmt); auto One = MIRBuilder.buildConstant(AmtTy, 1); - auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, One}); + auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {SrcReg, One}); RevShiftVal = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0); } - MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); + MIRBuilder.buildOr(DstReg, ShVal, RevShiftVal); MI.eraseFromParent(); return Legalized; } @@ -6051,8 +5953,7 @@ // representation. LegalizerHelper::LegalizeResult LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); + Get2RegsFromMI(Dst, Src, MI); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); const LLT S1 = LLT::scalar(1); @@ -6107,15 +6008,12 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); if (SrcTy == LLT::scalar(1)) { auto True = MIRBuilder.buildFConstant(DstTy, 1.0); auto False = MIRBuilder.buildFConstant(DstTy, 0.0); - MIRBuilder.buildSelect(Dst, Src, True, False); + MIRBuilder.buildSelect(DstReg, SrcReg, True, False); MI.eraseFromParent(); return Legalized; } @@ -6135,10 +6033,7 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); @@ -6147,7 +6042,7 @@ if (SrcTy == S1) { auto True = MIRBuilder.buildFConstant(DstTy, -1.0); auto False = MIRBuilder.buildFConstant(DstTy, 0.0); - MIRBuilder.buildSelect(Dst, Src, True, False); + MIRBuilder.buildSelect(DstReg, SrcReg, True, False); MI.eraseFromParent(); return Legalized; } @@ -6161,7 +6056,7 @@ // float r = cul2f((l + s) ^ s); // return s ? -r : r; // } - Register L = Src; + Register L = SrcReg; auto SignBit = MIRBuilder.buildConstant(S64, 63); auto S = MIRBuilder.buildAShr(S64, L, SignBit); @@ -6172,7 +6067,7 @@ auto RNeg = MIRBuilder.buildFNeg(S32, R); auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, MIRBuilder.buildConstant(S64, 0)); - MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); + MIRBuilder.buildSelect(DstReg, SignNotZero, RNeg, R); MI.eraseFromParent(); return Legalized; } @@ -6181,10 +6076,7 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); @@ -6203,12 +6095,12 @@ APInt::getZero(SrcTy.getSizeInBits())); TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); - MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); + MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, SrcReg); MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. - MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); + MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, SrcReg, Threshold); MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); @@ -6216,18 +6108,15 @@ const LLT S1 = LLT::scalar(1); MachineInstrBuilder FCMP = - MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); - MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); + MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, SrcReg, Threshold); + MIRBuilder.buildSelect(DstReg, FCMP, FPTOSI, Res); MI.eraseFromParent(); return Legalized; } LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); const LLT S64 = LLT::scalar(64); const LLT S32 = LLT::scalar(32); @@ -6244,18 +6133,18 @@ auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); - auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); + auto AndExpMask = MIRBuilder.buildAnd(SrcTy, SrcReg, ExponentMask); auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); auto SignMask = MIRBuilder.buildConstant(SrcTy, APInt::getSignMask(SrcEltBits)); - auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); + auto AndSignMask = MIRBuilder.buildAnd(SrcTy, SrcReg, SignMask); auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); Sign = MIRBuilder.buildSExt(DstTy, Sign); auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); - auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); + auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, SrcReg, MantissaMask); auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); @@ -6284,7 +6173,7 @@ S1, Exponent, ZeroSrcTy); auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); - MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); + MIRBuilder.buildSelect(DstReg, ExponentLt0, ZeroDstTy, Ret); MI.eraseFromParent(); return Legalized; @@ -6293,9 +6182,7 @@ // f64 -> f16 conversion using round-to-nearest-even rounding mode. LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - + Get2RegsFromMI(Dst, Src, MI); if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. return UnableToLegalize; @@ -6398,11 +6285,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); const LLT S64 = LLT::scalar(64); const LLT S16 = LLT::scalar(16); @@ -6415,9 +6298,7 @@ // TODO: If RHS is a constant SelectionDAGBuilder expands this into a // multiplication tree. LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); + Get3RegsFromMI(Dst, Src0, Src1, MI); LLT Ty = MRI.getType(Dst); auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); @@ -6442,9 +6323,7 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); + Get3RegsFromMI(Dst, Src0, Src1, MI); const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); LLT CmpType = MRI.getType(Dst).changeElementSize(1); @@ -6458,12 +6337,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFCopySign(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); - - const LLT Src0Ty = MRI.getType(Src0); - const LLT Src1Ty = MRI.getType(Src1); + Get3RegsTypesFromMI(Dst, Src0, Src1, MI, MRI); const int Src0Size = Src0Ty.getScalarSizeInBits(); const int Src1Size = Src1Ty.getScalarSizeInBits(); @@ -6474,18 +6348,18 @@ auto NotSignBitMask = MIRBuilder.buildConstant( Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); - Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); + Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0Reg, NotSignBitMask).getReg(0); Register And1; if (Src0Ty == Src1Ty) { - And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); + And1 = MIRBuilder.buildAnd(Src1Ty, Src1Reg, SignBitMask).getReg(0); } else if (Src0Size > Src1Size) { auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); - auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); + auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1Reg); auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); } else { auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); - auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); + auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1Reg, ShiftAmt); auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); } @@ -6494,7 +6368,7 @@ // constants are a nan and -0.0, but the final result should preserve // everything. unsigned Flags = MI.getFlags(); - MIRBuilder.buildOr(Dst, And0, And1, Flags); + MIRBuilder.buildOr(DstReg, And0, And1, Flags); MI.eraseFromParent(); return Legalized; @@ -6505,9 +6379,7 @@ unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; - Register Dst = MI.getOperand(0).getReg(); - Register Src0 = MI.getOperand(1).getReg(); - Register Src1 = MI.getOperand(2).getReg(); + Get3RegsFromMI(Dst, Src0, Src1, MI); LLT Ty = MRI.getType(Dst); if (!MI.getFlag(MachineInstr::FmNoNans)) { @@ -6546,8 +6418,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register X = MI.getOperand(1).getReg(); + Get2RegsFromMI(DstReg, X, MI); const unsigned Flags = MI.getFlags(); const LLT Ty = MRI.getType(DstReg); const LLT CondTy = Ty.changeElementSize(1); @@ -6577,10 +6448,8 @@ return Legalized; } -LegalizerHelper::LegalizeResult -LegalizerHelper::lowerFFloor(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); +LegalizerHelper::LegalizeResult LegalizerHelper::lowerFFloor(MachineInstr &MI) { + Get2RegsFromMI(DstReg, SrcReg, MI); unsigned Flags = MI.getFlags(); LLT Ty = MRI.getType(DstReg); const LLT CondTy = Ty.changeElementSize(1); @@ -6607,11 +6476,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerMergeValues(MachineInstr &MI) { const unsigned NumOps = MI.getNumOperands(); - Register DstReg = MI.getOperand(0).getReg(); - Register Src0Reg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(Src0Reg); - unsigned PartSize = SrcTy.getSizeInBits(); + Get2RegsTypesFromMI(Dst, Src0, MI, MRI); + unsigned PartSize = Src0Ty.getSizeInBits(); LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); @@ -6759,11 +6625,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register Src0Reg = MI.getOperand(1).getReg(); - Register Src1Reg = MI.getOperand(2).getReg(); - LLT Src0Ty = MRI.getType(Src0Reg); - LLT DstTy = MRI.getType(DstReg); + Get3RegsTypesFromMI(Dst, Src0, Src1, MI, MRI); LLT IdxTy = LLT::scalar(32); ArrayRef Mask = MI.getOperand(3).getShuffleMask(); @@ -6852,13 +6714,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerExtract(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); unsigned Offset = MI.getOperand(2).getImm(); - LLT DstTy = MRI.getType(Dst); - LLT SrcTy = MRI.getType(Src); - // Extract sub-vector or one element if (SrcTy.isVector()) { unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits(); @@ -6867,7 +6725,7 @@ if ((Offset % SrcEltSize == 0) && (DstSize % SrcEltSize == 0) && (Offset + DstSize <= SrcTy.getSizeInBits())) { // Unmerge and allow access to each Src element for the artifact combiner. - auto Unmerge = MIRBuilder.buildUnmerge(SrcTy.getElementType(), Src); + auto Unmerge = MIRBuilder.buildUnmerge(SrcTy.getElementType(), SrcReg); // Take element(s) we need to extract and copy it (merge them). SmallVector SubVectorElts; @@ -6876,9 +6734,9 @@ SubVectorElts.push_back(Unmerge.getReg(Idx)); } if (SubVectorElts.size() == 1) - MIRBuilder.buildCopy(Dst, SubVectorElts[0]); + MIRBuilder.buildCopy(DstReg, SubVectorElts[0]); else - MIRBuilder.buildMergeLikeInstr(Dst, SubVectorElts); + MIRBuilder.buildMergeLikeInstr(DstReg, SubVectorElts); MI.eraseFromParent(); return Legalized; @@ -6891,15 +6749,15 @@ LLT SrcIntTy = SrcTy; if (!SrcTy.isScalar()) { SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); - Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); + SrcReg = MIRBuilder.buildBitcast(SrcIntTy, SrcReg).getReg(0); } if (Offset == 0) - MIRBuilder.buildTrunc(Dst, Src); + MIRBuilder.buildTrunc(DstReg, SrcReg); else { auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); - auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); - MIRBuilder.buildTrunc(Dst, Shr); + auto Shr = MIRBuilder.buildLShr(SrcIntTy, SrcReg, ShiftAmt); + MIRBuilder.buildTrunc(DstReg, Shr); } MI.eraseFromParent(); @@ -6910,9 +6768,7 @@ } LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register InsertSrc = MI.getOperand(2).getReg(); + Get3RegsFromMI(Dst, Src, InsertSrc, MI) uint64_t Offset = MI.getOperand(3).getImm(); LLT DstTy = MRI.getType(Src); @@ -7002,19 +6858,16 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { - Register Dst0 = MI.getOperand(0).getReg(); - Register Dst1 = MI.getOperand(1).getReg(); - Register LHS = MI.getOperand(2).getReg(); - Register RHS = MI.getOperand(3).getReg(); + Get4RegsTypesFromMI(Dst0, Dst1, LHS, RHS, MI, MRI) const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; - LLT Ty = MRI.getType(Dst0); - LLT BoolTy = MRI.getType(Dst1); + LLT Ty = Dst0Ty; + LLT BoolTy = Dst1Ty; if (IsAdd) - MIRBuilder.buildAdd(Dst0, LHS, RHS); + MIRBuilder.buildAdd(Dst0Reg, LHSReg, RHSReg); else - MIRBuilder.buildSub(Dst0, LHS, RHS); + MIRBuilder.buildSub(Dst0Reg, LHSReg, RHSReg); // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. @@ -7027,20 +6880,18 @@ // (LHS) if and only if the other operand (RHS) is (non-zero) positive, // otherwise there will be overflow. auto ResultLowerThanLHS = - MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); + MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0Reg, LHSReg); auto ConditionRHS = MIRBuilder.buildICmp( - IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); + IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHSReg, Zero); - MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); + MIRBuilder.buildXor(Dst1Reg, ConditionRHS, ResultLowerThanLHS); MI.eraseFromParent(); return Legalized; } LegalizerHelper::LegalizeResult LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { - Register Res = MI.getOperand(0).getReg(); - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); + Get3RegsFromMI(Res, LHS, RHS, MI); LLT Ty = MRI.getType(Res); bool IsSigned; bool IsAdd; @@ -7115,9 +6966,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { - Register Res = MI.getOperand(0).getReg(); - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); + Get3RegsFromMI(Res, LHS, RHS, MI); LLT Ty = MRI.getType(Res); LLT BoolTy = Ty.changeElementSize(1); bool IsSigned; @@ -7187,9 +7036,7 @@ MI.getOpcode() == TargetOpcode::G_USHLSAT) && "Expected shlsat opcode!"); bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; - Register Res = MI.getOperand(0).getReg(); - Register LHS = MI.getOperand(1).getReg(); - Register RHS = MI.getOperand(2).getReg(); + Get3RegsFromMI(Res, LHS, RHS, MI); LLT Ty = MRI.getType(Res); LLT BoolTy = Ty.changeElementSize(1); @@ -7215,10 +7062,8 @@ return Legalized; } -LegalizerHelper::LegalizeResult -LegalizerHelper::lowerBswap(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); +LegalizerHelper::LegalizeResult LegalizerHelper::lowerBswap(MachineInstr &MI) { + Get2RegsFromMI(Dst, Src, MI); const LLT Ty = MRI.getType(Src); unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; @@ -7263,8 +7108,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerBitreverse(MachineInstr &MI) { - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); + Get2RegsFromMI(Dst, Src, MI) const LLT Ty = MRI.getType(Src); unsigned Size = Ty.getSizeInBits(); @@ -7342,10 +7186,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) { - Register DstReg = MI.getOperand(0).getReg(); - Register SrcReg = MI.getOperand(1).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT SrcTy = MRI.getType(SrcReg); + Get2RegsTypesFromMI(Dst, Src, MI, MRI); uint64_t Mask = MI.getOperand(2).getImm(); if (Mask == 0) { @@ -7502,12 +7343,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { // Implement vector G_SELECT in terms of XOR, AND, OR. - Register DstReg = MI.getOperand(0).getReg(); - Register MaskReg = MI.getOperand(1).getReg(); - Register Op1Reg = MI.getOperand(2).getReg(); - Register Op2Reg = MI.getOperand(3).getReg(); - LLT DstTy = MRI.getType(DstReg); - LLT MaskTy = MRI.getType(MaskReg); + Get4RegsTypesFromMI(Dst, Mask, Op1, Op2, MI, MRI); if (!DstTy.isVector()) return UnableToLegalize; @@ -7856,9 +7692,7 @@ LegalizerHelper::lowerMemcpyInline(MachineInstr &MI) { assert(MI.getOpcode() == TargetOpcode::G_MEMCPY_INLINE); - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Len = MI.getOperand(2).getReg(); + Get3RegsFromMI(Dst, Src, Len, MI); const auto *MMOIt = MI.memoperands_begin(); const MachineMemOperand *MemOp = *MMOIt; @@ -8121,9 +7955,7 @@ Align DstAlign = MemOp->getBaseAlign(); Align SrcAlign; - Register Dst = MI.getOperand(0).getReg(); - Register Src = MI.getOperand(1).getReg(); - Register Len = MI.getOperand(2).getReg(); + Get3RegsFromMI(Dst, Src, Len, MI); if (Opc != TargetOpcode::G_MEMSET) { assert(MMOIt != MI.memoperands_end() && "Expected a second MMO on MI");