Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1003,8 +1003,8 @@ template bool isConstantUImm() const { return isConstantImm() && isUInt(getConstantImm() - Offset); } - template bool isUImm() const { - return isImm() && isConstantImm() && isUInt(getConstantImm()); + template bool isConstantSImm() const { + return isConstantImm() && isInt(getConstantImm()); } bool isToken() const override { // Note: It's not possible to pretend that other operand kinds are tokens. @@ -3647,6 +3647,15 @@ case Match_UImm5_Lsl2: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 7-bit unsigned immediate and multiple of 4"); + case Match_SImm6: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 6-bit signed immediate"); + case Match_UImm7_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 7-bit unsigned immediate"); + case Match_UImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 10-bit unsigned immediate"); } llvm_unreachable("Implement any new match types added!"); Index: lib/Target/Mips/MicroMipsDSPInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -16,6 +16,12 @@ let DecoderNamespace = "MicroMips"; } +class MMDSPInstAlias + : InstAlias, PredicateControl { + let InsnPredicates = [HasDSP]; + let AdditionalPredicates = [InMicroMips]; +} + class POOL32A_3R_FMT op> : MMDSPInst { bits<5> rd; bits<5> rs; @@ -212,3 +218,27 @@ let Inst{11-6} = op; let Inst{5-0} = 0b111100; } + +class POOL32A_4B0SHIFT6AC4B0_FMT op> : MMDSPInst { + bits<6> shift; + bits<2> ac; + + let Inst{31-26} = 0b000000; + let Inst{25-22} = 0b0000; + let Inst{21-16} = shift; + let Inst{15-14} = ac; + let Inst{13-10} = 0b0000; + let Inst{9-0} = op; +} + +class POOL32A_5B01RAC_FMT op> : MMDSPInst { + bits<5> rs; + bits<2> ac; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = 0b00000; + let Inst{20-16} = rs; + let Inst{15-14} = ac; + let Inst{13-6} = op; + let Inst{5-0} = 0b111100; +} Index: lib/Target/Mips/MicroMipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -149,6 +149,12 @@ class REPLV_PH_MM_ENC : POOL32A_2R_FMT<"replv.ph", 0b0000001100>; class REPLV_QB_MM_ENC : POOL32A_2R_FMT<"replv.qb", 0b0001001100>; class MTHLIP_MM_ENC : POOL32A_1RAC_FMT<"mthlip", 0b00001001>; +class PACKRL_PH_MM_ENC : POOL32A_3RB0_FMT<"packrl.ph", 0b0110101101>; +class PICK_PH_MM_ENC : POOL32A_3RB0_FMT<"pick.ph", 0b1000101101>; +class PICK_QB_MM_ENC : POOL32A_3RB0_FMT<"pick.qb", 0b0111101101>; +class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>; +class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>; +class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>; // Instruction desc. class ABSQ_S_PH_MM_R2_DESC_BASE; +class WRDSP_MM_DESC { + dag OutOperandList = (outs); + dag InOperandList = (ins GPR32Opnd:$rt, uimm7:$mask); + string AsmString = !strconcat("wrdsp", "\t$rt, $mask"); + list Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, immZExt7:$mask)]; + InstrItinClass Itinerary = NoItinerary; +} + +// Instruction defs. // microMIPS DSP Rev 1 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC; @@ -451,6 +466,12 @@ def REPLV_PH_MM : DspMMRel, REPLV_PH_MM_ENC, REPLV_PH_MM_DESC; def REPLV_QB_MM : DspMMRel, REPLV_QB_MM_ENC, REPLV_QB_MM_DESC; def MTHLIP_MM : DspMMRel, MTHLIP_MM_ENC, MTHLIP_DESC; +def PACKRL_PH_MM : DspMMRel, PACKRL_PH_MM_ENC, PACKRL_PH_DESC; +def PICK_PH_MM : DspMMRel, PICK_PH_MM_ENC, PICK_PH_DESC; +def PICK_QB_MM : DspMMRel, PICK_QB_MM_ENC, PICK_QB_DESC; +def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC; +def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC; +def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC; // microMIPS DSP Rev 2 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, ISA_DSPR2; @@ -502,3 +523,6 @@ def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2; def PREPEND_MMR2 : DspMMRel, PREPEND_MMR2_ENC, PREPEND_DESC, ISA_DSPR2; + +// Instruction alias. +def : MMDSPInstAlias<"wrdsp $rt", (WRDSP_MM GPR32Opnd:$rt, 0x1F), 1>; Index: lib/Target/Mips/MipsDSPInstrFormats.td =================================================================== --- lib/Target/Mips/MipsDSPInstrFormats.td +++ lib/Target/Mips/MipsDSPInstrFormats.td @@ -41,16 +41,21 @@ def REGIMM_OPCODE : Field6<0b000001>; class DSPInst - : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { - let Predicates = [HasDSP]; + : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { + let InsnPredicates = [HasDSP]; string BaseOpcode = opstr; string Arch = "dsp"; } class PseudoDSP pattern, - InstrItinClass itin = IIPseudo>: - MipsPseudo { - let Predicates = [HasDSP]; + InstrItinClass itin = IIPseudo> + : MipsPseudo, PredicateControl { + let InsnPredicates = [HasDSP]; +} + +class DSPInstAlias + : InstAlias, PredicateControl { + let InsnPredicates = [HasDSP]; } // ADDU.QB sub-class format. Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -16,6 +16,7 @@ def immZExt2 : ImmLeaf(Imm);}]>; def immZExt3 : ImmLeaf(Imm);}]>; def immZExt4 : ImmLeaf(Imm);}]>; +def immZExt7 : ImmLeaf(Imm);}]>; def immZExt8 : ImmLeaf(Imm);}]>; def immZExt10 : ImmLeaf(Imm);}]>; def immSExt6 : ImmLeaf(Imm);}]>; @@ -408,11 +409,12 @@ class SHILO_R1_DESC_BASE { dag OutOperandList = (outs ACC64DSPOpnd:$ac); - dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin); + dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin); string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); list Pattern = [(set ACC64DSPOpnd:$ac, (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))]; string Constraints = "$acin = $ac"; + string BaseOpcode = instr_asm; } class SHILO_R2_DESC_BASE { @@ -422,6 +424,7 @@ list Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))]; string Constraints = "$acin = $ac"; + string BaseOpcode = instr_asm; } class MTHLIP_DESC_BASE { @@ -447,10 +450,11 @@ class WRDSP_DESC_BASE { dag OutOperandList = (outs); - dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask); + dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask); string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); list Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)]; InstrItinClass Itinerary = itin; + string BaseOpcode = instr_asm; } class DPA_W_PH_DESC_BASE { @@ -1183,13 +1187,13 @@ def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; def BITREV : BITREV_ENC, BITREV_DESC; -def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; +def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC; def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC; def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC; def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC; def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC; -def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; -def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; +def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC; +def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC; def LWX : DspMMRel, LWX_ENC, LWX_DESC; def LHX : DspMMRel, LHX_ENC, LHX_DESC; def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC; @@ -1207,63 +1211,61 @@ def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC; def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC; -def SHILO : SHILO_ENC, SHILO_DESC; -def SHILOV : SHILOV_ENC, SHILOV_DESC; +def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC; +def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC; def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC; def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC; -def WRDSP : WRDSP_ENC, WRDSP_DESC; +let AdditionalPredicates = [NotInMicroMips] in { + def WRDSP : WRDSP_ENC, WRDSP_DESC; +} // MIPS DSP Rev 2 -let Predicates = [HasDSPR2] in { - -def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC; -def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC; -def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC; -def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC; -def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; -def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; -def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; -def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; -def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC; -def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; -def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC; -def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; -def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC; -def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; -def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC; -def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; -def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC; -def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC; -def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC; -def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC; -def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC; -def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC; -def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC; -def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC; -def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC; -def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC; -def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC; -def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; -def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; -def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC; -def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC; -def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; -def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; -def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; -def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; -def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; -def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; -def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC; -def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC; -def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC; -def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; -def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC; -def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC; -def APPEND : APPEND_ENC, APPEND_DESC; -def BALIGN : BALIGN_ENC, BALIGN_DESC; -def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC; - -} +def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2; +def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2; +def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2; +def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2; +def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2; +def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2; +def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2; +def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2; +def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2; +def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; +def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2; +def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2; +def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2; +def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; +def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2; +def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2; +def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2; +def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2; +def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2; +def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2; +def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2; +def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2; +def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2; +def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2; +def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2; +def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2; +def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2; +def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2; +def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2; +def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2; +def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2; +def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2; +def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2; +def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2; +def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2; +def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2; +def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2; +def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2; +def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2; +def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2; +def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2; +def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2; +def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2; +def APPEND : APPEND_ENC, APPEND_DESC, ISA_DSPR2; +def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2; +def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2; // Pseudos. let isPseudo = 1, isCodeGenOnly = 1 in { @@ -1442,3 +1444,8 @@ def : IndexedLoadPat; def : IndexedLoadPat; } + +// Instruction alias. +let AdditionalPredicates = [NotInMicroMips] in { + def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>; +} Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -385,6 +385,16 @@ // Mips Operand, Complex Patterns and Transformations Definitions. //===----------------------------------------------------------------------===// +class ConstantSImmAsmOperandClass Supers = []> + : AsmOperandClass { + let Name = "ConstantSImm" # Bits; + let RenderMethod = "addImmOperands"; + let ParserMethod = "parseImm"; + let PredicateMethod = "isConstantSImm<" # Bits # ">"; + let SuperClasses = Supers; + let DiagnosticType = "SImm" # Bits; +} + class ConstantUImmAsmOperandClass Supers = [], int Offset = 0> : AsmOperandClass { let Name = "ConstantUImm" # Bits # "_" # Offset; @@ -394,6 +404,12 @@ let DiagnosticType = "UImm" # Bits # "_" # Offset; } +def ConstantUImm10AsmOperandClass + : ConstantUImmAsmOperandClass<10, []>; +def ConstantUImm7AsmOperandClass + : ConstantUImmAsmOperandClass<7, [ConstantUImm10AsmOperandClass]>; +def ConstantSImm6AsmOperandClass + : ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; def ConstantUImm5Plus32NormalizeAsmOperandClass : ConstantUImmAsmOperandClass<5, [], 32> { // We must also subtract 32 when we render the operand. @@ -412,7 +428,8 @@ let DiagnosticType = "UImm5_0_Report_UImm6"; } def ConstantUImm5AsmOperandClass - : ConstantUImmAsmOperandClass<5, []>; + : ConstantUImmAsmOperandClass< + 5, [ConstantSImm6AsmOperandClass]>; def ConstantUImm4AsmOperandClass : ConstantUImmAsmOperandClass< 4, [ConstantUImm5AsmOperandClass, @@ -458,6 +475,10 @@ def imm64: Operand; +def simm6 : Operand { + let ParserMatchClass = ConstantSImm6AsmOperandClass; + let OperandType = "OPERAND_IMMEDIATE"; +} def simm9 : Operand; def simm10 : Operand; def simm11 : Operand; @@ -484,17 +505,6 @@ def uimm20 : Operand { } -def MipsUImm10AsmOperand : AsmOperandClass { - let Name = "UImm10"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseImm"; - let PredicateMethod = "isUImm<10>"; -} - -def uimm10 : Operand { - let ParserMatchClass = MipsUImm10AsmOperand; -} - def simm16_64 : Operand { let DecoderMethod = "DecodeSimm16"; } @@ -506,7 +516,7 @@ } // Unsigned Operands -foreach I = {1, 2, 3, 4, 5} in +foreach I = {1, 2, 3, 4, 5, 7, 10} in def uimm # I : Operand { let PrintMethod = "printUnsignedImm"; let ParserMatchClass = Index: test/MC/Disassembler/Mips/dsp/valid-el.txt =================================================================== --- test/MC/Disassembler/Mips/dsp/valid-el.txt +++ test/MC/Disassembler/Mips/dsp/valid-el.txt @@ -7,3 +7,6 @@ 0x8a 0x51 0x54 0x7f # CHECK: lbux $10, $20($26) 0x0a 0x59 0x75 0x7f # CHECK: lhx $11, $21($27) 0x0a 0x60 0x96 0x7f # CHECK: lwx $12, $22($gp) +0xb8 0x0e 0x30 0x7c # CHECK: shilo $ac1, 3 +0xf8 0x14 0xa0 0x7c # CHECK: wrdsp $5, 2 +0xf8 0xfc 0xa0 0x7c # CHECK: wrdsp $5 Index: test/MC/Disassembler/Mips/micromips-dsp/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips-dsp/valid.txt +++ test/MC/Disassembler/Mips/micromips-dsp/valid.txt @@ -32,6 +32,9 @@ 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13 0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3 0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5 +0x00 0xa4 0x19 0xad # CHECK: packrl.ph $3, $4, $5 +0x00 0xa4 0x1a 0x2d # CHECK: pick.ph $3, $4, $5 +0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5 0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2 0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4 0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6 @@ -46,6 +49,8 @@ 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13 0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16 0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19 +0x00 0x03 0x40 0x1d # CHECK: shilo $ac1, 3 +0x00 0x05 0x52 0x7c # CHECK: shilov $ac1, $5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 @@ -94,3 +99,5 @@ 0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2 0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2 0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2 +0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5 +0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2 Index: test/MC/Disassembler/Mips/micromips-dspr2/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips-dspr2/valid.txt +++ test/MC/Disassembler/Mips/micromips-dspr2/valid.txt @@ -45,6 +45,9 @@ 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13 0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3 0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5 +0x00 0xa4 0x19 0xad # CHECK: packrl.ph $3, $4, $5 +0x00 0xa4 0x1a 0x2d # CHECK: pick.ph $3, $4, $5 +0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5 0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2 0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4 0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6 @@ -62,6 +65,8 @@ 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13 0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16 0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19 +0x00 0x03 0x40 0x1d # CHECK: shilo $ac1, 3 +0x00 0x05 0x52 0x7c # CHECK: shilov $ac1, $5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 @@ -116,3 +121,5 @@ 0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3 0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3 0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3 +0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5 +0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2 Index: test/MC/Mips/dsp/invalid.s =================================================================== --- test/MC/Mips/dsp/invalid.s +++ test/MC/Mips/dsp/invalid.s @@ -19,3 +19,7 @@ shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate + shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate + shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate + wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate Index: test/MC/Mips/dsp/valid.s =================================================================== --- test/MC/Mips/dsp/valid.s +++ test/MC/Mips/dsp/valid.s @@ -101,6 +101,7 @@ repl.qb $1, 85 # CHECK: repl.qb $1, 85 # encoding: [0x7c,0x55,0x08,0x92] replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x7c,0x02,0x0a,0xd2] replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x7c,0x02,0x08,0xd2] + shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x7c,0x30,0x0e,0xb8] shilo $ac1, 16 # CHECK: shilo $ac1, 16 # encoding: [0x7d,0x00,0x0e,0xb8] shilov $ac1, $2 # CHECK: shilov $ac1, $2 # encoding: [0x7c,0x40,0x0e,0xf8] shll.ph $1, $2, 3 # CHECK: shll.ph $1, $2, 3 # encoding: [0x7c,0x62,0x0a,0x13] @@ -125,3 +126,6 @@ subu.qb $1, $2, $3 # CHECK: subu.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0x50] subu_s.qb $1, $2, $3 # CHECK: subu_s.qb $1, $2, $3 # encoding: [0x7c,0x43,0x09,0x50] wrdsp $1, 0 # CHECK: wrdsp $1, 0 # encoding: [0x7c,0x20,0x04,0xf8] + wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8] + wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x7c,0xa0,0x14,0xf8] + wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8] Index: test/MC/Mips/dspr2/valid.s =================================================================== --- test/MC/Mips/dspr2/valid.s +++ test/MC/Mips/dspr2/valid.s @@ -135,6 +135,7 @@ repl.qb $1, 85 # CHECK: repl.qb $1, 85 # encoding: [0x7c,0x55,0x08,0x92] replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x7c,0x02,0x0a,0xd2] replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x7c,0x02,0x08,0xd2] + shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x7c,0x30,0x0e,0xb8] shilo $ac1, 16 # CHECK: shilo $ac1, 16 # encoding: [0x7d,0x00,0x0e,0xb8] shilov $ac1, $2 # CHECK: shilov $ac1, $2 # encoding: [0x7c,0x40,0x0e,0xf8] shll.ph $1, $2, 3 # CHECK: shll.ph $1, $2, 3 # encoding: [0x7c,0x62,0x0a,0x13] @@ -173,3 +174,6 @@ subuh.qb $1, $2, $3 # CHECK: subuh.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0x58] subuh_r.qb $1, $2, $3 # CHECK: subuh_r.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0xd8] wrdsp $1, 0 # CHECK: wrdsp $1, 0 # encoding: [0x7c,0x20,0x04,0xf8] + wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8] + wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x7c,0xa0,0x14,0xf8] + wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8] Index: test/MC/Mips/micromips-dsp/invalid-wrong-error.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips-dsp/invalid-wrong-error.s @@ -0,0 +1,9 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + wrdsp $5, 128 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate Index: test/MC/Mips/micromips-dsp/invalid.s =================================================================== --- test/MC/Mips/micromips-dsp/invalid.s +++ test/MC/Mips/micromips-dsp/invalid.s @@ -19,3 +19,5 @@ shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate + shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate + shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate Index: test/MC/Mips/micromips-dsp/valid.s =================================================================== --- test/MC/Mips/micromips-dsp/valid.s +++ test/MC/Mips/micromips-dsp/valid.s @@ -33,6 +33,9 @@ msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc] mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc] multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc] + packrl.ph $3, $4, $5 # CHECK: packrl.ph $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xad] + pick.ph $3, $4, $5 # CHECK: pick.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x2d] + pick.qb $3, $4, $5 # CHECK: pick.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xed] preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c] preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c] precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c] @@ -47,6 +50,8 @@ precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad] precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d] precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d] + shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x00,0x03,0x40,0x1d] + shilov $ac1, $5 # CHECK: shilov $ac1, $5 # encoding: [0x00,0x05,0x52,0x7c] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] @@ -95,3 +100,6 @@ replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x00,0x22,0x03,0x3c] replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x00,0x22,0x13,0x3c] mthlip $1, $ac2 # CHECK: mthlip $1, $ac2 # encoding: [0x00,0x01,0x82,0x7c] + wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] + wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c] + wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] Index: test/MC/Mips/micromips-dspr2/valid.s =================================================================== --- test/MC/Mips/micromips-dspr2/valid.s +++ test/MC/Mips/micromips-dspr2/valid.s @@ -46,6 +46,9 @@ msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc] mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc] multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc] + packrl.ph $3, $4, $5 # CHECK: packrl.ph $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xad] + pick.ph $3, $4, $5 # CHECK: pick.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x2d] + pick.qb $3, $4, $5 # CHECK: pick.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xed] preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c] preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c] precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c] @@ -63,6 +66,8 @@ precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad] precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d] precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d] + shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x00,0x03,0x40,0x1d] + shilov $ac1, $5 # CHECK: shilov $ac1, $5 # encoding: [0x00,0x05,0x52,0x7c] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] @@ -117,3 +122,6 @@ muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5] mulq_rs.ph $1, $2, $3 # CHECK: mulq_rs.ph $1, $2, $3 # encoding: [0x00,0x62,0x09,0x15] prepend $1, $2, 3 # CHECK: prepend $1, $2, 3 # encoding: [0x00,0x22,0x1a,0x55] + wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] + wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c] + wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] Index: test/MC/Mips/micromips-invalid.s =================================================================== --- test/MC/Mips/micromips-invalid.s +++ test/MC/Mips/micromips-invalid.s @@ -75,11 +75,11 @@ movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate + break 1024, 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate jraddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -16,8 +16,8 @@ bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate Index: test/MC/Mips/mips32r6/invalid.s =================================================================== --- test/MC/Mips/mips32r6/invalid.s +++ test/MC/Mips/mips32r6/invalid.s @@ -15,10 +15,10 @@ ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate + break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips64r6/invalid.s =================================================================== --- test/MC/Mips/mips64r6/invalid.s +++ test/MC/Mips/mips64r6/invalid.s @@ -13,10 +13,10 @@ jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate + break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction