Index: llvm/lib/Analysis/InstructionSimplify.cpp =================================================================== --- llvm/lib/Analysis/InstructionSimplify.cpp +++ llvm/lib/Analysis/InstructionSimplify.cpp @@ -3931,6 +3931,10 @@ if (Value *V = simplifyICmpWithDominatingAssume(Pred, LHS, RHS, Q)) return V; + if (std::optional Res = + isImpliedByDomCondition(Pred, LHS, RHS, Q.CxtI, Q.DL)) + return ConstantInt::getBool(ITy, *Res); + // Simplify comparisons of related pointers using a powerful, recursive // GEP-walk when we have target data available.. if (LHS->getType()->isPointerTy()) @@ -6152,13 +6156,6 @@ if (isICmpTrue(Pred, Op1, Op0, Q.getWithoutUndef(), RecursionLimit)) return Op1; - if (std::optional Imp = - isImpliedByDomCondition(Pred, Op0, Op1, Q.CxtI, Q.DL)) - return *Imp ? Op0 : Op1; - if (std::optional Imp = - isImpliedByDomCondition(Pred, Op1, Op0, Q.CxtI, Q.DL)) - return *Imp ? Op1 : Op0; - break; } case Intrinsic::usub_with_overflow: Index: llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp =================================================================== --- llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1411,11 +1411,8 @@ if (TrueBB == FalseBB) return nullptr; - // Try to simplify this compare to T/F based on the dominating condition. - std::optional Imp = - isImpliedCondition(DomCond, &Cmp, DL, TrueBB == CmpBB); - if (Imp) - return replaceInstUsesWith(Cmp, ConstantInt::get(Cmp.getType(), *Imp)); + // We already checked simple implication in InstSimplify, only handle complex + // cases here. CmpInst::Predicate Pred = Cmp.getPredicate(); Value *X = Cmp.getOperand(0), *Y = Cmp.getOperand(1); Index: llvm/test/CodeGen/AMDGPU/branch-relaxation.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll +++ llvm/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -501,12 +501,6 @@ ; GCN: [[LONG_BR_DEST0]]: -; GCN-DAG: s_cmp_lt_i32 -; GCN-DAG: s_cmp_ge_i32 - -; GCN: s_cbranch_vccz -; GCN: s_setpc_b64 - ; GCN: s_endpgm define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 { bb: Index: llvm/test/CodeGen/AMDGPU/collapse-endcf.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll +++ llvm/test/CodeGen/AMDGPU/collapse-endcf.ll @@ -233,12 +233,6 @@ ; GCN-NEXT: s_cbranch_execz [[THEN_OUTER:.LBB[0-9_]+]] ; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN: store_dword -; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]] -; GCN-NEXT: s_cbranch_execz [[THEN_OUTER_FLOW:.LBB[0-9_]+]] -; GCN-NEXT: ; %bb.{{[0-9]+}}: -; GCN: store_dword -; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]: -; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]] ; GCN: {{^}}[[THEN_OUTER]]: ; GCN-NEXT: s_andn2_saveexec_b64 [[SAVEEXEC_OUTER2]], [[SAVEEXEC_OUTER2]] ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:.LBB[0-9_]+]] Index: llvm/test/CodeGen/AMDGPU/infinite-loop.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/infinite-loop.ll +++ llvm/test/CodeGen/AMDGPU/infinite-loop.ll @@ -1,4 +1,3 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s ; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s @@ -149,33 +148,21 @@ ; SI: ; %bb.0: ; %entry ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc -; SI-NEXT: s_cbranch_execz .LBB3_5 +; SI-NEXT: s_cbranch_execz .LBB3_3 ; SI-NEXT: ; %bb.1: ; %outer_loop.preheader -; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 -; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0 -; SI-NEXT: s_mov_b32 s7, 0xf000 -; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 +; SI-NEXT: s_and_b64 vcc, exec, -1 ; SI-NEXT: .LBB3_2: ; %outer_loop -; SI-NEXT: ; =>This Loop Header: Depth=1 -; SI-NEXT: ; Child Loop BB3_3 Depth 2 -; SI-NEXT: s_mov_b64 s[2:3], 0 -; SI-NEXT: .LBB3_3: ; %inner_loop -; SI-NEXT: ; Parent Loop BB3_2 Depth=1 -; SI-NEXT: ; => This Inner Loop Header: Depth=2 -; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1] -; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] +; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] -; SI-NEXT: s_cbranch_execnz .LBB3_3 -; SI-NEXT: ; %bb.4: ; %loop.exit.guard -; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1 -; SI-NEXT: s_or_b64 exec, exec, s[2:3] -; SI-NEXT: s_mov_b64 vcc, 0 -; SI-NEXT: s_branch .LBB3_2 -; SI-NEXT: .LBB3_5: ; %UnifiedReturnBlock +; SI-NEXT: s_mov_b64 vcc, vcc +; SI-NEXT: s_cbranch_vccnz .LBB3_2 +; SI-NEXT: .LBB3_3: ; %UnifiedReturnBlock ; SI-NEXT: s_endpgm ; IR-LABEL: @infinite_loop_nest_ret( ; IR-NEXT: entry: Index: llvm/test/CodeGen/AMDGPU/uniform-cfg.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -398,15 +398,14 @@ ; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks: ; GCN: s_load_dword [[COND:s[0-9]+]] ; GCN: s_cmp_lt_i32 [[COND]], 1 -; GCN: s_cbranch_scc1 .LBB[[FNNUM:[0-9]+]]_3 +; GCN: s_cbranch_scc1 .LBB[[FNNUM:[0-9]+]]_2 ; GCN: %bb.1: ; GCN-NOT: cmp ; GCN: buffer_load_dword ; GCN: buffer_store_dword -; GCN: s_cbranch_scc1 .LBB[[FNNUM]]_3 -; GCN: .LBB[[FNNUM]]_3: +; GCN: .LBB[[FNNUM]]_2: ; GCN: s_endpgm define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, ptr addrspace(1) %out) { bb: Index: llvm/test/CodeGen/Thumb2/mve-memtp-branch.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-memtp-branch.ll +++ llvm/test/CodeGen/Thumb2/mve-memtp-branch.ll @@ -97,97 +97,9 @@ ; CHECK-NEXT: vstrb.8 q3, [r3], #16 ; CHECK-NEXT: letp lr, .LBB0_11 ; CHECK-NEXT: b .LBB0_2 -; CHECK-NEXT: .LBB0_12: -; CHECK-NEXT: movw r12, :lower16:arr_183 -; CHECK-NEXT: vmov.i32 q0, #0x0 -; CHECK-NEXT: movt r12, :upper16:arr_183 -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: b .LBB0_14 -; CHECK-NEXT: .LBB0_13: @ %for.body.lr.ph.3 -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: ldr r3, [r2, #4] -; CHECK-NEXT: cmp r3, #0 -; CHECK-NEXT: ite ne -; CHECK-NEXT: ldrbne r3, [r1, #1] -; CHECK-NEXT: moveq r3, #0 -; CHECK-NEXT: add.w r5, r12, r3 -; CHECK-NEXT: rsb.w r3, r3, #108 -; CHECK-NEXT: add.w r4, r5, #19 -; CHECK-NEXT: wlstp.8 lr, r3, .LBB0_14 -; CHECK-NEXT: b .LBB0_24 -; CHECK-NEXT: .LBB0_14: @ %for.cond -; CHECK-NEXT: @ =>This Loop Header: Depth=1 -; CHECK-NEXT: @ Child Loop BB0_16 Depth 2 -; CHECK-NEXT: @ Child Loop BB0_19 Depth 2 -; CHECK-NEXT: @ Child Loop BB0_22 Depth 2 -; CHECK-NEXT: @ Child Loop BB0_24 Depth 2 -; CHECK-NEXT: cmp r0, #2 -; CHECK-NEXT: blo .LBB0_17 -; CHECK-NEXT: @ %bb.15: @ %for.body.lr.ph -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: ldr r3, [r2, #4] -; CHECK-NEXT: cmp r3, #0 -; CHECK-NEXT: ite ne -; CHECK-NEXT: ldrbne r3, [r1, #1] -; CHECK-NEXT: moveq r3, #0 -; CHECK-NEXT: add.w r5, r12, r3 -; CHECK-NEXT: rsb.w r3, r3, #108 -; CHECK-NEXT: add.w r4, r5, #19 -; CHECK-NEXT: wlstp.8 lr, r3, .LBB0_17 -; CHECK-NEXT: .LBB0_16: @ Parent Loop BB0_14 Depth=1 -; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vstrb.8 q0, [r4], #16 -; CHECK-NEXT: letp lr, .LBB0_16 -; CHECK-NEXT: .LBB0_17: @ %for.cond.backedge -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: cmp r0, #2 -; CHECK-NEXT: blo .LBB0_20 -; CHECK-NEXT: @ %bb.18: @ %for.body.lr.ph.1 -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: ldr r3, [r2, #4] -; CHECK-NEXT: cmp r3, #0 -; CHECK-NEXT: ite ne -; CHECK-NEXT: ldrbne r3, [r1, #1] -; CHECK-NEXT: moveq r3, #0 -; CHECK-NEXT: add.w r5, r12, r3 -; CHECK-NEXT: rsb.w r3, r3, #108 -; CHECK-NEXT: add.w r4, r5, #19 -; CHECK-NEXT: wlstp.8 lr, r3, .LBB0_20 -; CHECK-NEXT: .LBB0_19: @ Parent Loop BB0_14 Depth=1 -; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vstrb.8 q1, [r4], #16 -; CHECK-NEXT: letp lr, .LBB0_19 -; CHECK-NEXT: .LBB0_20: @ %for.cond.backedge.1 -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: cmp r0, #2 -; CHECK-NEXT: blo .LBB0_23 -; CHECK-NEXT: @ %bb.21: @ %for.body.lr.ph.2 -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: ldr r3, [r2, #4] -; CHECK-NEXT: cmp r3, #0 -; CHECK-NEXT: ite ne -; CHECK-NEXT: ldrbne r3, [r1, #1] -; CHECK-NEXT: moveq r3, #0 -; CHECK-NEXT: add.w r5, r12, r3 -; CHECK-NEXT: rsb.w r3, r3, #108 -; CHECK-NEXT: add.w r4, r5, #19 -; CHECK-NEXT: wlstp.8 lr, r3, .LBB0_23 -; CHECK-NEXT: .LBB0_22: @ Parent Loop BB0_14 Depth=1 -; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vstrb.8 q2, [r4], #16 -; CHECK-NEXT: letp lr, .LBB0_22 -; CHECK-NEXT: .LBB0_23: @ %for.cond.backedge.2 -; CHECK-NEXT: @ in Loop: Header=BB0_14 Depth=1 -; CHECK-NEXT: cmp r0, #2 -; CHECK-NEXT: blo .LBB0_14 -; CHECK-NEXT: b .LBB0_13 -; CHECK-NEXT: .LBB0_24: @ Parent Loop BB0_14 Depth=1 -; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vstrb.8 q3, [r4], #16 -; CHECK-NEXT: letp lr, .LBB0_24 -; CHECK-NEXT: b .LBB0_14 +; CHECK-NEXT: .LBB0_12: @ %for.cond +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: b .LBB0_12 entry: %cmp = icmp ugt i8 %b, 1 br i1 %cmp, label %for.body.us.preheader, label %for.cond.preheader Index: llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll =================================================================== --- llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll +++ llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll @@ -144,7 +144,6 @@ ; CHECK-NEXT: br i1 [[CMP]], label [[RETURN:%.*]], label [[IF_END:%.*]] ; CHECK: if.end: ; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[X]], i1 true) -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: br label [[RETURN]] ; CHECK: return: ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[TMP0]], [[IF_END]] ], [ 32, [[ENTRY:%.*]] ] Index: llvm/test/Transforms/InstCombine/urem-via-cmp-select.ll =================================================================== --- llvm/test/Transforms/InstCombine/urem-via-cmp-select.ll +++ llvm/test/Transforms/InstCombine/urem-via-cmp-select.ll @@ -103,12 +103,64 @@ ret i8 %out } -; TODO: https://alive2.llvm.org/ce/z/eHkgRa +; https://alive2.llvm.org/ce/z/eHkgRa define i8 @urem_with_dominating_condition(i8 %x, i8 %n) { ; CHECK-LABEL: @urem_with_dominating_condition( -; CHECK-NEXT: [[COND:%.*]] = icmp ult i8 [[X:%.*]], [[N:%.*]] +; CHECK-NEXT: start: +; CHECK-NEXT: [[X_FR:%.*]] = freeze i8 [[X:%.*]] +; CHECK-NEXT: [[COND:%.*]] = icmp ult i8 [[X_FR]], [[N:%.*]] ; CHECK-NEXT: br i1 [[COND]], label [[DOTBB0:%.*]], label [[DOTBB1:%.*]] ; CHECK: .bb0: +; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X_FR]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[ADD]], [[N]] +; CHECK-NEXT: [[OUT:%.*]] = select i1 [[TMP0]], i8 0, i8 [[ADD]] +; CHECK-NEXT: ret i8 [[OUT]] +; CHECK: .bb1: +; CHECK-NEXT: ret i8 0 +; +start: + %cond = icmp ult i8 %x, %n + br i1 %cond, label %.bb0, label %.bb1 ; Should also works for a dominating condition +.bb0: + %add = add i8 %x, 1 + %out = urem i8 %add, %n + ret i8 %out +.bb1: + ret i8 0 +} + +; Revert the dominating condition and target branch at the same time. +define i8 @urem_with_dominating_condition_false(i8 %x, i8 %n) { +; CHECK-LABEL: @urem_with_dominating_condition_false( +; CHECK-NEXT: start: +; CHECK-NEXT: [[X_FR:%.*]] = freeze i8 [[X:%.*]] +; CHECK-NEXT: [[COND_NOT:%.*]] = icmp ult i8 [[X_FR]], [[N:%.*]] +; CHECK-NEXT: br i1 [[COND_NOT]], label [[DOTBB0:%.*]], label [[DOTBB1:%.*]] +; CHECK: .bb0: +; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X_FR]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[ADD]], [[N]] +; CHECK-NEXT: [[OUT:%.*]] = select i1 [[TMP0]], i8 0, i8 [[ADD]] +; CHECK-NEXT: ret i8 [[OUT]] +; CHECK: .bb1: +; CHECK-NEXT: ret i8 0 +; +start: + %cond = icmp uge i8 %x, %n + br i1 %cond, label %.bb1, label %.bb0 ; Swap the branch targets +.bb0: + %add = add i8 %x, 1 + %out = urem i8 %add, %n + ret i8 %out +.bb1: + ret i8 0 +} + +; Negative test +define noundef i8 @urem_with_opposite_condition(i8 %x, i8 %n) { +; CHECK-LABEL: @urem_with_opposite_condition( +; CHECK-NEXT: [[COND:%.*]] = icmp ult i8 [[X:%.*]], [[N:%.*]] +; CHECK-NEXT: br i1 [[COND]], label [[DOTBB1:%.*]], label [[DOTBB0:%.*]] +; CHECK: .bb0: ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X]], 1 ; CHECK-NEXT: [[OUT:%.*]] = urem i8 [[ADD]], [[N]] ; CHECK-NEXT: ret i8 [[OUT]] @@ -116,7 +168,7 @@ ; CHECK-NEXT: ret i8 0 ; %cond = icmp ult i8 %x, %n - br i1 %cond, label %.bb0, label %.bb1 ; Should also works for a dominating condition + br i1 %cond, label %.bb1, label %.bb0 ; Revert the condition .bb0: %add = add i8 %x, 1 %out = urem i8 %add, %n Index: llvm/test/Transforms/InstSimplify/select-implied.ll =================================================================== --- llvm/test/Transforms/InstSimplify/select-implied.ll +++ llvm/test/Transforms/InstSimplify/select-implied.ll @@ -108,8 +108,7 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[LEN]], 4 ; CHECK-NEXT: br i1 [[CMP]], label [[BB:%.*]], label [[B1:%.*]] ; CHECK: bb: -; CHECK-NEXT: [[CMP11:%.*]] = icmp eq i32 [[LEN]], 8 -; CHECK-NEXT: br i1 [[CMP11]], label [[B0:%.*]], label [[B1]] +; CHECK-NEXT: br i1 false, label [[B0:%.*]], label [[B1]] ; CHECK: b0: ; CHECK-NEXT: call void @foo(i32 [[LEN]]) ; CHECK-NEXT: br label [[B1]] @@ -399,9 +398,7 @@ ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: br i1 [[CMP1]], label [[END:%.*]], label [[TAKEN:%.*]] ; CHECK: taken: -; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[A]], [[B]] -; CHECK-NEXT: [[OR:%.*]] = and i1 [[CMP2]], [[X:%.*]] -; CHECK-NEXT: [[C:%.*]] = select i1 [[OR]], i32 20, i32 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[X:%.*]], i32 20, i32 0 ; CHECK-NEXT: call void @foo(i32 [[C]]) ; CHECK-NEXT: br label [[END]] ; CHECK: end: @@ -546,9 +543,7 @@ ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: br i1 [[CMP1]], label [[END:%.*]], label [[TAKEN:%.*]] ; CHECK: taken: -; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[A]], [[B]] -; CHECK-NEXT: [[AND:%.*]] = or i1 [[CMP2]], [[X:%.*]] -; CHECK-NEXT: [[C:%.*]] = select i1 [[AND]], i32 20, i32 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[X:%.*]], i32 20, i32 0 ; CHECK-NEXT: call void @foo(i32 [[C]]) ; CHECK-NEXT: br label [[END]] ; CHECK: end: Index: llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll =================================================================== --- llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll +++ llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll @@ -214,8 +214,7 @@ ; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1]], ptr [[DST]], align 8 ; CHECK-NEXT: [[INNER_1_IV_NEXT:%.*]] = add i64 [[INNER_1_IV]], 1 -; CHECK-NEXT: [[CMP_1_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0 -; CHECK-NEXT: br i1 [[CMP_1_1]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]] +; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]] ; CHECK: inner.1.latch.1: ; CHECK-NEXT: [[L_1_1:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_1]], ptr [[DST]], align 8 @@ -226,8 +225,7 @@ ; CHECK-NEXT: [[L_1_2:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_2]], ptr [[DST]], align 8 ; CHECK-NEXT: [[INNER_1_IV_NEXT_2:%.*]] = add i64 [[INNER_1_IV_NEXT_1]], 1 -; CHECK-NEXT: [[CMP_1_3:%.*]] = icmp sgt i32 [[OUTER_P]], 0 -; CHECK-NEXT: br i1 [[CMP_1_3]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]] +; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]] ; CHECK: inner.1.latch.3: ; CHECK-NEXT: [[L_1_3:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_3]], ptr [[DST]], align 8 @@ -238,8 +236,7 @@ ; CHECK-NEXT: [[L_1_4:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_4]], ptr [[DST]], align 8 ; CHECK-NEXT: [[INNER_1_IV_NEXT_4:%.*]] = add i64 [[INNER_1_IV_NEXT_3]], 1 -; CHECK-NEXT: [[CMP_1_5:%.*]] = icmp sgt i32 [[OUTER_P]], 0 -; CHECK-NEXT: br i1 [[CMP_1_5]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]] +; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]] ; CHECK: inner.1.latch.5: ; CHECK-NEXT: [[L_1_5:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_5]], ptr [[DST]], align 8 @@ -250,8 +247,7 @@ ; CHECK-NEXT: [[L_1_6:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_6]], ptr [[DST]], align 8 ; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add i64 [[INNER_1_IV_NEXT_5]], 1 -; CHECK-NEXT: [[CMP_1_7:%.*]] = icmp sgt i32 [[OUTER_P]], 0 -; CHECK-NEXT: br i1 [[CMP_1_7]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]] +; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]] ; CHECK: inner.1.latch.7: ; CHECK-NEXT: [[L_1_7:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8 Index: llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll =================================================================== --- llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll +++ llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll @@ -25,8 +25,7 @@ ; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]] ; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 -; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 -; ENABLED-NEXT: br i1 [[CMP_1]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_1:%.*]] +; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_1:%.*]] ; ENABLED: for.body.1: ; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]] ; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 @@ -41,8 +40,7 @@ ; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]] ; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1 -; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 -; ENABLED-NEXT: br i1 [[CMP_3]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_3:%.*]] +; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_3:%.*]] ; ENABLED: for.body.3: ; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]] ; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 @@ -57,8 +55,7 @@ ; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]] ; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1 -; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 -; ENABLED-NEXT: br i1 [[CMP_5]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_5:%.*]] +; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_5:%.*]] ; ENABLED: for.body.5: ; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]] ; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4 @@ -73,8 +70,7 @@ ; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]] ; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1 -; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 -; ENABLED-NEXT: br i1 [[CMP_7]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_7]] +; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_7]] ; ENABLED: for.body.7: ; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]] ; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4