diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/ELF_aarch32.h b/llvm/include/llvm/ExecutionEngine/JITLink/ELF_aarch32.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/ExecutionEngine/JITLink/ELF_aarch32.h @@ -0,0 +1,37 @@ +//===--- ELF_arm.h - JIT link functions for 32-bit arm/thumb ---*- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// jit-link functions for ELF/arm. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_EXECUTIONENGINE_JITLINK_ELF_ARM_H +#define LLVM_EXECUTIONENGINE_JITLINK_ELF_ARM_H + +#include "llvm/ExecutionEngine/JITLink/JITLink.h" + +namespace llvm { +namespace jitlink { + +/// Create a LinkGraph from an ELF/arm relocatable object +/// +/// Note: The graph does not take ownership of the underlying buffer, nor copy +/// its contents. The caller is responsible for ensuring that the object buffer +/// outlives the graph. +Expected> +createLinkGraphFromELFObject_arm(MemoryBufferRef ObjectBuffer); + +/// jit-link the given object buffer, which must be an ELF arm/thumb object +/// file. +void link_ELF_arm(std::unique_ptr G, + std::unique_ptr Ctx); + +} // end namespace jitlink +} // end namespace llvm + +#endif // LLVM_EXECUTIONENGINE_JITLINK_ELF_ARM_H diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h b/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h --- a/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h +++ b/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h @@ -448,7 +448,7 @@ orc::ExecutorAddrDiff Offset, orc::ExecutorAddrDiff Size, bool IsCallable, bool IsLive) { - assert((Offset + Size) <= Base.getSize() && + assert(((Offset & ~0x1) + Size) <= Base.getSize() && "Symbol extends past end of block"); auto *Sym = Allocator.Allocate(); new (Sym) Symbol(Base, Offset, StringRef(), Size, Linkage::Strong, @@ -460,7 +460,17 @@ orc::ExecutorAddrDiff Offset, StringRef Name, orc::ExecutorAddrDiff Size, Linkage L, Scope S, bool IsLive, bool IsCallable) { - assert((Offset + Size) <= Base.getSize() && + // + // On ARM the least significant bit (LSB) in a branch offset tells the CPU + // whether the subsequent code is ARM (LSB=0) or Thumb (LSB=1). It's not + // part of the range, but we need to maintain the exact value. This can + // break the below assertion. + // + // FIXME: Named definitions will rarely be entirely unaligned, so it might + // be acceptable to ignore the LSB for the size assertion here, until we + // find a better solution. + // + assert(((Offset & ~0x1) + Size) <= Base.getSize() && "Symbol extends past end of block"); assert(!Name.empty() && "Name cannot be empty"); auto *Sym = Allocator.Allocate(); diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h @@ -0,0 +1,292 @@ +//===-- arm.h - Generic JITLink arm/thumb edge kinds, utilities -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Generic utilities for graphs representing arm/thumb objects. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_EXECUTIONENGINE_JITLINK_ARM_H +#define LLVM_EXECUTIONENGINE_JITLINK_ARM_H + +#include "TableManager.h" +#include "llvm/ExecutionEngine/JITLink/JITLink.h" +#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h" +#include "llvm/Support/ARMBuildAttributes.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/Error.h" + +#include + +namespace llvm { +namespace jitlink { +namespace arm { + +/// AArch32 fixup types +enum EdgeKind_arm : Edge::Kind { + + /// + /// Relocations of class Data + /// + FirstDataRelocation = Edge::FirstRelocation, + + /// Plain 32-bit value relocation in target endianness + Data_Delta32 = FirstDataRelocation, + + LastDataRelocation = Data_Delta32, + + /// + /// Relocations of class Arm (covers fixed-width 4-byte instruction subset) + /// + FirstArmRelocation, + + Arm_Call = FirstArmRelocation, + + LastArmRelocation = Arm_Call, + + /// + /// Relocations of class Thumb16 and Thumb32 (covers Thumb instruction subset) + /// + FirstThumbRelocation, + + /// Write immediate value for PC-relative branch with link (can bridge between + /// ARM and Thumb). + Thumb_Call = FirstThumbRelocation, + + /// Write immediate value for (unconditional) PC-relative branch without link. + Thumb_Jump24, + + /// Write immediate value to the lower halfword of the destination register + Thumb_MovwAbsNC, + + /// Write immediate value to the top halfword of the destination register + Thumb_MovtAbs, + + LastThumbRelocation = Thumb_MovtAbs, +}; + +/// Human-readable name for a given edge +const char *getEdgeKindName(Edge::Kind K); + +/// Human-readable name for a given CPU architecture kind +const char *getCPUArchName(ARMBuildAttrs::CPUArch K); + +/// AArch32 uses stubs for a number of purposes, like branch range extension +/// or interworking between instruction subsets ARM and Thumb. +/// +/// Stub implementations vary depending on CPU architecture (v4, v6, v7), +/// instruction subset and branch type (absolute/PC-relative). +/// +/// For each kind of stub, the StubsFlavor defines one concrete form that is +/// used throughout the LinkGraph. +/// +/// Stubs are often called "veneers" in the official docs and online. +/// +enum StubsFlavor { + Unsupported = 0, + Thumbv7, +}; + +/// JITLink sub-arch configuration for ARM CPU models +struct ArmConfig { + bool HasBlx = false; + bool HasMovtMovw = false; + bool J1J2BranchEncoding = false; + StubsFlavor Stubs = Unsupported; +}; + +/// Obtain the sub-arch configuration for a given ARM CPU model. +inline ArmConfig getArmConfigForCPUArch(ARMBuildAttrs::CPUArch CPUArch) { + ArmConfig ArmCfg; + switch (CPUArch) { + case ARMBuildAttrs::v7: + case ARMBuildAttrs::v8_A: + ArmCfg.HasBlx = true; + ArmCfg.J1J2BranchEncoding = true; + ArmCfg.HasMovtMovw = true; + ArmCfg.Stubs = Thumbv7; + break; + default: + DEBUG_WITH_TYPE("jitlink", { + dbgs() << " Warning: ARM config not defined for CPU architecture " + << getCPUArchName(CPUArch); + }); + break; + } + return ArmCfg; +} + +/// Immutable pair of halfwords, Hi and Lo, with overflow check +struct HalfWords { + constexpr HalfWords() : Hi(0), Lo(0) {} + constexpr HalfWords(uint32_t Hi, uint32_t Lo) : Hi(Hi), Lo(Lo) { + assert(isUInt<16>(Hi) && "Overflow in first half-word"); + assert(isUInt<16>(Lo) && "Overflow in second half-word"); + } + const uint16_t Hi; // First halfword + const uint16_t Lo; // Second halfword +}; + +template struct FixupInfo {}; + +template <> struct FixupInfo { + static constexpr HalfWords Opcode{0xf000, 0x8000}; + static constexpr HalfWords OpcodeMask{0xf800, 0x8000}; + static constexpr HalfWords ImmMask{0x07ff, 0x2fff}; + static constexpr uint16_t LoBitConditional = 0x1000; +}; + +template <> struct FixupInfo { + static constexpr HalfWords Opcode{0xf000, 0xc000}; + static constexpr HalfWords OpcodeMask{0xf800, 0xc000}; + static constexpr HalfWords ImmMask{0x07ff, 0x2fff}; + static constexpr uint16_t LoBitH = 0x0001; + static constexpr uint16_t LoBitNoBlx = 0x1000; +}; + +template <> struct FixupInfo { + static constexpr HalfWords Opcode{0xf2c0, 0x0000}; + static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000}; + static constexpr HalfWords ImmMask{0x040f, 0x70ff}; + static constexpr HalfWords RegMask{0x0000, 0x0f00}; +}; + +template <> +struct FixupInfo : public FixupInfo { + static constexpr HalfWords Opcode{0xf240, 0x0000}; +}; + +std::optional> readAddendData(Edge::Kind Kind, + const char *FixupPtr, + support::endianness Endian); +std::optional> readAddendArm(Edge::Kind Kind, + const char *FixupPtr); +std::optional> +readAddendThumb(Edge::Kind Kind, const char *FixupPtr, const ArmConfig &ArmCfg); + +inline Expected readAddend(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg) { + Edge::Kind Kind = E.getKind(); + const char *BlockWorkingMem = B.getContent().data(); + const char *FixupPtr = BlockWorkingMem + E.getOffset(); + + if (Kind <= LastDataRelocation) { + if (auto AddendOrErr = readAddendData(Kind, FixupPtr, G.getEndianness())) + return std::move(*AddendOrErr); + + } else if (Kind <= LastArmRelocation) { + if (auto AddendOrErr = readAddendArm(Kind, FixupPtr)) + return std::move(*AddendOrErr); + + } else if (Kind <= LastThumbRelocation) { + if (auto AddendOrErr = readAddendThumb(Kind, FixupPtr, ArmCfg)) + return std::move(*AddendOrErr); + } + + return make_error( + "In graph " + G.getName() + ", section " + B.getSection().getName() + + " unsupported edge kind " + getEdgeKindName(Kind)); +} + +std::optional applyFixupData(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg); +std::optional applyFixupArm(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg); +std::optional applyFixupThumb(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg); + +/// Apply fixup expression for edge to block content. +inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg) { + Edge::Kind Kind = E.getKind(); + if (Kind <= LastDataRelocation) { + if (std::optional Err = applyFixupData(G, B, E, ArmCfg)) + return std::move(*Err); + + } else if (Kind <= LastArmRelocation) { + if (std::optional Err = applyFixupArm(G, B, E, ArmCfg)) + return std::move(*Err); + + } else if (Kind <= LastThumbRelocation) { + if (std::optional Err = applyFixupThumb(G, B, E, ArmCfg)) + return std::move(*Err); + } + + return make_error( + "In graph " + G.getName() + ", section " + B.getSection().getName() + + " unsupported edge kind " + getEdgeKindName(Kind)); +} + +/// Stubs builder for a specific StubsFlavor +/// +/// Right now we only have one default stub kind, but we want to extend this +/// and allow creation of specific kinds in the future (e.g. branch range +/// extension or interworking). +/// +/// Let's keep it simple for the moment and not wire this through a GOT. +/// +template +class StubsManager : public TableManager> { +public: + StubsManager() = default; + + /// Name of the object file section that will contain all our stubs. + static StringRef getSectionName() { return "S__STUBS"; } + + /// Implements link-graph traversal via visitExistingEdges(). + bool visitEdge(LinkGraph &G, Block *B, Edge &E) { + if (E.getTarget().isDefined()) + return false; + + switch (E.getKind()) { + case arm::Thumb_Call: + case arm::Thumb_Jump24: { + DEBUG_WITH_TYPE("jitlink", { + dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at " + << B->getFixupAddress(E) << " (" << B->getAddress() << " + " + << formatv("{0:x}", E.getOffset()) << ")\n"; + }); + E.setTarget(this->getEntryForTarget(G, E.getTarget())); + return true; + } + } + return false; + } + + /// Create a branch range extension stub for the class's flavor. + Symbol &createEntry(LinkGraph &G, Symbol &Target); + +private: + /// Create a new node in the link-graph for the given stub template. + template + Block &addStub(LinkGraph &G, const uint8_t (&Code)[Size], + uint64_t Alignment) { + ArrayRef Template(reinterpret_cast(Code), Size); + return G.createContentBlock(getStubsSection(G), Template, + orc::ExecutorAddr(), Alignment, 0); + } + + /// Get or create the object file section that will contain all our stubs. + Section &getStubsSection(LinkGraph &G) { + if (!StubsSection) + StubsSection = &G.createSection(getSectionName(), + orc::MemProt::Read | orc::MemProt::Exec); + return *StubsSection; + } + + Section *StubsSection = nullptr; +}; + +/// Create a branch range extension stub with Thumb encoding for v7 CPUs. +template <> +Symbol &StubsManager::createEntry(LinkGraph &G, Symbol &Target); + +} // namespace arm +} // namespace jitlink +} // namespace llvm + +#endif // LLVM_EXECUTIONENGINE_JITLINK_ARM_H diff --git a/llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt b/llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt --- a/llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt +++ b/llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt @@ -20,6 +20,7 @@ # ELF ELF.cpp ELFLinkGraphBuilder.cpp + ELF_aarch32.cpp ELF_aarch64.cpp ELF_i386.cpp ELF_loongarch.cpp @@ -33,6 +34,7 @@ COFF_x86_64.cpp # Architectures: + aarch32.cpp aarch64.cpp i386.cpp loongarch.cpp diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF.cpp --- a/llvm/lib/ExecutionEngine/JITLink/ELF.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/ELF.cpp @@ -13,6 +13,7 @@ #include "llvm/ExecutionEngine/JITLink/ELF.h" #include "llvm/BinaryFormat/ELF.h" +#include "llvm/ExecutionEngine/JITLink/ELF_aarch32.h" #include "llvm/ExecutionEngine/JITLink/ELF_aarch64.h" #include "llvm/ExecutionEngine/JITLink/ELF_i386.h" #include "llvm/ExecutionEngine/JITLink/ELF_loongarch.h" @@ -69,6 +70,8 @@ switch (*TargetMachineArch) { case ELF::EM_AARCH64: return createLinkGraphFromELFObject_aarch64(ObjectBuffer); + case ELF::EM_ARM: + return createLinkGraphFromELFObject_arm(ObjectBuffer); case ELF::EM_LOONGARCH: return createLinkGraphFromELFObject_loongarch(ObjectBuffer); case ELF::EM_RISCV: @@ -90,6 +93,12 @@ case Triple::aarch64: link_ELF_aarch64(std::move(G), std::move(Ctx)); return; + case Triple::arm: + case Triple::armeb: + case Triple::thumb: + case Triple::thumbeb: + link_ELF_arm(std::move(G), std::move(Ctx)); + return; case Triple::loongarch32: case Triple::loongarch64: link_ELF_loongarch(std::move(G), std::move(Ctx)); diff --git a/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h b/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h --- a/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h +++ b/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h @@ -108,6 +108,10 @@ Error graphifySections(); Error graphifySymbols(); + /// Override in derived classes to suppress certain sections in the link + /// graph. + virtual bool excludeSectionByName(StringRef Name) const { return false; } + /// Traverse all matching ELFT::Rela relocation records in the given section. /// The handler function Func should be callable with this signature: /// Error(const typename ELFT::Rela &, @@ -307,6 +311,13 @@ auto Name = Obj.getSectionName(Sec, SectionStringTab); if (!Name) return Name.takeError(); + if (excludeSectionByName(*Name)) { + LLVM_DEBUG({ + dbgs() << " " << SecIndex << ": Skipping section \"" << *Name + << "\"\n"; + }); + continue; + } // If the name indicates that it's a debug section then skip it: We don't // support those yet. diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp @@ -0,0 +1,276 @@ +//===-- ELF_arm.cpp - JIT linker implementation for 32-bit arm and thumb --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// ELF/arm jit-link implementation. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ExecutionEngine/JITLink/ELF_aarch32.h" + +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/ExecutionEngine/JITLink/DWARFRecordSectionSplitter.h" +#include "llvm/ExecutionEngine/JITLink/JITLink.h" +#include "llvm/ExecutionEngine/JITLink/aarch32.h" +#include "llvm/Object/ELF.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/TargetParser/ARMTargetParser.h" + +#include "EHFrameSupportImpl.h" +#include "ELFLinkGraphBuilder.h" +#include "JITLinkGeneric.h" + +#define DEBUG_TYPE "jitlink" + +using namespace llvm; +using namespace llvm::jitlink; +using namespace llvm::jitlink::arm; + +namespace { + +class ELFJITLinker_arm : public JITLinker { + friend class JITLinker; + +public: + ELFJITLinker_arm(std::unique_ptr Ctx, + std::unique_ptr G, PassConfiguration PassCfg, + ArmConfig ArmCfg) + : JITLinker(std::move(Ctx), std::move(G), std::move(PassCfg)), + ArmCfg(std::move(ArmCfg)) {} + +private: + ArmConfig ArmCfg; + + Error applyFixup(LinkGraph &G, Block &B, const Edge &E) const { + return arm::applyFixup(G, B, E, ArmCfg); + } +}; + +template +class ELFLinkGraphBuilder_arm + : public ELFLinkGraphBuilder> { +private: + using ELFT = object::ELFType; + + static Expected getRelocationKind(const uint32_t Type) { + using namespace arm; + switch (Type) { + case ELF::R_ARM_REL32: + return Data_Delta32; + case ELF::R_ARM_CALL: + return Arm_Call; + case ELF::R_ARM_THM_CALL: + return Thumb_Call; + case ELF::R_ARM_THM_JUMP24: + return Thumb_Jump24; + case ELF::R_ARM_THM_MOVW_ABS_NC: + return Thumb_MovwAbsNC; + case ELF::R_ARM_THM_MOVT_ABS: + return Thumb_MovtAbs; + } + + return make_error( + "Unsupported arm relocation: " + formatv("{0:d}: ", Type) + + object::getELFRelocationTypeName(ELF::EM_ARM, Type)); + } + + bool excludeSectionByName(StringRef Name) const override { + // TODO: Process .ex* sections + return Name.contains(".ARM.exidx") || Name.contains(".ARM.extab"); + } + + Error addRelocations() override { + LLVM_DEBUG(dbgs() << "Processing relocations:\n"); + + using Base = ELFLinkGraphBuilder; + using Self = ELFLinkGraphBuilder_arm; + for (const auto &RelSect : Base::Sections) { + auto Name = Base::Obj.getSectionName(RelSect, Base::SectionStringTab); + assert(Name && "We traversed section names before in graphifySections()"); + if (Name && !excludeSectionByName(*Name)) + if (Error Err = Base::forEachRelRelocation( + RelSect, this, &Self::addSingleRelRelocation)) + return Err; + } + return Error::success(); + } + + Error addSingleRelRelocation(const typename ELFT::Rel &Rel, + const typename ELFT::Shdr &FixupSect, + Block &BlockToFix) { + using Base = ELFLinkGraphBuilder; + + uint32_t SymbolIndex = Rel.getSymbol(false); + auto ObjSymbol = Base::Obj.getRelocationSymbol(Rel, Base::SymTabSec); + if (!ObjSymbol) + return ObjSymbol.takeError(); + + Symbol *GraphSymbol = Base::getGraphSymbol(SymbolIndex); + if (!GraphSymbol) + return make_error( + formatv("Could not find symbol at given index, did you add it to " + "JITSymbolTable? index: {0}, shndx: {1} Size of table: {2}", + SymbolIndex, (*ObjSymbol)->st_shndx, + Base::GraphSymbols.size()), + inconvertibleErrorCode()); + + uint32_t Type = Rel.getType(false); + Expected Kind = getRelocationKind(Type); + if (!Kind) + return Kind.takeError(); + + auto FixupAddress = orc::ExecutorAddr(FixupSect.sh_addr) + Rel.r_offset; + Edge::OffsetT Offset = FixupAddress - BlockToFix.getAddress(); + Edge E(*Kind, Offset, *GraphSymbol, 0); + + using Base = ELFLinkGraphBuilder; + Expected Addend = arm::readAddend(*Base::G, BlockToFix, E, ArmCfg); + if (!Addend) + return Addend.takeError(); + + E.setAddend(*Addend); + LLVM_DEBUG({ + dbgs() << " "; + printEdge(dbgs(), BlockToFix, E, arm::getEdgeKindName(*Kind)); + dbgs() << "\n"; + }); + + BlockToFix.addEdge(std::move(E)); + return Error::success(); + } + + ArmConfig ArmCfg; + +public: + ELFLinkGraphBuilder_arm(StringRef FileName, const object::ELFFile &Obj, + Triple TT, ArmConfig ArmCfg) + : ELFLinkGraphBuilder(Obj, std::move(TT), FileName, + arm::getEdgeKindName), + ArmCfg(std::move(ArmCfg)) {} +}; + +template Error buildTables_ELF_arm(LinkGraph &G) { + LLVM_DEBUG(dbgs() << "Visiting edges in graph:\n"); + + arm::StubsManager PLT; + visitExistingEdges(G, PLT); + return Error::success(); +} + +} // namespace + +namespace llvm { +namespace jitlink { + +Expected> +createLinkGraphFromELFObject_arm(MemoryBufferRef ObjectBuffer) { + LLVM_DEBUG({ + dbgs() << "Building jitlink graph for new input " + << ObjectBuffer.getBufferIdentifier() << "...\n"; + }); + + auto ELFObj = object::ObjectFile::createELFObjectFile(ObjectBuffer); + if (!ELFObj) + return ELFObj.takeError(); + + auto TT = (*ELFObj)->makeTriple(); + ARM::ArchKind AK = ARM::parseArch(TT.getArchName()); + if (AK == ARM::ArchKind::INVALID) + return make_error( + "Failed to build ELF link graph: Invalid ARM ArchKind"); + + using namespace ARMBuildAttrs; + auto Arch = static_cast(ARM::getArchAttr(AK)); + arm::ArmConfig ArmCfg; + switch (Arch) { + case v7: + case v8_A: + ArmCfg = getArmConfigForCPUArch(Arch); + assert(ArmCfg.Stubs != arm::Unsupported && + "Provide a ARM config for each supported CPU"); + break; + case Pre_v4: + case v4: + case v4T: + case v5T: + case v5TE: + case v5TEJ: + case v6: + case v6KZ: + case v6T2: + case v6K: + case v6_M: + case v6S_M: + case v7E_M: + case v8_R: + case v8_M_Base: + case v8_M_Main: + case v8_1_M_Main: + case v9_A: + return make_error( + "Failed to build ELF link graph: Unsupported CPU sub-arch " + + StringRef(arm::getCPUArchName(Arch))); + } + + switch (TT.getArch()) { + case Triple::arm: + case Triple::thumb: { + auto &ELFObjFile = cast>(**ELFObj); + return ELFLinkGraphBuilder_arm( + (*ELFObj)->getFileName(), ELFObjFile.getELFFile(), TT, ArmCfg) + .buildGraph(); + } + case Triple::armeb: + case Triple::thumbeb: { + auto &ELFObjFile = cast>(**ELFObj); + return ELFLinkGraphBuilder_arm( + (*ELFObj)->getFileName(), ELFObjFile.getELFFile(), TT, ArmCfg) + .buildGraph(); + } + default: + llvm_unreachable("Invalid arch type for JITLink ELF/arm"); + } +} + +void link_ELF_arm(std::unique_ptr G, + std::unique_ptr Ctx) { + const Triple &TT = G->getTargetTriple(); + + using namespace ARMBuildAttrs; + ARM::ArchKind AK = ARM::parseArch(TT.getArchName()); + auto CPU = static_cast(ARM::getArchAttr(AK)); + arm::ArmConfig ArmCfg = getArmConfigForCPUArch(CPU); + + PassConfiguration PassCfg; + if (Ctx->shouldAddDefaultTargetPasses(TT)) { + // Add a mark-live pass. + if (auto MarkLive = Ctx->getMarkLivePass(TT)) + PassCfg.PrePrunePasses.push_back(std::move(MarkLive)); + else + PassCfg.PrePrunePasses.push_back(markAllSymbolsLive); + + switch (ArmCfg.Stubs) { + case arm::Thumbv7: + PassCfg.PostPrunePasses.push_back(buildTables_ELF_arm); + break; + case arm::Unsupported: + llvm_unreachable("Check before building graph"); + } + } + + if (auto Err = Ctx->modifyPassConfig(*G, PassCfg)) + return Ctx->notifyFailed(std::move(Err)); + + ELFJITLinker_arm::link(std::move(Ctx), std::move(G), std::move(PassCfg), + std::move(ArmCfg)); +} + +} // namespace jitlink +} // namespace llvm diff --git a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp @@ -0,0 +1,467 @@ +//===----- arm.cpp - Generic JITLink arm/thumb edge kinds, utilities ------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Generic utilities for graphs representing arm/thumb objects. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ExecutionEngine/JITLink/aarch32.h" + +#include "llvm/ADT/StringExtras.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/ExecutionEngine/JITLink/JITLink.h" +#include "llvm/ExecutionEngine/JITSymbol.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Endian.h" + +#define DEBUG_TYPE "jitlink" + +namespace llvm { +namespace jitlink { +namespace arm { + +using namespace support; +using namespace support::endian; + +/// Encode 22-bit immediate value for branch instructions without J1J2 range +/// extension (formats B T4, BL T1 and BLX T2). +/// +/// 00000:Imm11H:Imm11L:0 -> [ 00000:Imm11H, 00000:Imm11L ] +/// J1^ ^J2 will always be 1 +/// +HalfWords encodeImmBT4BlT1BlxT2(int64_t Value) { + constexpr uint32_t J1J2 = 0x2800; + uint32_t Imm11H = (Value >> 12) & 0x07ff; + uint32_t Imm11L = (Value >> 1) & 0x07ff; + return HalfWords{Imm11H, Imm11L | J1J2}; +} + +/// Decode 22-bit immediate value for branch instructions without J1J2 range +/// extension (formats B T4, BL T1 and BLX T2). +/// +/// [ 00000:Imm11H, 00000:Imm11L ] -> 00000:Imm11H:Imm11L:0 +/// J1^ ^J2 will always be 1 +/// +int64_t decodeImmBT4BlT1BlxT2(uint32_t Hi, uint32_t Lo) { + uint32_t Imm11H = Hi & 0x07ff; + uint32_t Imm11L = Lo & 0x07ff; + return SignExtend64<22>(Imm11H << 12 | Imm11L << 1); +} + +/// Encode 25-bit immediate value for branch instructions with J1J2 range +/// extension (formats B T4, BL T1 and BLX T2). +/// +/// S:I1:I2:Imm10:Imm11:0 -> [ 00000:S:Imm10, 00:J1:0:J2:Imm11 ] +/// +HalfWords encodeImmBT4BlT1BlxT2_J1J2(int64_t Value) { + uint32_t S = (Value >> 14) & 0x0400; + uint32_t J1 = (((~(Value >> 10)) ^ (Value >> 11)) & 0x2000); + uint32_t J2 = (((~(Value >> 11)) ^ (Value >> 13)) & 0x0800); + uint32_t Imm10 = (Value >> 12) & 0x03ff; + uint32_t Imm11 = (Value >> 1) & 0x07ff; + return HalfWords{S | Imm10, J1 | J2 | Imm11}; +} + +/// Decode 25-bit immediate value for branch instructions with J1J2 range +/// extension (formats B T4, BL T1 and BLX T2). +/// +/// [ 00000:S:Imm10, 00:J1:0:J2:Imm11] -> S:I1:I2:Imm10:Imm11:0 +/// +int64_t decodeImmBT4BlT1BlxT2_J1J2(uint32_t Hi, uint32_t Lo) { + uint32_t S = Hi & 0x0400; + uint32_t I1 = ~((Lo ^ (Hi << 3)) << 10) & 0x00800000; + uint32_t I2 = ~((Lo ^ (Hi << 1)) << 11) & 0x00400000; + uint32_t Imm10 = Hi & 0x03ff; + uint32_t Imm11 = Lo & 0x07ff; + return SignExtend64<25>(S << 14 | I1 | I2 | Imm10 << 12 | Imm11 << 1); +} + +/// Encode 16-bit immediate value for move instruction formats MOVT T1 and +/// MOVW T3. +/// +/// Imm4:Imm1:Imm3:Imm8 -> [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ] +/// +HalfWords encodeImmMovtT1MovwT3(uint16_t Value) { + uint32_t Imm4 = (Value >> 12) & 0x0f; + uint32_t Imm1 = (Value >> 11) & 0x01; + uint32_t Imm3 = (Value >> 8) & 0x07; + uint32_t Imm8 = Value & 0xff; + return HalfWords{Imm1 << 10 | Imm4, Imm3 << 12 | Imm8}; +} + +/// Decode 16-bit immediate value from move instruction formats MOVT T1 and +/// MOVW T3. +/// +/// [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ] -> Imm4:Imm1:Imm3:Imm8 +/// +uint16_t decodeImmMovtT1MovwT3(uint32_t Hi, uint32_t Lo) { + uint32_t Imm4 = Hi & 0x0f; + uint32_t Imm1 = (Hi >> 10) & 0x01; + uint32_t Imm3 = (Lo >> 12) & 0x07; + uint32_t Imm8 = Lo & 0xff; + uint32_t Imm16 = Imm4 << 12 | Imm1 << 11 | Imm3 << 8 | Imm8; + assert(Imm16 <= 0xffff && "Decoded value out-of-range"); + return Imm16; +} + +/// Encode register ID for instruction formats MOVT T1 and MOVW T3. +/// +/// Rd4 -> [0000000000000000, 0000:Rd4:00000000] +/// +HalfWords encodeRegMovtT1MovwT3(int64_t Value) { + uint32_t Rd4 = (Value & 0x0f) << 8; + return HalfWords{0, Rd4}; +} + +/// Decode register ID from instruction formats MOVT T1 and MOVW T3. +/// +/// [0000000000000000, 0000:Rd4:00000000] -> Rd4 +/// +int64_t decodeRegMovtT1MovwT3(uint32_t Hi, uint32_t Lo) { + uint32_t Rd4 = (Lo >> 8) & 0x0f; + return Rd4; +} + +/// 32-bit Thumb instructions are stored as two little-endian halfwords. +/// An instruction at address A encodes bytes A+1, A in the first halfword (Hi), +/// followed by bytes A+3, A+2 in the second halfword (Lo). +class ThumbRelocation { +public: + /// Create a read-only reference to a Thumb32 fixup + ThumbRelocation(const char *FixupPtr) + : Hi{*reinterpret_cast(FixupPtr)}, + Lo{*reinterpret_cast(FixupPtr + 2)} {} + + /// Create a writable reference to a Thumb32 fixup + ThumbRelocation(char *FixupPtr) + : ThumbRelocation(static_cast(FixupPtr)) { + Writable = true; + } + + void setLo(uint16_t Imm) { + assert(Writable && "Create with mutable FixupPtr"); + const_cast(Lo) = Imm; + } + void setHi(uint16_t Imm) { + assert(Writable && "Create with mutable FixupPtr"); + const_cast(Hi) = Imm; + } + + const support::ulittle16_t &Hi; // First halfword + const support::ulittle16_t &Lo; // Second halfword + +private: + bool Writable{false}; +}; + +Error makeUnexpectedOpcodeError(Edge::Kind Kind, const ThumbRelocation &R) { + return make_error( + "Invalid opcode for '" + StringRef(getEdgeKindName(Kind)) + + "' relocation: [ 0x" +utohexstr(R.Hi, true, 4) + ", 0x" + + utohexstr(R.Lo, true, 4) + " ]"); +} + +template bool checkOpcode(const ThumbRelocation &R) { + uint16_t Hi = R.Hi & FixupInfo::OpcodeMask.Hi; + uint16_t Lo = R.Lo & FixupInfo::OpcodeMask.Lo; + return Hi == FixupInfo::Opcode.Hi && Lo == FixupInfo::Opcode.Lo; +} + +template +bool checkRegister(const ThumbRelocation &R, HalfWords Reg) { + uint16_t Hi = R.Hi & FixupInfo::RegMask.Hi; + uint16_t Lo = R.Lo & FixupInfo::RegMask.Lo; + return Hi == Reg.Hi && Lo == Reg.Lo; +} + +template +bool writeRegister(ThumbRelocation &R, HalfWords Reg) { + static constexpr HalfWords Mask = FixupInfo::RegMask; + assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Hi & Reg.Hi) == Reg.Hi && + "Value bits exceed bit range of given mask"); + R.setHi((R.Hi & ~Mask.Hi) | Reg.Hi); + R.setLo((R.Lo & ~Mask.Lo) | Reg.Lo); +} + +template +void writeImmediate(ThumbRelocation &R, HalfWords Imm) { + static constexpr HalfWords Mask = FixupInfo::ImmMask; + assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Hi & Imm.Hi) == Imm.Hi && + "Value bits exceed bit range of given mask"); + R.setHi((R.Hi & ~Mask.Hi) | Imm.Hi); + R.setLo((R.Lo & ~Mask.Lo) | Imm.Lo); +} + +std::optional> +readAddendData(Edge::Kind Kind, const char *FixupPtr, endianness Endian) { + assert(Endian != native && "Declare explicitly as little or big"); + switch (Kind) { + case Data_Delta32: + return SignExtend64<32>((Endian == little) ? read32(FixupPtr) + : read32(FixupPtr)); + default: + break; + } + return std::nullopt; +} + +std::optional> readAddendArm(Edge::Kind Kind, + const char *FixupPtr) { + return std::nullopt; +} + +std::optional> readAddendThumb(Edge::Kind Kind, + const char *FixupPtr, + const ArmConfig &ArmCfg) { + ThumbRelocation R(FixupPtr); + switch (Kind) { + case Thumb_Call: + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + if ((R.Lo & FixupInfo::LoBitNoBlx) == 0 && + (R.Lo & FixupInfo::LoBitH) != 0) + return make_error( + "Least significant bit H must be clear in " + "second halfword for encoding BLX T2: " + + llvm::utohexstr(R.Lo)); + return LLVM_LIKELY(ArmCfg.J1J2BranchEncoding) + ? decodeImmBT4BlT1BlxT2_J1J2(R.Hi, R.Lo) + : decodeImmBT4BlT1BlxT2(R.Hi, R.Lo); + + case Thumb_Jump24: + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + if (R.Lo & FixupInfo::LoBitConditional) + return make_error("Relocation expects an unconditional " + "B.W branch instruction: " + + StringRef(getEdgeKindName(Kind))); + return decodeImmBT4BlT1BlxT2_J1J2(R.Hi, R.Lo); + + case Thumb_MovwAbsNC: + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + // Initial addend is interpreted as a signed value + return SignExtend64<16>(decodeImmMovtT1MovwT3(R.Hi, R.Lo)); + + case Thumb_MovtAbs: + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + // Initial addend is interpreted as a signed value + return SignExtend64<16>(decodeImmMovtT1MovwT3(R.Hi, R.Lo)); + + default: + break; + } + return std::nullopt; +} + +std::optional applyFixupData(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg) { + using namespace support; + + char *BlockWorkingMem = B.getAlreadyMutableContent().data(); + char *FixupPtr = BlockWorkingMem + E.getOffset(); + + auto Write32 = [FixupPtr, Endian = G.getEndianness()](int64_t Value) { + assert(Endian != native && "Must be explicit: little or big"); + assert(isInt<32>(Value) && "Must be in signed 32-bit range"); + uint32_t Imm = static_cast(Value); + if (LLVM_LIKELY(Endian == little)) + endian::write32(FixupPtr, Imm); + else + endian::write32(FixupPtr, Imm); + }; + + Edge::Kind Kind = E.getKind(); + uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue(); + uint64_t TargetAddress = E.getTarget().getAddress().getValue(); + int64_t Addend = E.getAddend(); + + // Regular data relocations have size 4, alignment 1 and write the full 32-bit + // result to the place; no need for overflow checking. There are three + // exceptions: R_ARM_ABS8, R_ARM_ABS16, R_ARM_PREL31 + switch (Kind) { + case Data_Delta32: { + int64_t Value = TargetAddress - FixupAddress + Addend; + if (!isInt<32>(Value)) + return makeTargetOutOfRangeError(G, B, E); + Write32(Value); + return Error::success(); + } + default: + break; + } + return std::nullopt; +} + +std::optional applyFixupArm(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg) { + return std::nullopt; +} + +std::optional applyFixupThumb(LinkGraph &G, Block &B, const Edge &E, + const ArmConfig &ArmCfg) { + char *BlockWorkingMem = B.getAlreadyMutableContent().data(); + ThumbRelocation R(BlockWorkingMem + E.getOffset()); + + Edge::Kind Kind = E.getKind(); + uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue(); + uint64_t TargetAddress = E.getTarget().getAddress().getValue(); + int64_t Addend = E.getAddend(); + + switch (Kind) { + case Thumb_Jump24: { + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + if (R.Lo & FixupInfo::LoBitConditional) + return make_error("Relocation expects an unconditional " + "B.W branch instruction: " + + StringRef(getEdgeKindName(Kind))); + if ((TargetAddress & 0x1) == 0) + return make_error("Branch relocation needs interworking " + "veneer when bridging to ARM: " + + StringRef(getEdgeKindName(Kind))); + if (!ArmCfg.J1J2BranchEncoding) + return make_error( + "Relocation doesn't support branch " + "encoding without J1/J2 range extensions: " + + StringRef(getEdgeKindName(Kind))); + + int64_t Value = TargetAddress - FixupAddress + Addend; + if (!isInt<25>(Value)) + return makeTargetOutOfRangeError(G, B, E); + + writeImmediate(R, encodeImmBT4BlT1BlxT2_J1J2(Value)); + return Error::success(); + } + + case Thumb_Call: { + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + int64_t Value = TargetAddress - FixupAddress + Addend; + if (ArmCfg.J1J2BranchEncoding ? !isInt<25>(Value) : !isInt<22>(Value)) + return makeTargetOutOfRangeError(G, B, E); + + bool TargetIsThumb = Value & 0x1; + bool InstIsBlx = (R.Lo & FixupInfo::LoBitNoBlx) == 0; + uint16_t BlxBitsToClear = + FixupInfo::LoBitNoBlx | FixupInfo::LoBitH; + + if (!TargetIsThumb && InstIsBlx) { + // Fix range value: (1) accounts for 4-byte alignment of destination while + // instruction may only be 2-byte aligned and (2) clears Thumb bit. + Value = alignTo(Value, 4); + R.setLo(R.Lo & ~BlxBitsToClear); + InstIsBlx = true; + } + + writeImmediate(R, LLVM_LIKELY(ArmCfg.J1J2BranchEncoding) + ? encodeImmBT4BlT1BlxT2_J1J2(Value) + : encodeImmBT4BlT1BlxT2(Value)); + + assert((!InstIsBlx || (R.Lo & BlxBitsToClear) == 0) && + "Avoid UB in BLX T2"); + return Error::success(); + } + + case Thumb_MovwAbsNC: { + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + uint16_t Value = (TargetAddress + Addend) & 0xffff; + writeImmediate(R, encodeImmMovtT1MovwT3(Value)); + return Error::success(); + } + + case Thumb_MovtAbs: { + if (!checkOpcode(R)) + return makeUnexpectedOpcodeError(Kind, R); + uint16_t Value = ((TargetAddress + Addend) >> 16) & 0xffff; + writeImmediate(R, encodeImmMovtT1MovwT3(Value)); + return Error::success(); + } + + default: + break; + } + return std::nullopt; +} + +const uint8_t Thumbv7ABS[] = { + 0x40, 0xf2, 0x00, 0x0c, // movw r12, #0x0000 ; lower 16-bit + 0xc0, 0xf2, 0x00, 0x0c, // movt r12, #0x0000 ; upper 16-bit + 0x60, 0x47 // bx r12 +}; + +template <> +Symbol &StubsManager::createEntry(LinkGraph &G, Symbol &Target) { + constexpr uint64_t Alignment = 4; + Block &B = addStub(G, Thumbv7ABS, Alignment); + assert(checkRegister(B.getContent().data(), + encodeRegMovtT1MovwT3(12)) && + checkRegister(B.getContent().data() + 4, + encodeRegMovtT1MovwT3(12)) && + "Linker generated veneers may only corrupt register r12 (IP)"); + B.addEdge(Thumb_MovwAbsNC, 0, Target, 0); + B.addEdge(Thumb_MovtAbs, 4, Target, 0); + return G.addAnonymousSymbol(B, 0x1, B.getSize(), true, false); +} + +const char *getEdgeKindName(Edge::Kind K) { + switch (K) { + case Data_Delta32: + return "R_ARM_REL32"; + case Arm_Call: + return "R_ARM_CALL"; + case Thumb_Call: + return "R_ARM_THM_CALL"; + case Thumb_Jump24: + return "R_ARM_THM_JUMP24"; + case Thumb_MovwAbsNC: + return "R_ARM_THM_MOVW_ABS_NC"; + case Thumb_MovtAbs: + return "R_ARM_THM_MOVT_ABS"; + default: + return getGenericEdgeKindName(K); + } +} + +const char *getCPUArchName(ARMBuildAttrs::CPUArch K) { +#define CPUARCH_NAME_CASE(K) \ + case K: \ + return #K; + + using namespace ARMBuildAttrs; + switch (K) { + CPUARCH_NAME_CASE(Pre_v4) + CPUARCH_NAME_CASE(v4) + CPUARCH_NAME_CASE(v4T) + CPUARCH_NAME_CASE(v5T) + CPUARCH_NAME_CASE(v5TE) + CPUARCH_NAME_CASE(v5TEJ) + CPUARCH_NAME_CASE(v6) + CPUARCH_NAME_CASE(v6KZ) + CPUARCH_NAME_CASE(v6T2) + CPUARCH_NAME_CASE(v6K) + CPUARCH_NAME_CASE(v7) + CPUARCH_NAME_CASE(v6_M) + CPUARCH_NAME_CASE(v6S_M) + CPUARCH_NAME_CASE(v7E_M) + CPUARCH_NAME_CASE(v8_A) + CPUARCH_NAME_CASE(v8_R) + CPUARCH_NAME_CASE(v8_M_Base) + CPUARCH_NAME_CASE(v8_M_Main) + CPUARCH_NAME_CASE(v8_1_M_Main) + CPUARCH_NAME_CASE(v9_A) + } + llvm_unreachable("Missing CPUArch in switch?"); +#undef CPUARCH_NAME_CASE +} + +} // namespace arm +} // namespace jitlink +} // namespace llvm diff --git a/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s b/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s new file mode 100644 --- /dev/null +++ b/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s @@ -0,0 +1,40 @@ +// RUN: llvm-mc -triple=thumbv7-none-linux-gnueabi -arm-add-build-attributes -filetype=obj -o %t.o %s +// RUN: llvm-jitlink -noexec %t.o + + .globl main + .p2align 2 + .type main,%function + .code 16 + .thumb_func +main: + .fnstart + .save {r7, lr} + push {r7, lr} + .setfp r7, sp + mov r7, sp + .pad #8 + sub sp, #8 + movs r0, #0 + str r0, [sp] + str r0, [sp, #4] + ldr r0, .LCPI0_0 +.LPC0_0: + add r0, pc + bl printf + ldr r0, [sp] + add sp, #8 + pop {r7, pc} + + .p2align 2 +.LCPI0_0: + .long .L.str-(.LPC0_0+4) + + .size main, .-main + .cantunwind + .fnend + + .type .L.str,%object + .section .rodata.str1.1,"aMS",%progbits,1 +.L.str: + .asciz "Hello AArch32!\n" + .size .L.str, 12 diff --git a/llvm/test/ExecutionEngine/JITLink/AArch32/lit.local.cfg b/llvm/test/ExecutionEngine/JITLink/AArch32/lit.local.cfg new file mode 100644 --- /dev/null +++ b/llvm/test/ExecutionEngine/JITLink/AArch32/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'ARM' in config.root.targets: + config.unsupported = True diff --git a/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp b/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp new file mode 100644 --- /dev/null +++ b/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp @@ -0,0 +1,116 @@ +//===------- AArch32Tests.cpp - Unit tests for the AArch32 backend --------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "gtest/gtest.h" + +namespace llvm { +namespace jitlink { +namespace arm { + +HalfWords encodeImmBT4BlT1BlxT2(int64_t Value); +HalfWords encodeImmBT4BlT1BlxT2_J1J2(int64_t Value); +HalfWords encodeImmMovtT1MovwT3(uint32_t Value); +HalfWords encodeRegMovtT1MovwT3(int64_t Value); + +int64_t decodeImmBT4BlT1BlxT2(uint32_t Hi, uint32_t Lo); +int64_t decodeImmBT4BlT1BlxT2_J1J2(uint32_t Hi, uint32_t Lo); +uint32_t decodeImmMovtT1MovwT3(uint32_t Hi, uint32_t Lo); +int64_t decodeRegMovtT1MovwT3(uint32_t Hi, uint32_t Lo); + +} // namespace arm +} // namespace jitlink +} // namespace llvm + +using namespace llvm; +using namespace llvm::jitlink; +using namespace llvm::jitlink::arm; +using namespace llvm::support; +using namespace llvm::support::endian; + +template +static HalfWords makeHalfWords(std::array Mem) { + return HalfWords{read16(Mem.data()), read16(Mem.data() + 2)}; +} + +/// 25-bit branch with link (with J1J2 range extension) +TEST(AArch32Relocations, Thumb_Call_J1J2) { + static_assert(isInt<25>(16777215) && !isInt<25>(16777217), + "Max and first overflow"); + static_assert(isInt<25>(-16777215) && !isInt<25>(-16777217), + "Min and first underflow"); + + constexpr HalfWords ImmMask = FixupInfo::ImmMask; + + static std::array MemPresets{ + makeHalfWords({0xff, 0xf7, 0xfe, 0xef}), // common + makeHalfWords({0x00, 0x00, 0x00, 0x00}), // zeros + makeHalfWords({0xff, 0xff, 0xff, 0xff}), // ones + }; + + auto EncodeDecode = [](int64_t In, HalfWords &Mem) { + HalfWords Imm = encodeImmBT4BlT1BlxT2_J1J2(In); + HalfWords Patched((Mem.Hi & ~ImmMask.Hi) | Imm.Hi, + (Mem.Lo & ~ImmMask.Lo) | Imm.Lo); + return decodeImmBT4BlT1BlxT2_J1J2(Patched.Hi, Patched.Lo); + }; + + for (HalfWords Mem : MemPresets) { + HalfWords UnaffectedBits(Mem.Hi & ~ImmMask.Hi, Mem.Lo & ~ImmMask.Lo); + + EXPECT_EQ(EncodeDecode(1, Mem), 0); // Zero value (LSB was thumb bit) + EXPECT_EQ(EncodeDecode(0x41, Mem), 0x40); // Common value + EXPECT_EQ(EncodeDecode(16777215, Mem), 16777214); // Maximum value + EXPECT_EQ(EncodeDecode(-16777215, Mem), -16777216); // Minimum value + EXPECT_EQ(EncodeDecode(16777217, Mem), -16777216); // First overflow + EXPECT_EQ(EncodeDecode(-16777217, Mem), 16777214); // First underflow + + EXPECT_TRUE(UnaffectedBits.Hi == (Mem.Hi & ~ImmMask.Hi) && + UnaffectedBits.Lo == (Mem.Lo & ~ImmMask.Lo)) + << "Diff outside immediate field"; + } +} + +/// 22-bit branch with link (without J1J2 range extension) +TEST(AArch32Relocations, Thumb_Call_Old) { + static_assert(isInt<22>(2097151) && !isInt<22>(2097153), + "Max and first overflow"); + static_assert(isInt<22>(-2097151) && !isInt<22>(-2097153), + "Min and first underflow"); + + constexpr HalfWords ImmMask = FixupInfo::ImmMask; + + static std::array MemPresets{ + makeHalfWords({0xff, 0xf7, 0xfe, 0xef}), // common + makeHalfWords({0x00, 0x00, 0x00, 0x00}), // zeros + makeHalfWords({0xff, 0xff, 0xff, 0xff}), // ones + }; + + auto EncodeDecode = [](int64_t In, HalfWords &Mem) { + HalfWords Imm = encodeImmBT4BlT1BlxT2(In); + HalfWords Patched((Mem.Hi & ~ImmMask.Hi) | Imm.Hi, + (Mem.Lo & ~ImmMask.Lo) | Imm.Lo); + return decodeImmBT4BlT1BlxT2(Patched.Hi, Patched.Lo); + }; + + for (HalfWords Mem : MemPresets) { + HalfWords UnaffectedBits(Mem.Hi & ~ImmMask.Hi, Mem.Lo & ~ImmMask.Lo); + + EXPECT_EQ(EncodeDecode(1, Mem), 0); // Zero value (LSB was thumb bit) + EXPECT_EQ(EncodeDecode(0x41, Mem), 0x40); // Common value + EXPECT_EQ(EncodeDecode(2097151, Mem), 2097150); // Maximum value + EXPECT_EQ(EncodeDecode(-2097151, Mem), -2097152); // Minimum value + EXPECT_EQ(EncodeDecode(2097153, Mem), -2097152); // First overflow + EXPECT_EQ(EncodeDecode(-2097153, Mem), 2097150); // First underflow + + EXPECT_TRUE(UnaffectedBits.Hi == (Mem.Hi & ~ImmMask.Hi) && + UnaffectedBits.Lo == (Mem.Lo & ~ImmMask.Lo)) + << "Diff outside immediate field"; + } +} diff --git a/llvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt b/llvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt --- a/llvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt +++ b/llvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt @@ -8,6 +8,7 @@ ) add_llvm_unittest(JITLinkTests + AArch32Tests.cpp EHFrameSupportTests.cpp LinkGraphTests.cpp )