Index: llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -1254,7 +1254,9 @@ switch (MI.getOpcode()) { default: llvm_unreachable("Unexpected opcode"); case AArch64::FMOVH0: - FMov.setOpcode(AArch64::FMOVWHr); + FMov.setOpcode(STI->hasFullFP16() ? AArch64::FMOVWHr : AArch64::FMOVWSr); + if (!STI->hasFullFP16()) + DestReg = (AArch64::S0 + (DestReg - AArch64::H0)); FMov.addOperand(MCOperand::createReg(DestReg)); FMov.addOperand(MCOperand::createReg(AArch64::WZR)); break; Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9788,8 +9788,10 @@ IsLegal = AArch64_AM::getFP64Imm(ImmInt) != -1 || Imm.isPosZero(); else if (VT == MVT::f32) IsLegal = AArch64_AM::getFP32Imm(ImmInt) != -1 || Imm.isPosZero(); - else if (VT == MVT::f16 && Subtarget->hasFullFP16()) - IsLegal = AArch64_AM::getFP16Imm(ImmInt) != -1 || Imm.isPosZero(); + else if (VT == MVT::f16) + IsLegal = + (Subtarget->hasFullFP16() && AArch64_AM::getFP16Imm(ImmInt) != -1) || + Imm.isPosZero(); // TODO: fmov h0, w0 is also legal, however on't have an isel pattern to // generate that fmov. Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -4201,7 +4201,7 @@ // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, - Sched<[WriteF]>, Requires<[HasFullFP16]>; + Sched<[WriteF]>; def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, Sched<[WriteF]>; def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, Index: llvm/test/CodeGen/AArch64/arm64-fmax.ll =================================================================== --- llvm/test/CodeGen/AArch64/arm64-fmax.ll +++ llvm/test/CodeGen/AArch64/arm64-fmax.ll @@ -73,8 +73,7 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 ; CHECK-NEXT: fcvt s1, h0 -; CHECK-NEXT: adrp x8, .LCPI5_0 -; CHECK-NEXT: ldr h2, [x8, :lo12:.LCPI5_0] +; CHECK-NEXT: movi d2, #0000000000000000 ; CHECK-NEXT: fcmp s1, #0.0 ; CHECK-NEXT: fcsel s0, s0, s2, lt ; CHECK-NEXT: fcvt s0, h0 Index: llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll =================================================================== --- llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll +++ llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll @@ -19,7 +19,7 @@ entry: ; ALL-LABEL: t1: ; ALL-NOT: fmov -; NONEFP-DAG: ldr h0,{{.*}} +; NONEFP-DAG: fmov s0, wzr ; NONEFP-DAG: fmov s1, wzr ; NONEFP-DAG: fmov d2, xzr ; NONEFP-DAG: movi{{(.16b)?}} v3{{(.2d)?}}, #0 @@ -27,7 +27,7 @@ ; NONE16: fmov s1, wzr ; NONE16: fmov d2, xzr ; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0 -; ZEROFP-DAG: ldr h0,{{.*}} +; ZEROFP-DAG: movi d0, #0 ; ZEROFP-DAG: movi d1, #0 ; ZEROFP-DAG: movi d2, #0 ; ZEROFP-DAG: movi v3.2d, #0 Index: llvm/test/CodeGen/AArch64/f16-imm.ll =================================================================== --- llvm/test/CodeGen/AArch64/f16-imm.ll +++ llvm/test/CodeGen/AArch64/f16-imm.ll @@ -16,8 +16,7 @@ ; ; CHECK-NOFP16-LABEL: Const0: ; CHECK-NOFP16: // %bb.0: // %entry -; CHECK-NOFP16-NEXT: adrp x8, .LCPI0_0 -; CHECK-NOFP16-NEXT: ldr h0, [x8, :lo12:.LCPI0_0] +; CHECK-NOFP16-NEXT: movi d0, #0000000000000000 ; CHECK-NOFP16-NEXT: ret entry: ret half 0xH0000 Index: llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll =================================================================== --- llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll +++ llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll @@ -38,9 +38,7 @@ define void @nvcast_f64(ptr %a) #0 { ; CHECK-LABEL: nvcast_f64: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI3_0 -; CHECK-NEXT: add x8, x8, :lo12:.LCPI3_0 -; CHECK-NEXT: ld1r { v0.4h }, [x8] +; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret store volatile <4 x half> zeroinitializer, ptr %a @@ -84,9 +82,7 @@ define void @nvcast_v2i64(ptr %a) #0 { ; CHECK-LABEL: nvcast_v2i64: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI7_0 -; CHECK-NEXT: add x8, x8, :lo12:.LCPI7_0 -; CHECK-NEXT: ld1r { v0.8h }, [x8] +; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret store volatile <8 x half> zeroinitializer, ptr %a Index: llvm/test/CodeGen/AArch64/mattr-all.ll =================================================================== --- llvm/test/CodeGen/AArch64/mattr-all.ll +++ llvm/test/CodeGen/AArch64/mattr-all.ll @@ -6,8 +6,7 @@ define half @bf16() nounwind { ; CHECK-LABEL: bf16: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI0_0 -; CHECK-NEXT: ldr h0, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: ret ret half 0xH0000 } Index: llvm/test/CodeGen/AArch64/vecreduce-fadd.ll =================================================================== --- llvm/test/CodeGen/AArch64/vecreduce-fadd.ll +++ llvm/test/CodeGen/AArch64/vecreduce-fadd.ll @@ -294,9 +294,8 @@ ; ; CHECKNOFP16-LABEL: fadd_reduction_v4f16_in_loop: ; CHECKNOFP16: // %bb.0: // %entry -; CHECKNOFP16-NEXT: adrp x9, .LCPI10_0 +; CHECKNOFP16-NEXT: movi d0, #0000000000000000 ; CHECKNOFP16-NEXT: mov x8, xzr -; CHECKNOFP16-NEXT: ldr h0, [x9, :lo12:.LCPI10_0] ; CHECKNOFP16-NEXT: .LBB10_1: // %loop ; CHECKNOFP16-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECKNOFP16-NEXT: ldr d1, [x0, x8] @@ -365,9 +364,8 @@ ; ; CHECKNOFP16-LABEL: fadd_reduction_v8f16_in_loop: ; CHECKNOFP16: // %bb.0: // %entry -; CHECKNOFP16-NEXT: adrp x9, .LCPI11_0 +; CHECKNOFP16-NEXT: movi d0, #0000000000000000 ; CHECKNOFP16-NEXT: mov x8, xzr -; CHECKNOFP16-NEXT: ldr h0, [x9, :lo12:.LCPI11_0] ; CHECKNOFP16-NEXT: .LBB11_1: // %loop ; CHECKNOFP16-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECKNOFP16-NEXT: ldr q1, [x0, x8]