diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -1711,6 +1711,25 @@
       case TargetOpcode::MEMBARRIER:
         OutStreamer->emitRawComment("MEMBARRIER");
         break;
+
+      // patchable-function-entry=N is a target-independent NOP sled.
+      case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
+        const Function &F = MF->getFunction();
+        if (F.hasFnAttribute("patchable-function-entry")) {
+          unsigned Num;
+          if (F.getFnAttribute("patchable-function-entry")
+                  .getValueAsString()
+                  .getAsInteger(10, Num)) {
+            // This is garbage, do nothing.
+            break;
+          }
+          emitNops(Num);
+        } else {
+          emitInstruction(&MI);
+        }
+        break;
+      }
+
       default:
         emitInstruction(&MI);
         if (CanDoExtraAnalysis) {
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -262,17 +262,6 @@
 
 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
 {
-  const Function &F = MF->getFunction();
-  if (F.hasFnAttribute("patchable-function-entry")) {
-    unsigned Num;
-    if (F.getFnAttribute("patchable-function-entry")
-            .getValueAsString()
-            .getAsInteger(10, Num))
-      return;
-    emitNops(Num);
-    return;
-  }
-
   emitSled(MI, SledKind::FUNCTION_ENTER);
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -227,19 +227,6 @@
   }
 
   switch (OutMI.getOpcode()) {
-  case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
-    const Function &F = MI->getParent()->getParent()->getFunction();
-    if (F.hasFnAttribute("patchable-function-entry")) {
-      unsigned Num;
-      if (F.getFnAttribute("patchable-function-entry")
-              .getValueAsString()
-              .getAsInteger(10, Num))
-        return false;
-      AP.emitNops(Num);
-      return true;
-    }
-    break;
-  }
   case RISCV::PseudoReadVLENB:
     OutMI.setOpcode(RISCV::CSRRS);
     OutMI.addOperand(MCOperand::createImm(
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1760,16 +1760,6 @@
 
   NoAutoPaddingScope NoPadScope(*OutStreamer);
 
-  const Function &F = MF->getFunction();
-  if (F.hasFnAttribute("patchable-function-entry")) {
-    unsigned Num;
-    if (F.getFnAttribute("patchable-function-entry")
-            .getValueAsString()
-            .getAsInteger(10, Num))
-      return;
-    emitX86Nops(*OutStreamer, Num, Subtarget);
-    return;
-  }
   // We want to emit the following pattern:
   //
   //   .p2align 1, ...
diff --git a/llvm/test/CodeGen/Hexagon/patchable-function-entry.ll b/llvm/test/CodeGen/Hexagon/patchable-function-entry.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/patchable-function-entry.ll
@@ -0,0 +1,25 @@
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
+
+define void @f0() "patchable-function-entry"="0" {
+; CHECK-LABEL: f0:
+; CHECK-NOT: nop
+; CHECK: jumpr r31
+  ret void
+}
+
+define void @f1() "patchable-function-entry"="1" {
+; CHECK-LABEL: f1:
+; CHECK: nop
+; CHECK-NOT: nop
+; CHECK: jumpr r31
+  ret void
+}
+
+define void @f2() "patchable-function-entry"="2" {
+; CHECK-LABEL: f2:
+; CHECK: nop
+; CHECK: nop
+; CHECK-NOT: nop
+; CHECK: jumpr r31
+  ret void
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/X86/patchable-function-entry.ll b/llvm/test/CodeGen/X86/patchable-function-entry.ll
--- a/llvm/test/CodeGen/X86/patchable-function-entry.ll
+++ b/llvm/test/CodeGen/X86/patchable-function-entry.ll
@@ -31,8 +31,8 @@
 define void @f2() "patchable-function-entry"="2" {
 ; CHECK-LABEL: f2:
 ; CHECK-NEXT: .Lfunc_begin2:
-; 32:          xchgw %ax, %ax
-; 64:          xchgw %ax, %ax
+; CHECK:  nop
+; CHECK-NEXT:  nop
 ; CHECK-NEXT:  ret
 ; CHECK:       .section __patchable_function_entries,"awo",@progbits,f2{{$}}
 ; 32:          .p2align 2
@@ -46,9 +46,9 @@
 define void @f3() "patchable-function-entry"="3" comdat {
 ; CHECK-LABEL: f3:
 ; CHECK-NEXT: .Lfunc_begin3:
-; 32:          xchgw %ax, %ax
-; 32-NEXT:     nop
-; 64:          nopl (%rax)
+; CHECK:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
 ; CHECK:       ret
 ; CHECK:       .section __patchable_function_entries,"aGwo",@progbits,f3,comdat,f3{{$}}
 ; 32:          .p2align 2
@@ -62,9 +62,11 @@
 define void @f5() "patchable-function-entry"="5" comdat {
 ; CHECK-LABEL: f5:
 ; CHECK-NEXT: .Lfunc_begin4:
-; 32-COUNT-2:  xchgw %ax, %ax
-; 32-NEXT:     nop
-; 64:          nopl 8(%rax,%rax)
+; CHECK:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
 ; CHECK-NEXT:  ret
 ; CHECK:       .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}}
 ; 32:          .p2align 2
@@ -81,7 +83,7 @@
 define void @f3_2() "patchable-function-entry"="1" "patchable-function-prefix"="2" {
 ; CHECK-LABEL: .type f3_2,@function
 ; CHECK-NEXT: .Ltmp0: # @f3_2
-; CHECK-NEXT:  nop
+; CHECK:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT: f3_2:
 ; CHECK:      # %bb.0: