diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3360,8 +3360,12 @@ SDValue Imm = RecordedNodes[RecNo].first; if (Imm->getOpcode() == ISD::Constant) { - const ConstantInt *Val=cast(Imm)->getConstantIntValue(); - Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch), + int64_t Val = cast(Imm)->getSExtValue(); + if (auto LSBaseNode = dyn_cast(NodeToMatch)) + if (LSBaseNode->getAddressingMode() == ISD::PRE_DEC || + LSBaseNode->getAddressingMode() == ISD::POST_DEC) + Val = -Val; + Imm = CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch), Imm.getValueType()); } else if (Imm->getOpcode() == ISD::ConstantFP) { const ConstantFP *Val=cast(Imm)->getConstantFPValue(); diff --git a/llvm/test/CodeGen/AArch64/pre-dec-addrmode-constant-offset.ll b/llvm/test/CodeGen/AArch64/pre-dec-addrmode-constant-offset.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/pre-dec-addrmode-constant-offset.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s + +; Reduced test from https://github.com/llvm/llvm-project/issues/60645. +; To check that we are generating -32 as offset for the first pre-dec store. + +define i8* @pr60645(i8* %ptr, i64 %t0) { +; CHECK-LABEL: pr60645: +; CHECK: // %bb.0: +; CHECK-NEXT: sub x8, x0, x1, lsl #2 +; CHECK-NEXT: str wzr, [x8, #-32]! +; CHECK-NEXT: stur wzr, [x8, #-8] +; CHECK-NEXT: ret + %t1 = add nuw nsw i64 %t0, 8 + %t2 = mul i64 %t1, -4 + %t3 = getelementptr i8, i8* %ptr, i64 %t2 + %t4 = bitcast i8* %t3 to i32* + store i32 0, i32* %t4, align 4 + %t5 = shl i64 %t1, 2 + %t6 = sub nuw nsw i64 -8, %t5 + %t7 = getelementptr i8, i8* %ptr, i64 %t6 + %t8 = bitcast i8* %t7 to i32* + store i32 0, i32* %t8, align 4 + ret i8* %ptr +}