diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1939,14 +1939,48 @@
     return false;
   }
 
+  /// Helper function for inserting a COPY to \p Dst at insertion point \p InsPt
+  /// in \p MBB block.
+  MachineInstr *buildCopy(MachineBasicBlock &MBB,
+                          MachineBasicBlock::iterator InsPt, const DebugLoc &DL,
+                          Register Dst) const {
+    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst);
+  }
+
+  /// Helper function for inserting a COPY to \p Dst from \p Src at insertion
+  /// point \p InsPt in \p MBB block.
+  MachineInstr *buildCopy(MachineBasicBlock &MBB,
+                          MachineBasicBlock::iterator InsPt, const DebugLoc &DL,
+                          Register Dst, Register Src, unsigned Flags = 0,
+                          unsigned SubReg = 0) const {
+    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
+        .addReg(Src, Flags, SubReg);
+  }
+
+  /// Helper function for inserting a COPY to \p Dst from \p Src at insertion
+  /// point \p InsPt in \p MBB block. Get the Debug Location from \p MIMD.
+  MachineInstrBuilder buildCopy(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator InsPt,
+                                const MIMetadata &MIMD, Register Dst,
+                                Register Src, unsigned Flags = 0,
+                                unsigned SubReg = 0) const {
+    MachineFunction &MF = *MBB.getParent();
+    MachineInstr *MI =
+        MF.CreateMachineInstr(get(TargetOpcode::COPY), MIMD.getDL());
+    MBB.insert(InsPt, MI);
+    return MachineInstrBuilder(MF, MI)
+        .setPCSections(MIMD.getPCSections())
+        .addReg(Dst, RegState::Define)
+        .addReg(Src, Flags, SubReg);
+  }
+
   /// During PHI eleimination lets target to make necessary checks and
   /// insert the copy to the PHI destination register in a target specific
   /// manner.
   virtual MachineInstr *createPHIDestinationCopy(
       MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
       const DebugLoc &DL, Register Src, Register Dst) const {
-    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
-        .addReg(Src);
+    return buildCopy(MBB, InsPt, DL, Dst, Src);
   }
 
   /// During PHI eleimination lets target to make necessary checks and
@@ -1957,8 +1991,7 @@
                                             const DebugLoc &DL, Register Src,
                                             unsigned SrcSubReg,
                                             Register Dst) const {
-    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
-        .addReg(Src, 0, SrcSubReg);
+    return buildCopy(MBB, InsPt, DL, Dst, Src, 0, SrcSubReg);
   }
 
   /// Returns a \p outliner::OutlinedFunction struct containing target-specific
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -624,8 +624,7 @@
     if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
       // We do not need the select instruction if both incoming values are
       // equal, but we do need a COPY.
-      BuildMI(*Head, FirstTerm, HeadDL, TII->get(TargetOpcode::COPY), DstReg)
-          .addReg(PI.TReg);
+      TII->buildCopy(*Head, FirstTerm, HeadDL, DstReg, PI.TReg);
     } else {
       TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg,
                         PI.FReg);
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -73,14 +73,11 @@
     // FIXME: The copy needs to have the classes constrained for its operands.
     // Use operand's regbank to get the class for old register (Reg).
     if (RegMO.isUse()) {
-      BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
-              TII.get(TargetOpcode::COPY), ConstrainedReg)
-          .addReg(Reg);
+      TII.buildCopy(MBB, InsertIt, InsertPt.getDebugLoc(), ConstrainedReg, Reg);
     } else {
       assert(RegMO.isDef() && "Must be a definition");
-      BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
-              TII.get(TargetOpcode::COPY), Reg)
-          .addReg(ConstrainedReg);
+      TII.buildCopy(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), Reg,
+                    ConstrainedReg);
     }
     if (GISelChangeObserver *Observer = MF.getObserver()) {
       Observer->changingInstr(*RegMO.getParent());
@@ -752,8 +749,7 @@
       MRI.setType(LiveIn, RegTy);
   }
 
-  BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
-    .addReg(PhysReg);
+  TII.buildCopy(EntryMBB, EntryMBB.begin(), DL, LiveIn, PhysReg);
   if (!EntryMBB.isLiveIn(PhysReg))
     EntryMBB.addLiveIn(PhysReg);
   return LiveIn;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -649,8 +649,7 @@
 
   // No luck, create a virtual register.
   Register VirtReg = MRI.createVirtualRegister(RC);
-  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
-    .addReg(PhysReg, RegState::Kill);
+  TII.buildCopy(*this, I, DebugLoc(), VirtReg, PhysReg, RegState::Kill);
   if (!LiveIn)
     addLiveIn(PhysReg);
   return VirtReg;
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -418,9 +418,8 @@
       MachineBasicBlock &PredB = *PI.getOperand(i+1).getMBB();
       MachineBasicBlock::iterator At = PredB.getFirstTerminator();
       const DebugLoc &DL = PredB.findDebugLoc(At);
-      auto Copy = BuildMI(PredB, At, DL, TII->get(TargetOpcode::COPY), NewReg)
-                    .addReg(RegOp.getReg(), getRegState(RegOp),
-                            RegOp.getSubReg());
+      auto Copy = TII->buildCopy(PredB, At, DL, NewReg, RegOp.getReg(),
+                                 getRegState(RegOp), RegOp.getSubReg());
       Slots.insertMachineInstrInMaps(*Copy);
       RegOp.setReg(NewReg);
       RegOp.setSubReg(0);
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -481,9 +481,8 @@
         --i; --e;
       } else {
         // Emit a copy.
-        BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
-                TII.get(TargetOpcode::COPY), LiveIns[i].second)
-          .addReg(LiveIns[i].first);
+        TII.buildCopy(*EntryMBB, EntryMBB->begin(), DebugLoc(),
+                      LiveIns[i].second, LiveIns[i].first);
 
         // Add the register to the entry block live-in set.
         EntryMBB->addLiveIn(LiveIns[i].first);
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -823,9 +823,7 @@
             // We split the lifetime when we find the first use.
             if (SplitReg == 0) {
               SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def));
-              BuildMI(*KernelBB, MI, MI->getDebugLoc(),
-                      TII->get(TargetOpcode::COPY), SplitReg)
-                  .addReg(Def);
+              TII->buildCopy(*KernelBB, MI, MI->getDebugLoc(), SplitReg, Def);
             }
             BBJ.substituteRegister(Def, SplitReg, 0, *TRI);
           }
@@ -1190,9 +1188,7 @@
         UseOp.setReg(ReplaceReg);
       else {
         Register SplitReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
-        BuildMI(*BB, UseMI, UseMI->getDebugLoc(), TII->get(TargetOpcode::COPY),
-                SplitReg)
-            .addReg(ReplaceReg);
+        TII->buildCopy(*BB, UseMI, UseMI->getDebugLoc(), SplitReg, ReplaceReg);
         UseOp.setReg(SplitReg);
       }
     }
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -602,9 +602,8 @@
         RC = MRI->getRegClass(UseMI->getOperand(0).getReg());
 
       Register NewVR = MRI->createVirtualRegister(RC);
-      BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
-              TII->get(TargetOpcode::COPY), NewVR)
-        .addReg(DstReg, 0, SubIdx);
+      TII->buildCopy(*UseMBB, UseMI, UseMI->getDebugLoc(), NewVR, DstReg, 0,
+                     SubIdx);
       if (UseSrcSubIdx)
         UseMO->setSubReg(0);
 
@@ -1251,9 +1250,8 @@
   Register NewVReg = MRI->createVirtualRegister(DefRC);
 
   MachineInstr *NewCopy =
-      BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
-              TII->get(TargetOpcode::COPY), NewVReg)
-          .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
+      TII->buildCopy(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
+                     NewVReg, NewSrc.Reg, 0, NewSrc.SubReg);
 
   if (Def.SubReg) {
     NewCopy->getOperand(0).setSubReg(Def.SubReg);
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -603,9 +603,8 @@
       unsigned Reg = CS.getReg();
 
       if (CS.isSpilledToReg()) {
-        BuildMI(SaveBlock, I, DebugLoc(),
-                TII.get(TargetOpcode::COPY), CS.getDstReg())
-          .addReg(Reg, getKillRegState(true));
+        TII.buildCopy(SaveBlock, I, DebugLoc(), CS.getDstReg(), Reg,
+                      getKillRegState(true));
       } else {
         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
         TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC,
@@ -631,8 +630,8 @@
     for (const CalleeSavedInfo &CI : reverse(CSI)) {
       unsigned Reg = CI.getReg();
       if (CI.isSpilledToReg()) {
-        BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
-          .addReg(CI.getDstReg(), getKillRegState(true));
+        TII.buildCopy(RestoreBlock, I, DebugLoc(), Reg, CI.getDstReg(),
+                      getKillRegState(true));
       } else {
         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
         TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC,
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -892,9 +892,8 @@
         std::next((MachineBasicBlock::iterator)MI.getIterator());
       LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
                         << printReg(PrevReg, TRI) << '\n');
-      BuildMI(*MBB, InsertBefore, MI.getDebugLoc(),
-              TII->get(TargetOpcode::COPY), PrevReg)
-        .addReg(LRI->PhysReg, llvm::RegState::Kill);
+      TII->buildCopy(*MBB, InsertBefore, MI.getDebugLoc(), PrevReg,
+                     LRI->PhysReg, llvm::RegState::Kill);
     }
     MachineOperand &MO = MI.getOperand(OpNum);
     if (MO.getSubReg() && !MO.isUndef()) {
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1184,9 +1184,8 @@
                       << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
 
     // Insert new copy to CopyLeftBB.
-    MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
-                                      TII->get(TargetOpcode::COPY), IntB.reg())
-                                  .addReg(IntA.reg());
+    MachineInstr *NewCopyMI = TII->buildCopy(
+        *CopyLeftBB, InsPos, CopyMI.getDebugLoc(), IntB.reg(), IntA.reg());
     SlotIndex NewCopyIdx =
         LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
     IntB.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1449,8 +1449,7 @@
   MVT Ty = ETy.getSimpleVT();
   const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
   Register ResultReg = createResultReg(TyRegClass);
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
-          TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
+  TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg, Reg);
 
   updateValueMap(I, ResultReg);
   return true;
@@ -1907,8 +1906,7 @@
       // If it's not legal to COPY between the register classes, something
       // has gone very wrong before we got here.
       Register NewOp = createResultReg(RegClass);
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
-              TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
+      TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, NewOp, Op);
       return NewOp;
     }
   }
@@ -1937,9 +1935,8 @@
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
 
   return ResultReg;
@@ -1962,9 +1959,8 @@
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addReg(Op1);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -1989,9 +1985,8 @@
         .addReg(Op0)
         .addReg(Op1)
         .addReg(Op2);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -2012,9 +2007,8 @@
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addImm(Imm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -2037,9 +2031,8 @@
         .addReg(Op0)
         .addImm(Imm1)
         .addImm(Imm2);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -2057,9 +2050,8 @@
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addFPImm(FPImm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -2083,9 +2075,8 @@
         .addReg(Op0)
         .addReg(Op1)
         .addImm(Imm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -2100,9 +2091,8 @@
         .addImm(Imm);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II).addImm(Imm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
@@ -2114,8 +2104,7 @@
          "Cannot yet extract from physregs");
   const TargetRegisterClass *RC = MRI.getRegClass(Op0);
   MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-          ResultReg).addReg(Op0, 0, Idx);
+  TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg, Op0, 0, Idx);
   return ResultReg;
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -171,8 +171,7 @@
   } else {
     // Create the reg, emit the copy.
     VRBase = MRI->createVirtualRegister(DstRC);
-    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
-            VRBase).addReg(SrcReg);
+    TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), VRBase, SrcReg);
   }
 
   SDValue Op(Node, ResNo);
@@ -329,8 +328,8 @@
         OpRC = TRI->getAllocatableClass(OpRC);
         assert(OpRC && "Constraints cannot be fulfilled for allocation");
         Register NewVReg = MRI->createVirtualRegister(OpRC);
-        BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
-                TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
+        TII->buildCopy(*MBB, InsertPos, Op.getNode()->getDebugLoc(), NewVReg,
+                       VReg);
         VReg = NewVReg;
       } else {
         assert(ConstrainedRC->isAllocatable() &&
@@ -396,8 +395,8 @@
 
     if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
       Register NewVReg = MRI->createVirtualRegister(IIRC);
-      BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
-               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
+      TII->buildCopy(*MBB, InsertPos, Op.getNode()->getDebugLoc(), NewVReg,
+                     VReg);
       VReg = NewVReg;
     }
     // Turn additional physreg operands into implicit uses on non-variadic
@@ -465,8 +464,7 @@
   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
   assert(RC && "No legal register class for VT supports that SubIdx");
   Register NewReg = MRI->createVirtualRegister(RC);
-  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
-    .addReg(VReg);
+  TII->buildCopy(*MBB, InsertPos, DL, NewReg, VReg);
   return NewReg;
 }
 
@@ -522,8 +520,7 @@
       // to a copy
       // r1026 = copy r1024
       VRBase = MRI->createVirtualRegister(TRC);
-      BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
-              TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
+      TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), VRBase, SrcReg);
       MRI->clearKillFlags(SrcReg);
     } else {
       // Reg may not support a SubIdx sub-register, and we may need to
@@ -538,9 +535,9 @@
         VRBase = MRI->createVirtualRegister(TRC);
 
       // Create the extract_subreg machine instruction.
-      MachineInstrBuilder CopyMI =
-          BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
-                  TII->get(TargetOpcode::COPY), VRBase);
+      MachineInstrBuilder CopyMI = MachineInstrBuilder(
+          *MBB->getParent(),
+          TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), VRBase));
       if (Reg.isVirtual())
         CopyMI.addReg(Reg, 0, SubIdx);
       else
@@ -615,8 +612,7 @@
   const TargetRegisterClass *DstRC =
     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
   Register NewVReg = MRI->createVirtualRegister(DstRC);
-  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
-    NewVReg).addReg(VReg);
+  TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), NewVReg, VReg);
 
   SDValue Op(Node, 0);
   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
@@ -1228,8 +1224,7 @@
     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
       break;
 
-    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
-            DestReg).addReg(SrcReg);
+    TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), DestReg, SrcReg);
     break;
   }
   case ISD::CopyFromReg: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -826,8 +826,7 @@
           break;
         }
       }
-      BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
-        .addReg(VRI->second);
+      TII->buildCopy(*BB, InsertPos, DebugLoc(), Reg, VRI->second);
     } else {
       // Copy from physical register.
       assert(Pred.getReg() && "Unknown physical register!");
@@ -835,8 +834,7 @@
       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
       (void)isNew; // Silence compiler warning.
       assert(isNew && "Node emitted out of order - early");
-      BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
-          .addReg(Pred.getReg());
+      TII->buildCopy(*BB, InsertPos, DebugLoc(), VRBase, Pred.getReg());
     }
     break;
   }
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1252,9 +1252,8 @@
         assert(EHPhysReg && "target lacks exception pointer register");
         MBB->addLiveIn(EHPhysReg);
         unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
-        BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
-                TII->get(TargetOpcode::COPY), VReg)
-            .addReg(EHPhysReg, RegState::Kill);
+        TII->buildCopy(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), VReg,
+                       EHPhysReg, RegState::Kill);
       }
     }
     return true;
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -534,14 +534,14 @@
 }
 
 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
-    LaneBitmask LaneMask, MachineBasicBlock &MBB,
-    MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
-  const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
+                                 LaneBitmask LaneMask, MachineBasicBlock &MBB,
+                                 MachineBasicBlock::iterator InsertBefore,
+                                 bool Late, unsigned RegIdx) {
   SlotIndexes &Indexes = *LIS.getSlotIndexes();
   if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
     // The full vreg is copied.
     MachineInstr *CopyMI =
-        BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
+        TII.buildCopy(MBB, InsertBefore, DebugLoc(), ToReg, FromReg);
     return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
   }
 
diff --git a/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp b/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp
--- a/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp
+++ b/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp
@@ -228,9 +228,8 @@
         assert(!VRegs.empty() &&
                "No predecessors?  Is the Calling Convention correct?");
         Register DestReg = UUseVReg;
-        BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY),
-                DestReg)
-            .addReg(VRegs[0].second);
+        TII->buildCopy(*MBB, MBB->getFirstNonPHI(), DLoc, DestReg,
+                       VRegs[0].second);
         continue;
       }
 
diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp
--- a/llvm/lib/CodeGen/TailDuplicator.cpp
+++ b/llvm/lib/CodeGen/TailDuplicator.cpp
@@ -443,9 +443,8 @@
             // class constraints. An explicit COPY is necessary. Create one
             // that can be reused.
             Register NewReg = MRI->createVirtualRegister(OrigRC);
-            BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(),
-                    TII->get(TargetOpcode::COPY), NewReg)
-                .addReg(VI->second.Reg, 0, VI->second.SubReg);
+            TII->buildCopy(*PredBB, NewMI, NewMI.getDebugLoc(), NewReg,
+                           VI->second.Reg, 0, VI->second.SubReg);
             LocalVRMap.erase(VI);
             LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
             MO.setReg(NewReg);
@@ -1033,10 +1032,9 @@
       SmallVectorImpl<std::pair<Register, RegSubRegPair>> &CopyInfos,
       SmallVectorImpl<MachineInstr*> &Copies) {
   MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
-  const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
   for (auto &CI : CopyInfos) {
-    auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
-                .addReg(CI.second.Reg, 0, CI.second.SubReg);
+    auto C = TII->buildCopy(*MBB, Loc, DebugLoc(), CI.first, CI.second.Reg, 0,
+                            CI.second.SubReg);
     Copies.push_back(C);
   }
 }
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1492,8 +1492,9 @@
 #endif
 
     // Emit a copy.
-    MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
-                                      TII->get(TargetOpcode::COPY), RegA);
+    MachineInstrBuilder MIB = MachineInstrBuilder(
+        *MI->getParent()->getParent(),
+        TII->buildCopy(*MI->getParent(), MI, MI->getDebugLoc(), RegA));
     // If this operand is folding a truncation, the truncation now moves to the
     // copy so that the register classes remain valid for the operands.
     MIB.addReg(RegB, 0, SubRegB);
diff --git a/llvm/lib/CodeGen/UnreachableBlockElim.cpp b/llvm/lib/CodeGen/UnreachableBlockElim.cpp
--- a/llvm/lib/CodeGen/UnreachableBlockElim.cpp
+++ b/llvm/lib/CodeGen/UnreachableBlockElim.cpp
@@ -182,9 +182,8 @@
             // insert a COPY instead of simply replacing the output
             // with the input.
             const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo();
-            BuildMI(BB, BB.getFirstNonPHI(), phi->getDebugLoc(),
-                    TII->get(TargetOpcode::COPY), OutputReg)
-                .addReg(InputReg, getRegState(Input), InputSub);
+            TII->buildCopy(BB, BB.getFirstNonPHI(), phi->getDebugLoc(),
+                           OutputReg, InputReg, getRegState(Input), InputSub);
           }
           phi++->eraseFromParent();
         }