diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4569,6 +4569,9 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + GlobalAddressSDNode *GA = cast(Op); + if (DAG.getTarget().useEmulatedTLS()) + return LowerToTLSEmulatedModel(GA, DAG); GlobalAddressSDNode *N = cast(Op); assert(N->getOffset() == 0 && "unexpected offset in global node"); diff --git a/llvm/test/CodeGen/RISCV/emutls_generic.ll b/llvm/test/CodeGen/RISCV/emutls_generic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/emutls_generic.ll @@ -0,0 +1,111 @@ +; RUN: llc < %s -emulated-tls -mtriple=riscv64-gnu-linux -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=RISCV_64 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv64-gnu-linux -relocation-model=pic -O3 \ +; RUN: | FileCheck -check-prefix=RISCV_64 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv64-gnu-linux -O3 \ +; RUN: | FileCheck -check-prefix=RISCV_64 %s + +; RUN: llc < %s -emulated-tls -mtriple=riscv32-gnu-linux -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=RISCV_32 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv32-gnu-linux -relocation-model=pic -O3 \ +; RUN: | FileCheck -check-prefix=RISCV_32 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv32-gnu-linux -O3 \ +; RUN: | FileCheck -check-prefix=RISCV_32 %s + +; RUN: llc < %s -mtriple=riscv64-gnu-linux -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=NoEMU %s +; RUN: llc < %s -mtriple=riscv32-gnu-linux -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=NoEMU %s + +; NoEMU-NOT: __emutls + +; Make sure that TLS symbols are emitted in expected order. + +@external_x = external thread_local global i32, align 8 +@external_y = thread_local global i8 7, align 2 +@internal_y = internal thread_local global i64 9, align 16 + +define ptr @get_external_x() { +entry: + ret ptr @external_x +} + +define ptr @get_external_y() { +entry: + ret ptr @external_y +} + +define ptr @get_internal_y() { +entry: + ret ptr @internal_y +} + +; RISCV_64-LABEL: get_external_x: +; RISCV_64: __emutls_v.external_x +; RISCV_64: __emutls_get_address +; RISCV_64-LABEL: get_external_y: +; RISCV_64: __emutls_v.external_y +; RISCV_64: __emutls_get_address +; RISCV_64-LABEL: get_internal_y: +; RISCV_64: __emutls_v.internal_y +; RISCV_64: __emutls_get_address +; RISCV_64-NOT: __emutls_t.external_x +; RISCV_64-NOT: __emutls_v.external_x: +; RISCV_64: .data{{$}} +; RISCV_64: .globl __emutls_v.external_y +; RISCV_64: .p2align 3 +; RISCV_64-LABEL: __emutls_v.external_y: +; RISCV_64-NEXT: .quad 1 +; RISCV_64-NEXT: .quad 2 +; RISCV_64-NEXT: .quad 0 +; RISCV_64-NEXT: .quad __emutls_t.external_y +; RISCV_64-NOT: __emutls_v.external_x: +; RISCV_64: .section .r{{o?}}data, +; RISCV_64-LABEL: __emutls_t.external_y: +; RISCV_64-NEXT: .byte 7 +; RISCV_64: .data{{$}} +; RISCV_64-NOT: .globl __emutls_v +; RISCV_64: .p2align 3 +; RISCV_64-LABEL: __emutls_v.internal_y: +; RISCV_64-NEXT: .quad 8 +; RISCV_64-NEXT: .quad 16 +; RISCV_64-NEXT: .quad 0 +; RISCV_64-NEXT: .quad __emutls_t.internal_y +; RISCV_64: .section .r{{o?}}data, +; RISCV_64-LABEL: __emutls_t.internal_y: +; RISCV_64-NEXT: .quad 9 + +; RISCV_32-LABEL: get_external_x: +; RISCV_32: __emutls_v.external_x +; RISCV_32: __emutls_get_address +; RISCV_32-LABEL: get_external_y: +; RISCV_32: __emutls_v.external_y +; RISCV_32: __emutls_get_address +; RISCV_32-LABEL: get_internal_y: +; RISCV_32: __emutls_v.internal_y +; RISCV_32: __emutls_get_address +; RISCV_32-NOT: __emutls_t.external_x +; RISCV_32-NOT: __emutls_v.external_x: +; RISCV_32: .data{{$}} +; RISCV_32: .globl __emutls_v.external_y +; RISCV_32: .p2align 2 +; RISCV_32-LABEL: __emutls_v.external_y: +; RISCV_32-NEXT: .word 1 +; RISCV_32-NEXT: .word 2 +; RISCV_32-NEXT: .word 0 +; RISCV_32-NEXT: .word __emutls_t.external_y +; RISCV_32-NOT: __emutls_v.external_x: +; RISCV_32: .section .r{{o?}}data, +; RISCV_32-LABEL: __emutls_t.external_y: +; RISCV_32-NEXT: .byte 7 +; RISCV_32: .data{{$}} +; RISCV_32-NOT: .globl __emutls_v +; RISCV_32: .p2align 2 +; RISCV_32-LABEL: __emutls_v.internal_y: +; RISCV_32-NEXT: .word 8 +; RISCV_32-NEXT: .word 16 +; RISCV_32-NEXT: .word 0 +; RISCV_32-NEXT: .word __emutls_t.internal_y +; RISCV_32: .section .r{{o?}}data, +; RISCV_32-LABEL: __emutls_t.internal_y: +; RISCV_32-NEXT: .quad 9