diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -825,10 +825,10 @@ //////////////////////////////////////////////////////////////////////////////// // Logical operations -defm SVAND : SInstZPZZ<"svand", "csilUcUsUiUl", "aarch64_sve_and", "aarch64_sve_and">; -defm SVBIC : SInstZPZZ<"svbic", "csilUcUsUiUl", "aarch64_sve_bic", "aarch64_sve_bic">; -defm SVEOR : SInstZPZZ<"sveor", "csilUcUsUiUl", "aarch64_sve_eor", "aarch64_sve_eor">; -defm SVORR : SInstZPZZ<"svorr", "csilUcUsUiUl", "aarch64_sve_orr", "aarch64_sve_orr">; +defm SVAND : SInstZPZZ<"svand", "csilUcUsUiUl", "aarch64_sve_and", "aarch64_sve_and_u">; +defm SVBIC : SInstZPZZ<"svbic", "csilUcUsUiUl", "aarch64_sve_bic", "aarch64_sve_bic_u">; +defm SVEOR : SInstZPZZ<"sveor", "csilUcUsUiUl", "aarch64_sve_eor", "aarch64_sve_eor_u">; +defm SVORR : SInstZPZZ<"svorr", "csilUcUsUiUl", "aarch64_sve_orr", "aarch64_sve_orr_u">; defm SVCNOT : SInstZPZ<"svcnot", "csilUcUsUiUl", "aarch64_sve_cnot">; defm SVNOT : SInstZPZ<"svnot", "csilUcUsUiUl", "aarch64_sve_not">; diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c @@ -296,12 +296,12 @@ // CHECK-LABEL: @test_svand_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_svand_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svand_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -312,13 +312,13 @@ // CHECK-LABEL: @test_svand_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svand_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svand_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -329,13 +329,13 @@ // CHECK-LABEL: @test_svand_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svand_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svand_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -346,13 +346,13 @@ // CHECK-LABEL: @test_svand_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svand_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svand_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -362,12 +362,12 @@ // CHECK-LABEL: @test_svand_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_svand_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svand_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) @@ -378,13 +378,13 @@ // CHECK-LABEL: @test_svand_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svand_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svand_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) @@ -395,13 +395,13 @@ // CHECK-LABEL: @test_svand_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svand_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svand_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) @@ -412,13 +412,13 @@ // CHECK-LABEL: @test_svand_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svand_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svand_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) @@ -774,14 +774,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svand_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svand_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -794,7 +794,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svand_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -802,7 +802,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svand_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -815,7 +815,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svand_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -823,7 +823,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svand_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -836,7 +836,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svand_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -844,7 +844,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svand_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -856,14 +856,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svand_n_u8_xu10__SVBool_tu11__SVUint8_th( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svand_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) @@ -876,7 +876,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svand_n_u16_xu10__SVBool_tu12__SVUint16_tt( @@ -884,7 +884,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svand_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) @@ -897,7 +897,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svand_n_u32_xu10__SVBool_tu12__SVUint32_tj( @@ -905,7 +905,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svand_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) @@ -918,7 +918,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svand_n_u64_xu10__SVBool_tu12__SVUint64_tm( @@ -926,7 +926,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svand_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c @@ -296,12 +296,12 @@ // CHECK-LABEL: @test_svbic_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_svbic_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svbic_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -312,13 +312,13 @@ // CHECK-LABEL: @test_svbic_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svbic_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svbic_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -329,13 +329,13 @@ // CHECK-LABEL: @test_svbic_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svbic_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svbic_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -346,13 +346,13 @@ // CHECK-LABEL: @test_svbic_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svbic_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svbic_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -362,12 +362,12 @@ // CHECK-LABEL: @test_svbic_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_svbic_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svbic_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) @@ -378,13 +378,13 @@ // CHECK-LABEL: @test_svbic_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svbic_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svbic_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) @@ -395,13 +395,13 @@ // CHECK-LABEL: @test_svbic_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svbic_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svbic_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) @@ -412,13 +412,13 @@ // CHECK-LABEL: @test_svbic_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svbic_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svbic_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) @@ -774,14 +774,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svbic_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svbic_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -794,7 +794,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svbic_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -802,7 +802,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svbic_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -815,7 +815,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svbic_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -823,7 +823,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svbic_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -836,7 +836,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svbic_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -844,7 +844,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svbic_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -856,14 +856,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svbic_n_u8_xu10__SVBool_tu11__SVUint8_th( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svbic_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) @@ -876,7 +876,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svbic_n_u16_xu10__SVBool_tu12__SVUint16_tt( @@ -884,7 +884,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svbic_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) @@ -897,7 +897,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svbic_n_u32_xu10__SVBool_tu12__SVUint32_tj( @@ -905,7 +905,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svbic_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) @@ -918,7 +918,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svbic_n_u64_xu10__SVBool_tu12__SVUint64_tm( @@ -926,7 +926,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svbic_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c @@ -296,12 +296,12 @@ // CHECK-LABEL: @test_sveor_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_sveor_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_sveor_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -312,13 +312,13 @@ // CHECK-LABEL: @test_sveor_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_sveor_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_sveor_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -329,13 +329,13 @@ // CHECK-LABEL: @test_sveor_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_sveor_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_sveor_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -346,13 +346,13 @@ // CHECK-LABEL: @test_sveor_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_sveor_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_sveor_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -362,12 +362,12 @@ // CHECK-LABEL: @test_sveor_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_sveor_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_sveor_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) @@ -378,13 +378,13 @@ // CHECK-LABEL: @test_sveor_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_sveor_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_sveor_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) @@ -395,13 +395,13 @@ // CHECK-LABEL: @test_sveor_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_sveor_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_sveor_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) @@ -412,13 +412,13 @@ // CHECK-LABEL: @test_sveor_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_sveor_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_sveor_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) @@ -774,14 +774,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_sveor_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_sveor_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -794,7 +794,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_sveor_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -802,7 +802,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_sveor_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -815,7 +815,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_sveor_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -823,7 +823,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_sveor_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -836,7 +836,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_sveor_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -844,7 +844,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_sveor_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -856,14 +856,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_sveor_n_u8_xu10__SVBool_tu11__SVUint8_th( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_sveor_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) @@ -876,7 +876,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_sveor_n_u16_xu10__SVBool_tu12__SVUint16_tt( @@ -884,7 +884,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_sveor_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) @@ -897,7 +897,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_sveor_n_u32_xu10__SVBool_tu12__SVUint32_tj( @@ -905,7 +905,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_sveor_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) @@ -918,7 +918,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_sveor_n_u64_xu10__SVBool_tu12__SVUint64_tm( @@ -926,7 +926,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_sveor_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c @@ -296,12 +296,12 @@ // CHECK-LABEL: @test_svorr_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_svorr_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svorr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -312,13 +312,13 @@ // CHECK-LABEL: @test_svorr_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svorr_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svorr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -329,13 +329,13 @@ // CHECK-LABEL: @test_svorr_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svorr_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svorr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -346,13 +346,13 @@ // CHECK-LABEL: @test_svorr_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svorr_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svorr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -362,12 +362,12 @@ // CHECK-LABEL: @test_svorr_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z15test_svorr_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svorr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) @@ -378,13 +378,13 @@ // CHECK-LABEL: @test_svorr_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svorr_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svorr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) @@ -395,13 +395,13 @@ // CHECK-LABEL: @test_svorr_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svorr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svorr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) @@ -412,13 +412,13 @@ // CHECK-LABEL: @test_svorr_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svorr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svorr_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) @@ -774,14 +774,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svorr_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svorr_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -794,7 +794,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svorr_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -802,7 +802,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svorr_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -815,7 +815,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svorr_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -823,7 +823,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svorr_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -836,7 +836,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svorr_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -844,7 +844,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svorr_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -856,14 +856,14 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svorr_n_u8_xu10__SVBool_tu11__SVUint8_th( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svorr_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) @@ -876,7 +876,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svorr_n_u16_xu10__SVBool_tu12__SVUint16_tt( @@ -884,7 +884,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svorr_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) @@ -897,7 +897,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svorr_n_u32_xu10__SVBool_tu12__SVUint32_tj( @@ -905,7 +905,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svorr_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) @@ -918,7 +918,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svorr_n_u64_xu10__SVBool_tu12__SVUint64_tm( @@ -926,7 +926,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svorr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -1892,11 +1892,15 @@ // def int_aarch64_sve_and : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_and_u: AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_bic : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_bic_u: AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_cnot : AdvSIMD_Merged1VectorArg_Intrinsic; def int_aarch64_sve_eor : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_eor_u: AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_not : AdvSIMD_Merged1VectorArg_Intrinsic; def int_aarch64_sve_orr : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_orr_u: AdvSIMD_Pred2VectorArg_Intrinsic; // // Conversion diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -18307,12 +18307,24 @@ return convertMergedOpToPredOp(N, ISD::SUB, DAG, true, true); case Intrinsic::aarch64_sve_and: return convertMergedOpToPredOp(N, ISD::AND, DAG, true); + case Intrinsic::aarch64_sve_and_u: + return DAG.getNode(ISD::AND, SDLoc(N), N->getValueType(0), N->getOperand(2), + N->getOperand(3)); case Intrinsic::aarch64_sve_bic: return convertMergedOpToPredOp(N, AArch64ISD::BIC, DAG, true); + case Intrinsic::aarch64_sve_bic_u: + return DAG.getNode(AArch64ISD::BIC, SDLoc(N), N->getValueType(0), + N->getOperand(2), N->getOperand(3)); case Intrinsic::aarch64_sve_eor: return convertMergedOpToPredOp(N, ISD::XOR, DAG, true); + case Intrinsic::aarch64_sve_eor_u: + return DAG.getNode(ISD::XOR, SDLoc(N), N->getValueType(0), N->getOperand(2), + N->getOperand(3)); case Intrinsic::aarch64_sve_orr: return convertMergedOpToPredOp(N, ISD::OR, DAG, true); + case Intrinsic::aarch64_sve_orr_u: + return DAG.getNode(ISD::OR, SDLoc(N), N->getValueType(0), N->getOperand(2), + N->getOperand(3)); case Intrinsic::aarch64_sve_sabd: return convertMergedOpToPredOp(N, ISD::ABDS, DAG, true); case Intrinsic::aarch64_sve_sabd_u: diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-undef.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-undef.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-undef.ll @@ -0,0 +1,440 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mattr=+sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; +; AND +; + +define @and_i8( %pg, %a, %b) { +; CHECK-LABEL: and_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.and.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @and_i16( %pg, %a, %b) { +; CHECK-LABEL: and_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.and.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @and_i32( %pg, %a, %b) { +; CHECK-LABEL: and_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.and.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @and_i64( %pg, %a, %b) { +; CHECK-LABEL: and_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.and.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; AND (immediate) +; + +define @and_imm_i8( %pg, %a) { +; CHECK-LABEL: and_imm_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.b, z0.b, #0x3 +; CHECK-NEXT: ret + %imm = insertelement undef, i8 3, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.and.u.nxv16i8( %pg, + %a, + %imm.splat) + ret %out +} + +define @and_imm_i16( %pg, %a) { +; CHECK-LABEL: and_imm_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.h, z0.h, #0x4 +; CHECK-NEXT: ret + %imm = insertelement undef, i16 4, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.and.u.nxv8i16( %pg, + %a, + %imm.splat) + ret %out +} + +define @and_imm_i32( %pg, %a) { +; CHECK-LABEL: and_imm_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.s, z0.s, #0x10 +; CHECK-NEXT: ret + %imm = insertelement undef, i32 16, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.and.u.nxv4i32( %pg, + %a, + %imm.splat) + ret %out +} + +define @and_imm_i64( %pg, %a) { +; CHECK-LABEL: and_imm_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.d, z0.d, #0x20 +; CHECK-NEXT: ret + %imm = insertelement undef, i64 32, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.and.u.nxv2i64( %pg, + %a, + %imm.splat) + ret %out +} + +; +; EOR +; + +define @eor_i8( %pg, %a, %b) { +; CHECK-LABEL: eor_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.eor.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @eor_i16( %pg, %a, %b) { +; CHECK-LABEL: eor_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.eor.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @eor_i32( %pg, %a, %b) { +; CHECK-LABEL: eor_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.eor.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @eor_i64( %pg, %a, %b) { +; CHECK-LABEL: eor_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.eor.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; EOR (immediate) +; + +define @eor_imm_i8( %pg, %a) { +; CHECK-LABEL: eor_imm_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.b, z0.b, #0x7 +; CHECK-NEXT: ret + %imm = insertelement undef, i8 7, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.eor.u.nxv16i8( %pg, + %a, + %imm.splat) + ret %out +} + +define @eor_imm_i16( %pg, %a) { +; CHECK-LABEL: eor_imm_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.h, z0.h, #0x8 +; CHECK-NEXT: ret + %imm = insertelement undef, i16 8, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.eor.u.nxv8i16( %pg, + %a, + %imm.splat) + ret %out +} + +define @eor_imm_i32( %pg, %a) { +; CHECK-LABEL: eor_imm_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.s, z0.s, #0x10 +; CHECK-NEXT: ret + %imm = insertelement undef, i32 16, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.eor.u.nxv4i32( %pg, + %a, + %imm.splat) + ret %out +} + +define @eor_imm_i64( %pg, %a) { +; CHECK-LABEL: eor_imm_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: eor z0.d, z0.d, #0x20 +; CHECK-NEXT: ret + %imm = insertelement undef, i64 32, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.eor.u.nxv2i64( %pg, + %a, + %imm.splat) + ret %out +} + +; +; ORR +; + +define @orr_i8( %pg, %a, %b) { +; CHECK-LABEL: orr_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.orr.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @orr_i16( %pg, %a, %b) { +; CHECK-LABEL: orr_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.orr.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @orr_i32( %pg, %a, %b) { +; CHECK-LABEL: orr_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.orr.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @orr_i64( %pg, %a, %b) { +; CHECK-LABEL: orr_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.orr.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; ORR (immediate) +; + +define @orr_imm_i8( %pg, %a) { +; CHECK-LABEL: orr_imm_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.b, z0.b, #0x8 +; CHECK-NEXT: ret + %imm = insertelement undef, i8 8, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.orr.u.nxv16i8( %pg, + %a, + %imm.splat) + ret %out +} + +define @orr_imm_i16( %pg, %a) { +; CHECK-LABEL: orr_imm_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.h, z0.h, #0xc +; CHECK-NEXT: ret + %imm = insertelement undef, i16 12, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.orr.u.nxv8i16( %pg, + %a, + %imm.splat) + ret %out +} + +define @orr_imm_i32( %pg, %a) { +; CHECK-LABEL: orr_imm_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.s, z0.s, #0x10 +; CHECK-NEXT: ret + %imm = insertelement undef, i32 16, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.orr.u.nxv4i32( %pg, + %a, + %imm.splat) + ret %out +} + +define @orr_imm_i64( %pg, %a) { +; CHECK-LABEL: orr_imm_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: orr z0.d, z0.d, #0x20 +; CHECK-NEXT: ret + %imm = insertelement undef, i64 32, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.orr.u.nxv2i64( %pg, + %a, + %imm.splat) + ret %out +} + +; +; BIC +; + +define @bic_i8( %pg, %a, %b) { +; CHECK-LABEL: bic_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.bic.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @bic_i16( %pg, %a, %b) { +; CHECK-LABEL: bic_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.bic.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @bic_i32( %pg, %a, %b) { +; CHECK-LABEL: bic_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.bic.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @bic_i64( %pg, %a, %b) { +; CHECK-LABEL: bic_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.bic.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; BIC (immediate) +; + +define @bic_imm_i8( %pg, %a) { +; CHECK-LABEL: bic_imm_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.b, z0.b, #0xf8 +; CHECK-NEXT: ret + %imm = insertelement undef, i8 7, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.bic.u.nxv16i8( %pg, + %a, + %imm.splat) + ret %out +} + +define @bic_imm_i16( %pg, %a) { +; CHECK-LABEL: bic_imm_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.h, z0.h, #0xfff7 +; CHECK-NEXT: ret + %imm = insertelement undef, i16 8, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.bic.u.nxv8i16( %pg, + %a, + %imm.splat) + ret %out +} + +define @bic_imm_i32( %pg, %a) { +; CHECK-LABEL: bic_imm_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.s, z0.s, #0xffffffef +; CHECK-NEXT: ret + %imm = insertelement undef, i32 16, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.bic.u.nxv4i32( %pg, + %a, + %imm.splat) + ret %out +} + +define @bic_imm_i64( %pg, %a) { +; CHECK-LABEL: bic_imm_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.d, z0.d, #0xffffffffffffffdf +; CHECK-NEXT: ret + %imm = insertelement undef, i64 32, i32 0 + %imm.splat = shufflevector %imm, undef, zeroinitializer + %out = call @llvm.aarch64.sve.bic.u.nxv2i64( %pg, + %a, + %imm.splat) + ret %out +} + +declare @llvm.aarch64.sve.and.u.nxv16i8(, , ) +declare @llvm.aarch64.sve.and.u.nxv8i16(, , ) +declare @llvm.aarch64.sve.and.u.nxv4i32(, , ) +declare @llvm.aarch64.sve.and.u.nxv2i64(, , ) + +declare @llvm.aarch64.sve.eor.u.nxv16i8(, , ) +declare @llvm.aarch64.sve.eor.u.nxv8i16(, , ) +declare @llvm.aarch64.sve.eor.u.nxv4i32(, , ) +declare @llvm.aarch64.sve.eor.u.nxv2i64(, , ) + +declare @llvm.aarch64.sve.orr.u.nxv16i8(, , ) +declare @llvm.aarch64.sve.orr.u.nxv8i16(, , ) +declare @llvm.aarch64.sve.orr.u.nxv4i32(, , ) +declare @llvm.aarch64.sve.orr.u.nxv2i64(, , ) + +declare @llvm.aarch64.sve.bic.u.nxv16i8(, , ) +declare @llvm.aarch64.sve.bic.u.nxv8i16(, , ) +declare @llvm.aarch64.sve.bic.u.nxv4i32(, , ) +declare @llvm.aarch64.sve.bic.u.nxv2i64(, , )