diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -19,15 +19,21 @@ // The format of this database matches clang/Basic/Builtins.def except for the // MMA builtins that are using their own format documented below. -#if defined(BUILTIN) && !defined(CUSTOM_BUILTIN) -# define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE) \ - BUILTIN(__builtin_##ID, "i.", "t") -#elif defined(CUSTOM_BUILTIN) && !defined(BUILTIN) -# define BUILTIN(ID, TYPES, ATTRS) +#ifndef BUILTIN +#define BUILTIN(ID, TYPE, ATTRS) #endif -#define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \ - CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE) +#if defined(BUILTIN) && !defined(TARGET_BUILTIN) +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) +#endif + +#ifndef CUSTOM_BUILTIN +#define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE, FEATURE) \ + TARGET_BUILTIN(__builtin_##ID, "i.", "t", FEATURE) +#endif + +#define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE, FEATURE) \ + CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE, FEATURE) // XL Compatibility built-ins BUILTIN(__builtin_ppc_popcntb, "ULiULi", "") @@ -46,7 +52,7 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "") BUILTIN(__builtin_ppc_dcbtst, "vv*", "") BUILTIN(__builtin_ppc_dcbz, "vv*", "") -BUILTIN(__builtin_ppc_icbt, "vv*", "") +TARGET_BUILTIN(__builtin_ppc_icbt, "vv*", "", "isa-v207-instructions") BUILTIN(__builtin_ppc_fric, "dd", "") BUILTIN(__builtin_ppc_frim, "dd", "") BUILTIN(__builtin_ppc_frims, "ff", "") @@ -74,12 +80,12 @@ BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "") BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "") BUILTIN(__builtin_ppc_lwarx, "iiD*", "") -BUILTIN(__builtin_ppc_lharx, "ssD*", "") -BUILTIN(__builtin_ppc_lbarx, "ccD*", "") +TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*", "", "isa-v207-instructions") +TARGET_BUILTIN(__builtin_ppc_lbarx, "ccD*", "", "isa-v207-instructions") BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "") BUILTIN(__builtin_ppc_stwcx, "iiD*i", "") -BUILTIN(__builtin_ppc_sthcx, "isD*s", "") -BUILTIN(__builtin_ppc_stbcx, "icD*i", "") +TARGET_BUILTIN(__builtin_ppc_sthcx, "isD*s", "", "isa-v207-instructions") +TARGET_BUILTIN(__builtin_ppc_stbcx, "icD*i", "", "isa-v207-instructions") BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "") BUILTIN(__builtin_ppc_tw, "viiIUi", "") BUILTIN(__builtin_ppc_trap, "vi", "") @@ -96,26 +102,27 @@ BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "") BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc") BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc") -BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "") -BUILTIN(__builtin_ppc_compare_exp_lt, "idd", "") -BUILTIN(__builtin_ppc_compare_exp_gt, "idd", "") -BUILTIN(__builtin_ppc_compare_exp_eq, "idd", "") -BUILTIN(__builtin_ppc_test_data_class, "idIi", "t") +TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", "isa-v30-instructions,vsx") +TARGET_BUILTIN(__builtin_ppc_compare_exp_lt, "idd", "", "isa-v30-instructions,vsx") +TARGET_BUILTIN(__builtin_ppc_compare_exp_gt, "idd", "", "isa-v30-instructions,vsx") +TARGET_BUILTIN(__builtin_ppc_compare_exp_eq, "idd", "", "isa-v30-instructions,vsx") +TARGET_BUILTIN(__builtin_ppc_test_data_class, "idIi", "t", "isa-v30-instructions,vsx") BUILTIN(__builtin_ppc_swdiv, "ddd", "") BUILTIN(__builtin_ppc_swdivs, "fff", "") // Compare -BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "") -BUILTIN(__builtin_ppc_cmprb, "iCIiii", "") -BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "") +TARGET_BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "", "isa-v30-instructions") +TARGET_BUILTIN(__builtin_ppc_cmprb, "iCIiii", "", "isa-v30-instructions") +TARGET_BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "", "isa-v30-instructions") BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "") // Multiply BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "") BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "") BUILTIN(__builtin_ppc_mulhw, "iii", "") BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "") -BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "") -BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "") -BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "") +TARGET_BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "", "isa-v30-instructions") +TARGET_BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "", + "isa-v30-instructions") +TARGET_BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "", "isa-v30-instructions") // Rotate BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "") BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "") @@ -123,18 +130,18 @@ // load BUILTIN(__builtin_ppc_load2r, "UsUs*", "") BUILTIN(__builtin_ppc_load4r, "UiUi*", "") -BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "") +TARGET_BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "", "isa-v206-instructions") // store BUILTIN(__builtin_ppc_store2r, "vUiUs*", "") BUILTIN(__builtin_ppc_store4r, "vUiUi*", "") -BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "") -BUILTIN(__builtin_ppc_extract_exp, "Uid", "") -BUILTIN(__builtin_ppc_extract_sig, "ULLid", "") +TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "", "isa-v206-instructions") +TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector") BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "") BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "") BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "") BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "") -BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "") +TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector") BUILTIN(__builtin_ppc_fmsub, "dddd", "") BUILTIN(__builtin_ppc_fmsubs, "ffff", "") BUILTIN(__builtin_ppc_fnmadd, "dddd", "") @@ -145,13 +152,13 @@ BUILTIN(__builtin_ppc_fres, "ff", "") BUILTIN(__builtin_ppc_dcbtstt, "vv*", "") BUILTIN(__builtin_ppc_dcbtt, "vv*", "") -BUILTIN(__builtin_ppc_mftbu, "Ui","") +BUILTIN(__builtin_ppc_mftbu, "Ui", "") BUILTIN(__builtin_ppc_mfmsr, "Ui", "") BUILTIN(__builtin_ppc_mfspr, "ULiIi", "") BUILTIN(__builtin_ppc_mtmsr, "vUi", "") BUILTIN(__builtin_ppc_mtspr, "vIiULi", "") BUILTIN(__builtin_ppc_stfiw, "viC*d", "") -BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "") +TARGET_BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "", "isa-v30-instructions") // select BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd.", "t") BUILTIN(__builtin_ppc_maxfl, "dddd.", "t") @@ -166,595 +173,696 @@ BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n") // This is just a placeholder, the types and attributes are wrong. -BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "") - -BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","") -BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi","") -BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","") -BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc","") -BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc","") -BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc","") -BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc","") - -BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","") -BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi","") -BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","") -BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc","") -BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc","") -BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc","") -BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc","") - -BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "") - -BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "") - -BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi", "") -BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi", "") -BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "") -BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "") - -BUILTIN(__builtin_altivec_dss, "vUIi", "") -BUILTIN(__builtin_altivec_dssall, "v", "") -BUILTIN(__builtin_altivec_dst, "vvC*iUIi", "") -BUILTIN(__builtin_altivec_dstt, "vvC*iUIi", "") -BUILTIN(__builtin_altivec_dstst, "vvC*iUIi", "") -BUILTIN(__builtin_altivec_dststt, "vvC*iUIi", "") - -BUILTIN(__builtin_altivec_vexptefp, "V4fV4f", "") - -BUILTIN(__builtin_altivec_vrfim, "V4fV4f", "") - -BUILTIN(__builtin_altivec_lvx, "V4iLivC*", "") -BUILTIN(__builtin_altivec_lvxl, "V4iLivC*", "") -BUILTIN(__builtin_altivec_lvebx, "V16cLivC*", "") -BUILTIN(__builtin_altivec_lvehx, "V8sLivC*", "") -BUILTIN(__builtin_altivec_lvewx, "V4iLivC*", "") - -BUILTIN(__builtin_altivec_vlogefp, "V4fV4f", "") - -BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*", "") -BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*", "") - -BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "") -BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "") -BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "") - -BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "") -BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "") -BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "") -BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "") -BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "") -BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "") - -BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "") -BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "") -BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "") -BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "") -BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "") - -BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "") - -BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us", "") -BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si", "") -BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si", "") -BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi", "") -BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi", "") -BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi", "") - -BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc", "") - -BUILTIN(__builtin_altivec_stvx, "vV4iLiv*", "") -BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*", "") -BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*", "") -BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*", "") -BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*", "") - -BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f", "") - -BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f", "") - -BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c", "") -BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s", "") -BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i", "") -BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "") - -BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "") -BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "") -BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "") - -BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "") -BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "") -BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "") - -BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us", "") -BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si", "") -BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "") +TARGET_BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc", "", + "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc", "", + "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_dss, "vUIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_dssall, "v", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_dst, "vvC*iUIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_dstt, "vvC*iUIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_dstst, "vvC*iUIi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_dststt, "vvC*iUIi", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vexptefp, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrfim, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_lvx, "V4iLivC*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_lvxl, "V4iLivC*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_lvebx, "V16cLivC*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_lvehx, "V8sLivC*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_lvewx, "V4iLivC*", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vlogefp, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "", + "power10-vector") + +TARGET_BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi", "", + "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_stvx, "vV4iLiv*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "", "power9-vector") + +TARGET_BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "", "power9-vector") + +TARGET_BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "", "altivec") // P10 Vector compare builtins. -BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "") -BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "") -BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "") -BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "") -BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "") -BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "") - -BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f", "") - -BUILTIN(__builtin_altivec_mfvscr, "V8Us", "") - -BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f", "") - -BUILTIN(__builtin_altivec_mtvscr, "vV4i", "") - -BUILTIN(__builtin_altivec_vrefp, "V4fV4f", "") - -BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc", "") -BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us", "") -BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui", "") -BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi", "") - -BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui", "") - -BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "") -BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "") - -BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "") -BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "") -BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "") - -BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "") -BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "") - -BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "") +TARGET_BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "", + "power10-vector") + +TARGET_BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_mfvscr, "V8Us", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_mtvscr, "vV4i", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrefp, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi", "", "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vrfiz, "V4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i", "", "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vupklsb, "V8sV16c", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vupklsh, "V4iV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i", "", "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "", "vsx") +TARGET_BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "", "altivec") + +TARGET_BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "vsx") + +TARGET_BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "", "altivec") +TARGET_BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "", "vsx") +TARGET_BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "", "vsx") +TARGET_BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "", "altivec") -BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f", "") - -BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui", "") - -BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si", "") -BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui", "") -BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si", "") - -BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si", "") - -BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si", "") - -BUILTIN(__builtin_altivec_vrfiz, "V4fV4f", "") - -BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c", "") -BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s", "") -BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s", "") -BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i", "") - -BUILTIN(__builtin_altivec_vupklsb, "V8sV16c", "") -BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s", "") -BUILTIN(__builtin_altivec_vupklsh, "V4iV8s", "") -BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i", "") - -BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f", "") - -BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f", "") - -BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c", "") -BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s", "") -BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i", "") -BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "") - -BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "") -BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "") -BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "") -BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "") - -BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "") -BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "") -BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us", "") -BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "") - -BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "") +TARGET_BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "", + "power9-vector") // P8 Crypto built-ins. -BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "") -BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "") -BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi", "") - -BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "") -BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "") -BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "") -BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "") -BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui", "", + "power8-vector") +TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi", "", + "power8-vector") + +TARGET_BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector") // P8 BCD builtins. -BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "") -BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi", "") -BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "") -BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "") - -BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "") -BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "") -BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "") -BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi", "") +TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "", + "isa-v207-instructions") +TARGET_BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi", "", + "isa-v207-instructions") +TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "", + "isa-v207-instructions") +TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "", + "isa-v207-instructions") + +TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi", "", "power9-vector") // Vector population count built-ins -BUILTIN(__builtin_altivec_vpopcntb, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vpopcnth, "V8UsV8Us", "") -BUILTIN(__builtin_altivec_vpopcntw, "V4UiV4Ui", "") -BUILTIN(__builtin_altivec_vpopcntd, "V2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_vpopcntb, "V16UcV16Uc", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vpopcnth, "V8UsV8Us", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vpopcntw, "V4UiV4Ui", "", "power8-vector") +TARGET_BUILTIN(__builtin_altivec_vpopcntd, "V2ULLiV2ULLi", "", "power8-vector") // Absolute difference built-ins -BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "") -BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "") +TARGET_BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc", "", + "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "power9-vector") // P9 Shift built-ins. -BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc", "") -BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "") +TARGET_BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "", "power9-vector") // P9 Vector rotate built-ins -BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "", + "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "", + "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "", + "power9-vector") // P9 Vector extend sign builtins. -BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "") -BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "") -BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "") -BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "") -BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "") +TARGET_BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "", "power9-vector") +TARGET_BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "", "power9-vector") // P10 Vector extend sign builtins. -BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "") +TARGET_BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "", + "power10-vector") // P10 Vector Extract with Mask built-ins. -BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "") -BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "") -BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "") -BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "") -BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "") +TARGET_BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "", "power10-vector") // P10 Vector Divide Extended built-ins. -BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "") -BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "") +TARGET_BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "", + "power10-vector") // P10 Vector Multiply High built-ins. -BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "") -BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "") -BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "") -BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") // P10 Vector Expand with Mask built-ins. -BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "") -BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "") -BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "") +TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "", + "power10-vector") // P10 Vector Count with Mask built-ins. -BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "") -BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "") -BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "") -BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "") +TARGET_BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "", "power10-vector") // P10 Move to VSR with Mask built-ins. -BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "") -BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "") -BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "") -BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "") -BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "") +TARGET_BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "", "power10-vector") // P10 Vector Parallel Bits built-ins. -BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") // P10 Vector String Isolate Built-ins. -BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "") -BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "") -BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "") -BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "") -BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "") -BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "") -BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "") +TARGET_BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "", "power10-vector") // P10 Vector Centrifuge built-in. -BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") // P10 Vector Gather Every N-th Bit built-in. -BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "") +TARGET_BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "", "power10-vector") // P10 Vector Clear Bytes built-ins. -BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "") -BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "") +TARGET_BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "", "power10-vector") // P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins. -BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "") -BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "", + "power10-vector") // P10 Vector Shift built-ins. -BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "") -BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "") +TARGET_BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "", + "power10-vector") // P10 Vector Insert built-ins. -BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "") -BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "") -BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "") -BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "") -BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "") -BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "") -BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "") -BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "") -BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "") -BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "") -BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "") -BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "") -BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "") -BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "") -BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "") -BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "") -BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "") -BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "") +TARGET_BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "", + "power10-vector") // P10 Vector Extract built-ins. -BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "") -BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "") -BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "") -BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "") -BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "") -BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "") -BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "") -BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "") +TARGET_BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "", + "power10-vector") // P10 Vector rotate built-ins. -BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "") -BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "") +TARGET_BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", + "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "", + "power10-vector") // VSX built-ins. -BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*", "") -BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*", "") -BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "") -BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "") +TARGET_BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "", "vsx") -BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*", "") -BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*", "") -BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "") -BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "") +TARGET_BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "", "vsx") -BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi", "") -BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi", "") -BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi", "") -BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi", "") -BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii", "") -BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc", "") +TARGET_BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii", "", "isa-v207-instructions") +TARGET_BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc", "", "isa-v207-instructions") -BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "") -BUILTIN(__builtin_vsx_xsmaxdp, "ddd", "") +TARGET_BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xsmaxdp, "ddd", "", "vsx") -BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f", "") -BUILTIN(__builtin_vsx_xsmindp, "ddd", "") +TARGET_BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xsmindp, "ddd", "", "vsx") -BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvrspip, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvrspip, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d", "") -BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d", "") -BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d", "") -BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d", "") -BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d", "") -BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d", "") -BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvrspim, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvrspim, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvrspi, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvrspi, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvrspic, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvrspic, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvredp, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvresp, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvredp, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvresp, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d", "") -BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui", "") +TARGET_BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui", "", "power8-vector") -BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d", "") -BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "", "vsx") -BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "") -BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "") +TARGET_BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "", "vsx") -BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "") -BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "") -BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "") -BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "") +TARGET_BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "", "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "", "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "", "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "", "power10-vector") // vector Insert/Extract exponent/significand builtins -BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "") -BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "") -BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d", "") -BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f", "") -BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d", "") -BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f", "") +TARGET_BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f", "", "power9-vector") // Conversion builtins -BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "") -BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "") -BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f", "") -BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f", "") -BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "") -BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "") -BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "") -BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "") -BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "") -BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "") - -BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "") -BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "") - -BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "") -BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "") +TARGET_BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "", "vsx") + +TARGET_BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "", "power9-vector") + +TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "", "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "", "power10-vector") // Vector Test Data Class builtins -BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "") -BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "") +TARGET_BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "", "power9-vector") +TARGET_BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "", "power9-vector") -BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "") -BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "") +TARGET_BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "", "vsx") -BUILTIN(__builtin_vsx_xxpermdi, "v.", "t") -BUILTIN(__builtin_vsx_xxsldwi, "v.", "t") +TARGET_BUILTIN(__builtin_vsx_xxpermdi, "v.", "t", "vsx") +TARGET_BUILTIN(__builtin_vsx_xxsldwi, "v.", "t", "vsx") -BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "") +TARGET_BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "", + "power10-vector") -BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "") +TARGET_BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "", "power10-vector") -BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d", "") -BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f", "") -BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d", "") -BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f", "") +TARGET_BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d", "", "vsx") +TARGET_BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f", "", "vsx") // P10 Vector Permute Extended built-in. -BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "") +TARGET_BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "", + "power10-vector") // P10 Vector Blend built-ins. -BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "") -BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "") -BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "") -BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "") +TARGET_BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "", + "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "", + "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "", + "power10-vector") +TARGET_BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "", + "power10-vector") // Float 128 built-ins -BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "") -BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "") -BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "") -BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "") -BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "") -BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "") -BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "") -BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "") -BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "") +TARGET_BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "", "float128") +TARGET_BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "", "float128") +TARGET_BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "", "float128") +TARGET_BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "", "float128") +TARGET_BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "", "float128") +TARGET_BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "", "float128") +TARGET_BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "", "float128") +TARGET_BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "", "float128") +TARGET_BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "", "float128") // Fastmath by default builtins BUILTIN(__builtin_ppc_rsqrtf, "V4fV4f", "") @@ -763,60 +871,60 @@ BUILTIN(__builtin_ppc_recipdivd, "V2dV2dV2d", "") // HTM builtins -BUILTIN(__builtin_tbegin, "UiUIi", "") -BUILTIN(__builtin_tend, "UiUIi", "") +TARGET_BUILTIN(__builtin_tbegin, "UiUIi", "", "htm") +TARGET_BUILTIN(__builtin_tend, "UiUIi", "", "htm") -BUILTIN(__builtin_tabort, "UiUi", "") -BUILTIN(__builtin_tabortdc, "UiUiUiUi", "") -BUILTIN(__builtin_tabortdci, "UiUiUii", "") -BUILTIN(__builtin_tabortwc, "UiUiUiUi", "") -BUILTIN(__builtin_tabortwci, "UiUiUii", "") +TARGET_BUILTIN(__builtin_tabort, "UiUi", "", "htm") +TARGET_BUILTIN(__builtin_tabortdc, "UiUiUiUi", "", "htm") +TARGET_BUILTIN(__builtin_tabortdci, "UiUiUii", "", "htm") +TARGET_BUILTIN(__builtin_tabortwc, "UiUiUiUi", "", "htm") +TARGET_BUILTIN(__builtin_tabortwci, "UiUiUii", "", "htm") -BUILTIN(__builtin_tcheck, "Ui", "") -BUILTIN(__builtin_treclaim, "UiUi", "") -BUILTIN(__builtin_trechkpt, "Ui", "") -BUILTIN(__builtin_tsr, "UiUi", "") +TARGET_BUILTIN(__builtin_tcheck, "Ui", "", "htm") +TARGET_BUILTIN(__builtin_treclaim, "UiUi", "", "htm") +TARGET_BUILTIN(__builtin_trechkpt, "Ui", "", "htm") +TARGET_BUILTIN(__builtin_tsr, "UiUi", "", "htm") -BUILTIN(__builtin_tendall, "Ui", "") -BUILTIN(__builtin_tresume, "Ui", "") -BUILTIN(__builtin_tsuspend, "Ui", "") +TARGET_BUILTIN(__builtin_tendall, "Ui", "", "htm") +TARGET_BUILTIN(__builtin_tresume, "Ui", "", "htm") +TARGET_BUILTIN(__builtin_tsuspend, "Ui", "", "htm") -BUILTIN(__builtin_get_texasr, "LUi", "c") -BUILTIN(__builtin_get_texasru, "LUi", "c") -BUILTIN(__builtin_get_tfhar, "LUi", "c") -BUILTIN(__builtin_get_tfiar, "LUi", "c") +TARGET_BUILTIN(__builtin_get_texasr, "LUi", "c", "htm") +TARGET_BUILTIN(__builtin_get_texasru, "LUi", "c", "htm") +TARGET_BUILTIN(__builtin_get_tfhar, "LUi", "c", "htm") +TARGET_BUILTIN(__builtin_get_tfiar, "LUi", "c", "htm") -BUILTIN(__builtin_set_texasr, "vLUi", "c") -BUILTIN(__builtin_set_texasru, "vLUi", "c") -BUILTIN(__builtin_set_tfhar, "vLUi", "c") -BUILTIN(__builtin_set_tfiar, "vLUi", "c") +TARGET_BUILTIN(__builtin_set_texasr, "vLUi", "c", "htm") +TARGET_BUILTIN(__builtin_set_texasru, "vLUi", "c", "htm") +TARGET_BUILTIN(__builtin_set_tfhar, "vLUi", "c", "htm") +TARGET_BUILTIN(__builtin_set_tfiar, "vLUi", "c", "htm") -BUILTIN(__builtin_ttest, "LUi", "") +TARGET_BUILTIN(__builtin_ttest, "LUi", "", "htm") // Scalar built-ins -BUILTIN(__builtin_divwe, "SiSiSi", "") -BUILTIN(__builtin_divweu, "UiUiUi", "") -BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "") -BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "") -BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "") -BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "") -BUILTIN(__builtin_pextd, "ULLiULLiULLi", "") -BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "") -BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "") -BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "") +TARGET_BUILTIN(__builtin_divwe, "SiSiSi", "", "extdiv") +TARGET_BUILTIN(__builtin_divweu, "UiUiUi", "", "extdiv") +TARGET_BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "", "extdiv") +TARGET_BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "", "extdiv") +TARGET_BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "", "bpermd") +TARGET_BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "", "isa-v31-instructions") +TARGET_BUILTIN(__builtin_pextd, "ULLiULLiULLi", "", "isa-v31-instructions") +TARGET_BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "", "isa-v31-instructions") +TARGET_BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "", "isa-v31-instructions") +TARGET_BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "", "isa-v31-instructions") // Double-double (un)pack BUILTIN(__builtin_unpack_longdouble, "dLdIi", "") BUILTIN(__builtin_pack_longdouble, "Lddd", "") // Generate random number -BUILTIN(__builtin_darn, "LLi", "") -BUILTIN(__builtin_darn_raw, "LLi", "") -BUILTIN(__builtin_darn_32, "i", "") +TARGET_BUILTIN(__builtin_darn, "LLi", "", "isa-v30-instructions") +TARGET_BUILTIN(__builtin_darn_raw, "LLi", "", "isa-v30-instructions") +TARGET_BUILTIN(__builtin_darn_32, "i", "", "isa-v30-instructions") // Vector int128 (un)pack -BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "") -BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "") +TARGET_BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "", "vsx") +TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx") // Set the floating point rounding mode BUILTIN(__builtin_setrnd, "di", "") @@ -850,86 +958,159 @@ // its given accumulator. // Provided builtins with _mma_ prefix for compatibility. -CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*", false) -CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*", false) -CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false) -CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false) -CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV", false) -CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV", false) +CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*", false, + "paired-vector-memops") +CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*", false, + "paired-vector-memops") +CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false, + "paired-vector-memops") +CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false, + "paired-vector-memops") +CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV", false, + "paired-vector-memops") +CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV", false, "mma") // UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have // the same name as that of the intrinsic they generate, i.e. the // ID and INTR are the same. // This avoids repeating the ID and INTR in the macro expression. -UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*", false) -UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*", false) -UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false) -UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false) - -UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false) -UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false) -UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true) -UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true) -UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvf32ger, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvf64ger, "vW512*W256V", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pn, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2np, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2nn, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pp, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pn, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2np, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2nn, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpn, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernn, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpp, "vW512*VVi15i15", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpn, "vW512*VVi15i15", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernp, "vW512*VVi15i15", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernn, "vW512*VVi15i15", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpp, "vW512*W256V", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpn, "vW512*W256V", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernp, "vW512*W256V", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernn, "vW512*W256V", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpp, "vW512*W256Vi15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpn, "vW512*W256Vi15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernp, "vW512*W256Vi15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernn, "vW512*W256Vi15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2, "vW512*VV", false) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3", false) -UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pp, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pn, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2np, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2nn, "vW512*VV", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pp, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pn, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3", true) -UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true) +UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*", false, + "paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*", false, + "paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false, + "paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false, + "paired-vector-memops") + +// TODO: Require only mma after backend supports these without paired memops +UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf32ger, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf64ger, "vW512*W256V", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pn, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2np, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2nn, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pp, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pn, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2np, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2nn, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpn, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernn, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpp, "vW512*VVi15i15", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpn, "vW512*VVi15i15", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernp, "vW512*VVi15i15", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernn, "vW512*VVi15i15", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpp, "vW512*W256V", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpn, "vW512*W256V", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernp, "vW512*W256V", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernn, "vW512*W256V", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpp, "vW512*W256Vi15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpn, "vW512*W256Vi15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernp, "vW512*W256Vi15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernn, "vW512*W256Vi15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2, "vW512*VV", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3", false, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pp, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pn, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2np, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2nn, "vW512*VV", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pp, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pn, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") +UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true, + "mma,paired-vector-memops") // FIXME: Obviously incomplete. diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -10048,12 +10048,6 @@ "this builtin requires 'dsp r2' ASE, please use -mdspr2">; def err_mips_builtin_requires_msa : Error< "this builtin requires 'msa' ASE, please use -mmsa">; -def err_ppc_builtin_only_on_arch : Error< - "this builtin is only valid on POWER%0 or later CPUs">; -def err_ppc_builtin_requires_vsx : Error< - "this builtin requires VSX to be enabled">; -def err_ppc_builtin_requires_htm : Error< - "this builtin requires HTM to be enabled">; def err_ppc_builtin_requires_abi : Error< "this builtin requires ABI -mabi=%0">; def err_ppc_invalid_use_mma_type : Error< diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -21,6 +21,8 @@ static constexpr Builtin::Info BuiltinInfo[] = { #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::HEADER, ALL_LANGUAGES}, #include "clang/Basic/BuiltinsPPC.def" diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -16548,7 +16548,7 @@ // use custom code generation to expand a builtin call with a pointer to a // load (if the corresponding instruction accumulates its result) followed by // the call to the intrinsic and a store of the result. -#define CUSTOM_BUILTIN(Name, Intr, Types, Accumulate) \ +#define CUSTOM_BUILTIN(Name, Intr, Types, Accumulate, Feature) \ case PPC::BI__builtin_##Name: #include "clang/Basic/BuiltinsPPC.def" { @@ -16598,7 +16598,7 @@ } bool Accumulate; switch (BuiltinID) { - #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \ + #define CUSTOM_BUILTIN(Name, Intr, Types, Acc, Feature) \ case PPC::BI__builtin_##Name: \ ID = Intrinsic::ppc_##Intr; \ Accumulate = Acc; \ diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4172,21 +4172,6 @@ return false; } -static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall, - StringRef FeatureToCheck, unsigned DiagID, - StringRef DiagArg = "") { - if (S.Context.getTargetInfo().hasFeature(FeatureToCheck)) - return false; - - if (DiagArg.empty()) - S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange(); - else - S.Diag(TheCall->getBeginLoc(), DiagID) - << DiagArg << TheCall->getSourceRange(); - - return true; -} - /// Returns true if the argument consists of one contiguous run of 1s with any /// number of 0s on either side. The 1s are allowed to wrap from LSB to MSB, so /// 0x000FFF0, 0x0000FFFF, 0xFF0000FF, 0x0 are all runs. 0x0F0F0000 is not, @@ -4231,42 +4216,16 @@ return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3); case PPC::BI__builtin_tbegin: case PPC::BI__builtin_tend: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1) || - SemaFeatureCheck(*this, TheCall, "htm", - diag::err_ppc_builtin_requires_htm); + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); case PPC::BI__builtin_tsr: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) || - SemaFeatureCheck(*this, TheCall, "htm", - diag::err_ppc_builtin_requires_htm); + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7); case PPC::BI__builtin_tabortwc: case PPC::BI__builtin_tabortdc: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) || - SemaFeatureCheck(*this, TheCall, "htm", - diag::err_ppc_builtin_requires_htm); + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31); case PPC::BI__builtin_tabortwci: case PPC::BI__builtin_tabortdci: - return SemaFeatureCheck(*this, TheCall, "htm", - diag::err_ppc_builtin_requires_htm) || - (SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31)); - case PPC::BI__builtin_tabort: - case PPC::BI__builtin_tcheck: - case PPC::BI__builtin_treclaim: - case PPC::BI__builtin_trechkpt: - case PPC::BI__builtin_tendall: - case PPC::BI__builtin_tresume: - case PPC::BI__builtin_tsuspend: - case PPC::BI__builtin_get_texasr: - case PPC::BI__builtin_get_texasru: - case PPC::BI__builtin_get_tfhar: - case PPC::BI__builtin_get_tfiar: - case PPC::BI__builtin_set_texasr: - case PPC::BI__builtin_set_texasru: - case PPC::BI__builtin_set_tfhar: - case PPC::BI__builtin_set_tfiar: - case PPC::BI__builtin_ttest: - return SemaFeatureCheck(*this, TheCall, "htm", - diag::err_ppc_builtin_requires_htm); + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) || + SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); // According to GCC 'Basic PowerPC Built-in Functions Available on ISA 2.05', // __builtin_(un)pack_longdouble are available only if long double uses IBM // extended double representation. @@ -4287,26 +4246,8 @@ case PPC::BI__builtin_vsx_xxpermdi: case PPC::BI__builtin_vsx_xxsldwi: return SemaBuiltinVSX(TheCall); - case PPC::BI__builtin_divwe: - case PPC::BI__builtin_divweu: - case PPC::BI__builtin_divde: - case PPC::BI__builtin_divdeu: - return SemaFeatureCheck(*this, TheCall, "extdiv", - diag::err_ppc_builtin_only_on_arch, "7"); - case PPC::BI__builtin_bpermd: - return SemaFeatureCheck(*this, TheCall, "bpermd", - diag::err_ppc_builtin_only_on_arch, "7"); case PPC::BI__builtin_unpack_vector_int128: - return SemaFeatureCheck(*this, TheCall, "vsx", - diag::err_ppc_builtin_only_on_arch, "7") || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); - case PPC::BI__builtin_pack_vector_int128: - return SemaFeatureCheck(*this, TheCall, "vsx", - diag::err_ppc_builtin_only_on_arch, "7"); - case PPC::BI__builtin_pdepd: - case PPC::BI__builtin_pextd: - return SemaFeatureCheck(*this, TheCall, "isa-v31-instructions", - diag::err_ppc_builtin_only_on_arch, "10"); + return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); case PPC::BI__builtin_altivec_vgnb: return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7); case PPC::BI__builtin_vsx_xxeval: @@ -4320,17 +4261,8 @@ case PPC::BI__builtin_ppc_tw: case PPC::BI__builtin_ppc_tdw: return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31); - case PPC::BI__builtin_ppc_cmpeqb: - case PPC::BI__builtin_ppc_setb: - case PPC::BI__builtin_ppc_maddhd: - case PPC::BI__builtin_ppc_maddhdu: - case PPC::BI__builtin_ppc_maddld: - return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", - diag::err_ppc_builtin_only_on_arch, "9"); case PPC::BI__builtin_ppc_cmprb: - return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", - diag::err_ppc_builtin_only_on_arch, "9") || - SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must // be a constant that represents a contiguous bit field. case PPC::BI__builtin_ppc_rlwnm: @@ -4339,15 +4271,8 @@ case PPC::BI__builtin_ppc_rldimi: return SemaBuiltinConstantArg(TheCall, 2, Result) || SemaValueIsRunOfOnes(TheCall, 3); - case PPC::BI__builtin_ppc_extract_exp: - case PPC::BI__builtin_ppc_extract_sig: - case PPC::BI__builtin_ppc_insert_exp: - return SemaFeatureCheck(*this, TheCall, "power9-vector", - diag::err_ppc_builtin_only_on_arch, "9"); case PPC::BI__builtin_ppc_addex: { - if (SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", - diag::err_ppc_builtin_only_on_arch, "9") || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 3)) + if (SemaBuiltinConstantArgRange(TheCall, 2, 0, 3)) return true; // Output warning for reserved values 1 to 3. int ArgValue = @@ -4369,41 +4294,19 @@ return SemaBuiltinConstantArgPower2(TheCall, 0); case PPC::BI__builtin_ppc_rdlam: return SemaValueIsRunOfOnes(TheCall, 2); - case PPC::BI__builtin_ppc_icbt: - case PPC::BI__builtin_ppc_sthcx: - case PPC::BI__builtin_ppc_stbcx: - case PPC::BI__builtin_ppc_lharx: - case PPC::BI__builtin_ppc_lbarx: - return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions", - diag::err_ppc_builtin_only_on_arch, "8"); case PPC::BI__builtin_vsx_ldrmb: case PPC::BI__builtin_vsx_strmb: - return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions", - diag::err_ppc_builtin_only_on_arch, "8") || - SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); + return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); case PPC::BI__builtin_altivec_vcntmbb: case PPC::BI__builtin_altivec_vcntmbh: case PPC::BI__builtin_altivec_vcntmbw: case PPC::BI__builtin_altivec_vcntmbd: return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); - case PPC::BI__builtin_darn: - case PPC::BI__builtin_darn_raw: - case PPC::BI__builtin_darn_32: - return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", - diag::err_ppc_builtin_only_on_arch, "9"); case PPC::BI__builtin_vsx_xxgenpcvbm: case PPC::BI__builtin_vsx_xxgenpcvhm: case PPC::BI__builtin_vsx_xxgenpcvwm: case PPC::BI__builtin_vsx_xxgenpcvdm: return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3); - case PPC::BI__builtin_ppc_compare_exp_uo: - case PPC::BI__builtin_ppc_compare_exp_lt: - case PPC::BI__builtin_ppc_compare_exp_gt: - case PPC::BI__builtin_ppc_compare_exp_eq: - return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", - diag::err_ppc_builtin_only_on_arch, "9") || - SemaFeatureCheck(*this, TheCall, "vsx", - diag::err_ppc_builtin_requires_vsx); case PPC::BI__builtin_ppc_test_data_class: { // Check if the first argument of the __builtin_ppc_test_data_class call is // valid. The argument must be 'float' or 'double' or '__float128'. @@ -4413,11 +4316,7 @@ ArgType != QualType(Context.Float128Ty)) return Diag(TheCall->getBeginLoc(), diag::err_ppc_invalid_test_data_class_type); - return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions", - diag::err_ppc_builtin_only_on_arch, "9") || - SemaFeatureCheck(*this, TheCall, "vsx", - diag::err_ppc_builtin_requires_vsx) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 127); + return SemaBuiltinConstantArgRange(TheCall, 1, 0, 127); } case PPC::BI__builtin_ppc_maxfe: case PPC::BI__builtin_ppc_minfe: @@ -4446,11 +4345,7 @@ << TheCall->getArg(I)->getType() << ArgType << 1 << 0 << 0; return false; } - case PPC::BI__builtin_ppc_load8r: - case PPC::BI__builtin_ppc_store8r: - return SemaFeatureCheck(*this, TheCall, "isa-v206-instructions", - diag::err_ppc_builtin_only_on_arch, "7"); -#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \ +#define CUSTOM_BUILTIN(Name, Intr, Types, Acc, Feature) \ case PPC::BI__builtin_##Name: \ return SemaBuiltinPPCMMACall(TheCall, BuiltinID, Types); #include "clang/Basic/BuiltinsPPC.def" @@ -8688,29 +8583,6 @@ assert((TypeStr[0] != '\0') && "Invalid types in PPC MMA builtin declaration"); - switch (BuiltinID) { - default: - // This function is called in CheckPPCBuiltinFunctionCall where the - // BuiltinID is guaranteed to be an MMA or pair vector memop builtin, here - // we are isolating the pair vector memop builtins that can be used with mma - // off so the default case is every builtin that requires mma and paired - // vector memops. - if (SemaFeatureCheck(*this, TheCall, "paired-vector-memops", - diag::err_ppc_builtin_only_on_arch, "10") || - SemaFeatureCheck(*this, TheCall, "mma", - diag::err_ppc_builtin_only_on_arch, "10")) - return true; - break; - case PPC::BI__builtin_vsx_lxvp: - case PPC::BI__builtin_vsx_stxvp: - case PPC::BI__builtin_vsx_assemble_pair: - case PPC::BI__builtin_vsx_disassemble_pair: - if (SemaFeatureCheck(*this, TheCall, "paired-vector-memops", - diag::err_ppc_builtin_only_on_arch, "10")) - return true; - break; - } - unsigned Mask = 0; unsigned ArgNum = 0; diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c b/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c @@ -9526,80 +9526,6 @@ // CHECK-LE: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 1 } -/* ----------------------------- vec_xl_be ---------------------------------- */ -void test11() { - // CHECK-LABEL: define{{.*}} void @test11 - // CHECK-LE-LABEL: define{{.*}} void @test11 - res_vsc = vec_xl_be(param_sll, param_sc_ld); - // CHECK: load <16 x i8>, ptr %{{.+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) - // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> - - res_vuc = vec_xl_be(param_sll, param_uc_ld); - // CHECK: load <16 x i8>, ptr %{{.+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) - // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> - - res_vs = vec_xl_be(param_sll, param_s_ld); - // CHECK: load <8 x i16>, ptr %{{.+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) - // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> - - res_vus = vec_xl_be(param_sll, param_us_ld); - // CHECK: load <8 x i16>, ptr %{{.+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) - // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> - - res_vi = vec_xl_be(param_sll, param_i_ld); - // CHECK: load <4 x i32>, ptr %{{.+}}, align 1 - // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) - - res_vui = vec_xl_be(param_sll, param_ui_ld); - // CHECK: load <4 x i32>, ptr %{{.+}}, align 1 - // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) - - res_vf = vec_xl_be(param_sll, param_f_ld); - // CHECK: load <4 x float>, ptr %{{.+}}, align 1 - // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) -} - -/* ----------------------------- vec_xst_be --------------------------------- */ -void test12() { - // CHECK-LABEL: define{{.*}} void @test12 - // CHECK-LE-LABEL: define{{.*}} void @test12 - vec_xst_be(vsc, param_sll, ¶m_sc); - // CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) - - vec_xst_be(vuc, param_sll, ¶m_uc); - // CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) - - vec_xst_be(vs, param_sll, ¶m_s); - // CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) - - vec_xst_be(vus, param_sll, ¶m_us); - // CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) - - vec_xst_be(vi, param_sll, ¶m_i); - // CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) - - vec_xst_be(vui, param_sll, ¶m_ui); - // CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) - - vec_xst_be(vf, param_sll, ¶m_f); - // CHECK: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 1 - // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) -} - vector float test_rsqrtf(vector float a, vector float b) { // CHECK-LABEL: test_rsqrtf // CHECK: call fast <4 x float> @llvm.sqrt.v4f32 diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-fma.c b/clang/test/CodeGen/PowerPC/builtins-ppc-fma.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-fma.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-fma.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple powerpc64le-gnu-linux \ -// RUN: -target-feature +altivec -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck \ +// RUN: -target-feature +vsx -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck \ // RUN: %s typedef __attribute__((vector_size(4 * sizeof(float)))) float vec_float; diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c b/clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c @@ -12,7 +12,7 @@ // RUN: -o - %s | FileCheck --check-prefix=CHECK-ASM \ // RUN: --check-prefix=FIXME-CHECK %s // RUN: %clang_cc1 -triple powerpcspe -S -ffp-exception-behavior=strict \ -// RUN: -target-feature +spe -fexperimental-strict-floating-point -emit-llvm \ +// RUN: -target-feature +vsx -fexperimental-strict-floating-point -emit-llvm \ // RUN: %s -o - | FileCheck --check-prefix=CHECK-CONSTRAINED %s typedef __attribute__((vector_size(4 * sizeof(float)))) float vec_float; diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-htm.c b/clang/test/CodeGen/PowerPC/builtins-ppc-htm.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-htm.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-htm.c @@ -7,82 +7,82 @@ r[0] = __builtin_tbegin (0); // CHECK: @llvm.ppc.tbegin -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tbegin' needs target feature htm r[1] = __builtin_tbegin (1); // CHECK: @llvm.ppc.tbegin -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tbegin' needs target feature htm r[2] = __builtin_tend (0); // CHECK: @llvm.ppc.tend -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tend' needs target feature htm r[3] = __builtin_tendall (); // CHECK: @llvm.ppc.tendall -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tendall' needs target feature htm r[4] = __builtin_tabort (code); // CHECK: @llvm.ppc.tabort -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tabort' needs target feature htm r[5] = __builtin_tabort (0x1); // CHECK: @llvm.ppc.tabort -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tabort' needs target feature htm r[6] = __builtin_tabortdc (0xf, a[0], b[0]); // CHECK: @llvm.ppc.tabortdc -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tabortdc' needs target feature htm r[7] = __builtin_tabortdci (0xf, a[1], 0x1); // CHECK: @llvm.ppc.tabortdc -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tabortdci' needs target feature htm r[8] = __builtin_tabortwc (0xf, a[2], b[2]); // CHECK: @llvm.ppc.tabortwc -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tabortwc' needs target feature htm r[9] = __builtin_tabortwci (0xf, a[3], 0x1); // CHECK: @llvm.ppc.tabortwc -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tabortwci' needs target feature htm r[10] = __builtin_tcheck (); // CHECK: @llvm.ppc.tcheck -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tcheck' needs target feature htm r[11] = __builtin_trechkpt (); // CHECK: @llvm.ppc.trechkpt -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_trechkpt' needs target feature htm r[12] = __builtin_treclaim (0); // CHECK: @llvm.ppc.treclaim -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_treclaim' needs target feature htm r[13] = __builtin_tresume (); // CHECK: @llvm.ppc.tresume -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tresume' needs target feature htm r[14] = __builtin_tsuspend (); // CHECK: @llvm.ppc.tsuspend -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tsuspend' needs target feature htm r[15] = __builtin_tsr (0); // CHECK: @llvm.ppc.tsr -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_tsr' needs target feature htm r[16] = __builtin_ttest (); // CHECK: @llvm.ppc.ttest -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_ttest' needs target feature htm r[17] = __builtin_get_texasr (); // CHECK: @llvm.ppc.get.texasr -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_get_texasr' needs target feature htm r[18] = __builtin_get_texasru (); // CHECK: @llvm.ppc.get.texasru -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_get_texasru' needs target feature htm r[19] = __builtin_get_tfhar (); // CHECK: @llvm.ppc.get.tfhar -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_get_tfhar' needs target feature htm r[20] = __builtin_get_tfiar (); // CHECK: @llvm.ppc.get.tfiar -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_get_tfiar' needs target feature htm __builtin_set_texasr (a[21]); // CHECK: @llvm.ppc.set.texasr -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_set_texasr' needs target feature htm __builtin_set_texasru (a[22]); // CHECK: @llvm.ppc.set.texasru -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_set_texasru' needs target feature htm __builtin_set_tfhar (a[23]); // CHECK: @llvm.ppc.set.tfhar -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_set_tfhar' needs target feature htm __builtin_set_tfiar (a[24]); // CHECK: @llvm.ppc.set.tfiar -// ERROR: error: this builtin requires HTM to be enabled +// ERROR: error: '__builtin_set_tfiar' needs target feature htm } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p7-disabled.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p7-disabled.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p7-disabled.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p7-disabled.c @@ -6,6 +6,7 @@ // RUN: not %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - 2>&1 \ // RUN: -target-cpu pwr7 | FileCheck %s -check-prefix=CHECK-32 +// CHECK: error: use of '__int128' with '__vector' requires extended Altivec support (available on POWER8 or later) vector signed __int128 vslll = {33}; void call_p7_builtins(void) @@ -19,20 +20,6 @@ __builtin_unpack_vector_int128(vslll, 1); } -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_divwe -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_divweu -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_divde -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_divdeu -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_bpermd -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_pack_vector_int128 -// CHECK: error: this builtin is only valid on POWER7 or later CPUs -// CHECK: __builtin_unpack_vector_int128 // CHECK-32: error: this builtin is only available on 64-bit targets // CHECK-32: __builtin_divde // CHECK-32: error: this builtin is only available on 64-bit targets diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c @@ -1,6 +1,6 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +isa-v207-instructions -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +isa-v207-instructions -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC // Added -target-feature +vsx above to avoid errors about "vector double" and to // generate the correct errors for functions that are only overloaded with VSX diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c @@ -16,19 +16,15 @@ extern unsigned long long ull; -unsigned long long test_builtin_pextd() { - // CHECK-LABEL: @test_builtin_pextd( - // CHECK: %2 = call i64 @llvm.ppc.pextd(i64 %0, i64 %1) +void test_xlcompat() { + // CHECK-LABEL: @test_xlcompat( + // CHECK: %2 = call i64 @llvm.ppc.pextd(i64 %0, i64 %1) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR10-ERR: error: this builtin is only valid on POWER10 or later CPUs - return __builtin_pextd(ull, ull); -} + // CHECK-NONPWR10-ERR: error: '__builtin_pextd' needs target feature isa-v31-instructions + ull = __builtin_pextd(ull, ull); -unsigned long long test_builtin_pdepd() { - // CHECK-LABEL: @test_builtin_pdepd( - // CHECK: %2 = call i64 @llvm.ppc.pdepd(i64 %0, i64 %1) + // CHECK: %5 = call i64 @llvm.ppc.pdepd(i64 %3, i64 %4) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR10-ERR: error: this builtin is only valid on POWER10 or later CPUs - return __builtin_pdepd(ull, ull); + // CHECK-NONPWR10-ERR: error: '__builtin_pdepd' needs target feature isa-v31-instructions + ull = __builtin_pdepd(ull, ull); } - diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c @@ -1977,6 +1977,38 @@ // CHECK: load <2 x double>, ptr %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) +res_vsc = vec_xl_be(sll, asc); +// CHECK: load <16 x i8>, ptr %{{.+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) +// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> + +res_vuc = vec_xl_be(sll, auc); +// CHECK: load <16 x i8>, ptr %{{.+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) +// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> + +res_vss = vec_xl_be(sll, ass); +// CHECK: load <8 x i16>, ptr %{{.+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) +// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> + +res_vus = vec_xl_be(sll, aus); +// CHECK: load <8 x i16>, ptr %{{.+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) +// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> + +res_vsi = vec_xl_be(sll, asi); +// CHECK: load <4 x i32>, ptr %{{.+}}, align 1 +// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) + +res_vui = vec_xl_be(sll, aui); +// CHECK: load <4 x i32>, ptr %{{.+}}, align 1 +// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) + +res_vf = vec_xl_be(sll, af); +// CHECK: load <4 x float>, ptr %{{.+}}, align 1 +// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) + res_vsll = vec_xlds(sll, asll); // CHECK: load i64 // CHECK: insertelement <2 x i64> @@ -2061,6 +2093,38 @@ // CHECK: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) +vec_xst_be(vsc, sll, asc); +// CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) + +vec_xst_be(vuc, sll, auc); +// CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) + +vec_xst_be(vss, sll, ass); +// CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) + +vec_xst_be(vus, sll, aus); +// CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) + +vec_xst_be(vsi, sll, asi); +// CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) + +vec_xst_be(vui, sll, aui); +// CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) + +vec_xst_be(vf, sll, af); +// CHECK: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 1 +// CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) + res_vf = vec_neg(vf); // CHECK: fneg <4 x float> {{%[0-9]+}} // CHECK-LE: fneg <4 x float> {{%[0-9]+}} diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr8.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr8.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr8.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr8.c @@ -16,41 +16,31 @@ extern void *a; extern volatile char *c_addr; +extern char *ptr; extern char c; +extern int i; +extern vector unsigned char vuc; -void test_icbt() { -// CHECK-LABEL: @test_icbt( - +void test_xlcompat() { + // CHECK-PWR8-LABEL: @test_xlcompat( + // CHECK-PWR8: call void @llvm.ppc.icbt(ptr %{{[0-9]+}}) + // CHECK-NOPWR8: error: '__builtin_ppc_icbt' needs target feature isa-v207-instructions __icbt(a); -// CHECK-PWR8: call void @llvm.ppc.icbt(ptr %0) -// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs -} - -void test_builtin_ppc_icbt() { -// CHECK-LABEL: @test_builtin_ppc_icbt( + // CHECK-PWR8: call void @llvm.ppc.icbt(ptr %{{[0-9]+}}) + // CHECK-NOPWR8: error: '__builtin_ppc_icbt' needs target feature isa-v207-instructions __builtin_ppc_icbt(a); -// CHECK-PWR8: call void @llvm.ppc.icbt(ptr %0) -// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs -} -int test_builtin_ppc_stbcx() { -// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx( -// CHECK-PWR8: [[TMP0:%.*]] = load ptr, ptr @c_addr, align {{[0-9]+}} -// CHECK-PWR8-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1 -// CHECK-PWR8-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK-PWR8-NEXT: [[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(ptr [[TMP0]], i32 [[TMP2]]) -// CHECK-PWR8-NEXT: ret i32 [[TMP3]] -// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs - return __builtin_ppc_stbcx(c_addr, c); -} + // CHECK-PWR8: [[TMP0:%.*]] = load ptr, ptr @c_addr, align {{[0-9]+}} + // CHECK-PWR8-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1 + // CHECK-PWR8-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 + // CHECK-PWR8-NEXT: [[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(ptr [[TMP0]], i32 [[TMP2]]) + // CHECK-NOPWR8: error: '__builtin_ppc_stbcx' needs target feature isa-v207-instructions + i = __builtin_ppc_stbcx(c_addr, c); -vector unsigned char test_ldrmb(char *ptr) { - // CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs - return __builtin_vsx_ldrmb(ptr, 14); -} + // CHECK-NOPWR8: error: '__builtin_vsx_ldrmb' needs target feature isa-v207-instructions + vuc = __builtin_vsx_ldrmb(ptr, 14); -void test_strmbb(char *ptr, vector unsigned char data) { - // CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs - __builtin_vsx_strmb(ptr, 14, data); + // CHECK-NOPWR8: error: '__builtin_vsx_strmb' needs target feature isa-v207-instructions + __builtin_vsx_strmb(ptr, 14, vuc); } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.c @@ -12,87 +12,57 @@ extern signed long long sll; extern unsigned long long ull; +double d; -signed long long test_builtin_ppc_cmpeqb() { - // CHECK-LABEL: @test_builtin_ppc_cmpeqb( - // CHECK: %2 = call i64 @llvm.ppc.cmpeqb(i64 %0, i64 %1) +void test_compat_builtins() { + // CHECK-LABEL: @test_compat_builtins( + // CHECK: %2 = call i64 @llvm.ppc.cmpeqb(i64 %0, i64 %1) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_cmpeqb(sll, sll); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_cmpeqb' needs target feature isa-v30-instructions + sll = __builtin_ppc_cmpeqb(sll, sll); -long long test_builtin_ppc_setb() { - // CHECK-LABEL: @test_builtin_ppc_setb( - // CHECK: %2 = call i64 @llvm.ppc.setb(i64 %0, i64 %1) + // CHECK: %5 = call i64 @llvm.ppc.setb(i64 %3, i64 %4) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_setb(sll, sll); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_setb' needs target feature isa-v30-instructions + sll = __builtin_ppc_setb(sll, sll); -signed long long test_builtin_ppc_maddhd() { - // CHECK-LABEL: @test_builtin_ppc_maddhd( - // CHECK: %3 = call i64 @llvm.ppc.maddhd(i64 %0, i64 %1, i64 %2) + // CHECK: %9 = call i64 @llvm.ppc.maddhd(i64 %6, i64 %7, i64 %8) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_maddhd(sll, sll, sll); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_maddhd' needs target feature isa-v30-instructions + sll = __builtin_ppc_maddhd(sll, sll, sll); -unsigned long long test_builtin_ppc_maddhdu() { - // CHECK-LABEL: @test_builtin_ppc_maddhdu( - // CHECK: %3 = call i64 @llvm.ppc.maddhdu(i64 %0, i64 %1, i64 %2) + // CHECK: %13 = call i64 @llvm.ppc.maddhdu(i64 %10, i64 %11, i64 %12) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_maddhdu(ull, ull, ull); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_maddhdu' needs target feature isa-v30-instructions + ull = __builtin_ppc_maddhdu(ull, ull, ull); -signed long long test_builtin_ppc_maddld() { - // CHECK-LABEL: @test_builtin_ppc_maddld( - // CHECK: %3 = call i64 @llvm.ppc.maddld(i64 %0, i64 %1, i64 %2) + // CHECK: %17 = call i64 @llvm.ppc.maddld(i64 %14, i64 %15, i64 %16) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_maddld(sll, sll, sll); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_maddld' needs target feature isa-v30-instructions + sll = __builtin_ppc_maddld(sll, sll, sll); -unsigned long long test_builtin_ppc_maddld_unsigned() { - // CHECK-LABEL: @test_builtin_ppc_maddld_unsigned( - // CHECK: %3 = call i64 @llvm.ppc.maddld(i64 %0, i64 %1, i64 %2) + // CHECK: %21 = call i64 @llvm.ppc.maddld(i64 %18, i64 %19, i64 %20) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_maddld(ull, ull, ull); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_maddld' needs target feature isa-v30-instructions + ull = __builtin_ppc_maddld(ull, ull, ull); -unsigned long long extract_sig (double d) { -// CHECK-LABEL: @extract_sig( -// CHECK: [[TMP1:%.*]] = call i64 @llvm.ppc.extract.sig(double %0) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __extract_sig (d); -} + // CHECK: %23 = call i64 @llvm.ppc.extract.sig(double %22) + // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_extract_sig' needs target feature power9-vector + ull = __extract_sig (d); -double insert_exp (double d, unsigned long long ull) { -// CHECK-LABEL: @insert_exp( -// CHECK: [[TMP2:%.*]] = call double @llvm.ppc.insert.exp(double %0, i64 %1) -// CHECK-NEXT: ret double [[TMP2]] -// -// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __insert_exp (d, ull); -} + // CHECK: %26 = call double @llvm.ppc.insert.exp(double %24, i64 %25) + // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_insert_exp' needs target feature power9-vector + d = __insert_exp (d, ull); -signed long long test_builtin_ppc_addex0() { - // CHECK-LABEL: @test_builtin_ppc_addex0 - // CHECK: %2 = call i64 @llvm.ppc.addex(i64 %0, i64 %1, i32 0) + // CHECK: %29 = call i64 @llvm.ppc.addex(i64 %27, i64 %28, i32 0) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_addex(sll, sll, 0); -} + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_addex' needs target feature isa-v30-instructions + sll = __builtin_ppc_addex(sll, sll, 0); -unsigned long long test_builtin_ppc_addex1() { - // CHECK-LABEL: @test_builtin_ppc_addex1 - // CHECK: %2 = call i64 @llvm.ppc.addex(i64 %0, i64 %1, i32 0) + // CHECK: %32 = call i64 @llvm.ppc.addex(i64 %30, i64 %31, i32 0) // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_addex(ull, ull, 0); + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_addex' needs target feature isa-v30-instructions + ull = __builtin_ppc_addex(ull, ull, 0); } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.c @@ -12,18 +12,12 @@ extern unsigned int ui; -int test_builtin_ppc_cmprb() { - // CHECK-LABEL: @test_builtin_ppc_cmprb( +int test_builtin_ppc_cmprb_extract_exp(double d) { + // CHECK-LABEL: @test_builtin_ppc_cmprb_extract_exp( // CHECK: %2 = call i32 @llvm.ppc.cmprb(i32 0, i32 %0, i32 %1) // CHECK: %5 = call i32 @llvm.ppc.cmprb(i32 1, i32 %3, i32 %4) - // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __builtin_ppc_cmprb(0, ui, ui) + __builtin_ppc_cmprb(1, ui, ui); -} - -unsigned int extract_exp (double d) { -// CHECK-LABEL: @extract_exp -// CHECK: [[TMP1:%.*]] = call i32 @llvm.ppc.extract.exp(double %0) -// CHECK-NEXT: ret i32 [[TMP1]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs - return __extract_exp (d); + // CHECK: %7 = call i32 @llvm.ppc.extract.exp(double %6) + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_cmprb' needs target feature isa-v30-instructions + // CHECK-NONPWR9-ERR: error: '__builtin_ppc_extract_exp' needs target feature power9-vector + return __builtin_ppc_cmprb(0, ui, ui) + __builtin_ppc_cmprb(1, ui, ui) + __extract_exp(d); } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c @@ -16,110 +16,58 @@ extern double d; extern float f; -int test_builtin_ppc_compare_exp_uo() { -// CHECK-LABEL: @test_builtin_ppc_compare_exp_uo -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.uo(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __builtin_ppc_compare_exp_uo(d, d); -} - -int test_builtin_ppc_compare_exp_lt() { -// CHECK-LABEL: @test_builtin_ppc_compare_exp_lt -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.lt(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __builtin_ppc_compare_exp_lt(d, d); -} - -int test_builtin_ppc_compare_exp_gt() { -// CHECK-LABEL: @test_builtin_ppc_compare_exp_gt -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.gt(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __builtin_ppc_compare_exp_gt(d, d); -} - -int test_builtin_ppc_compare_exp_eq() { -// CHECK-LABEL: @test_builtin_ppc_compare_exp_eq -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.eq(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __builtin_ppc_compare_exp_eq(d, d); -} - -int test_builtin_ppc_test_data_class_d() { -// CHECK-LABEL: @test_builtin_ppc_test_data_class_d -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.test.data.class.f64(double %0, i32 0) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __builtin_ppc_test_data_class(d, 0); -} - -int test_builtin_ppc_test_data_class_f() { -// CHECK-LABEL: @test_builtin_ppc_test_data_class_f -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.test.data.class.f32(float %0, i32 0) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __builtin_ppc_test_data_class(f, 0); -} - -int test_compare_exp_uo() { -// CHECK-LABEL: @test_compare_exp_uo -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.uo(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __compare_exp_uo(d, d); -} - -int test_compare_exp_lt() { -// CHECK-LABEL: @test_compare_exp_lt -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.lt(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __compare_exp_lt(d, d); -} +int test_builtin_ppc_test() { +// CHECK-LABEL: @test_builtin_ppc_test +// CHECK: call i32 @llvm.ppc.compare.exp.uo(double %0, double %1) +// CHECK: call i32 @llvm.ppc.compare.exp.lt(double %3, double %4) +// CHECK: call i32 @llvm.ppc.compare.exp.gt(double %6, double %7) +// CHECK: call i32 @llvm.ppc.compare.exp.eq(double %9, double %10) +// CHECK: call i32 @llvm.ppc.test.data.class.f64(double %12, i32 0) +// CHECK: call i32 @llvm.ppc.test.data.class.f32(float %13, i32 0) +// CHECK: call i32 @llvm.ppc.compare.exp.uo(double %14, double %15) +// CHECK: call i32 @llvm.ppc.compare.exp.lt(double %17, double %18) +// CHECK: call i32 @llvm.ppc.compare.exp.gt(double %20, double %21) +// CHECK: call i32 @llvm.ppc.compare.exp.eq(double %23, double %24) +// CHECK: call i32 @llvm.ppc.test.data.class.f64(double %26, i32 127) +// CHECK: call i32 @llvm.ppc.test.data.class.f32(float %27, i32 127) -int test_compare_exp_gt() { -// CHECK-LABEL: @test_compare_exp_gt -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.gt(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __compare_exp_gt(d, d); -} - -int test_compare_exp_eq() { -// CHECK-LABEL: @test_compare_exp_eq -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.eq(double %0, double %1) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __compare_exp_eq(d, d); -} - -int test_test_data_class_d() { -// CHECK-LABEL: @test_test_data_class_d -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.test.data.class.f64(double %0, i32 127) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __test_data_class(d, 127); -} +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_gt' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_eq' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_gt' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_compare_exp_eq' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions +// CHECK-NONPWR9-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions -int test_test_data_class_f() { -// CHECK-LABEL: @test_test_data_class_f -// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.test.data.class.f32(float %0, i32 127) -// CHECK-NEXT: ret i32 [[TMP]] -// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs -// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled - return __test_data_class(f, 127); +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_gt' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_eq' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_gt' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_eq' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions,vsx +// CHECK-NOVSX-ERR: error: '__builtin_ppc_test_data_class' needs target feature isa-v30-instructions,vsx + int i; + i = __builtin_ppc_compare_exp_uo(d, d); + i = __builtin_ppc_compare_exp_lt(d, d); + i = __builtin_ppc_compare_exp_gt(d, d); + i = __builtin_ppc_compare_exp_eq(d, d); + i = __builtin_ppc_test_data_class(d, 0); + i = __builtin_ppc_test_data_class(f, 0); + i = __compare_exp_uo(d, d); + i = __compare_exp_lt(d, d); + i = __compare_exp_gt(d, d); + i = __compare_exp_eq(d, d); + i = __test_data_class(d, 127); + i = __test_data_class(f, 127); + return i; } diff --git a/clang/test/CodeGen/PowerPC/ppc-p10-mma-builtin-err.c b/clang/test/CodeGen/PowerPC/ppc-p10-mma-builtin-err.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/ppc-p10-mma-builtin-err.c @@ -0,0 +1,13 @@ +// RUN: not %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-cpu pwr10 \ +// RUN: %s -emit-llvm-only 2>&1 | FileCheck %s + +__attribute__((target("no-mma"))) +void test_mma(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { + __vector_quad vq = *((__vector_quad *)vqp); + __vector_pair vp = *((__vector_pair *)vpp); + __builtin_mma_xxmtacc(&vq); + *((__vector_quad *)resp) = vq; + __builtin_mma_pmxvf64ger(&vq, vp, vc, 0, 0); +// CHECK: error: '__builtin_mma_xxmtacc' needs target feature mma,paired-vector-memops +// CHECK: error: '__builtin_mma_pmxvf64ger' needs target feature mma,paired-vector-memops +} diff --git a/clang/test/CodeGen/PowerPC/ppc-p10-paired-vec-memops-builtin-err.c b/clang/test/CodeGen/PowerPC/ppc-p10-paired-vec-memops-builtin-err.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/ppc-p10-paired-vec-memops-builtin-err.c @@ -0,0 +1,20 @@ +// RUN: not %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-cpu pwr10 \ +// RUN: %s -emit-llvm-only 2>&1 | FileCheck %s + +__attribute__((target("no-paired-vector-memops"))) +void test_pair(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { + __vector_pair res; + signed long offset; + __builtin_vsx_assemble_pair(&res, vc, vc); + __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); + __vector_pair vp = __builtin_vsx_lxvp(offset, (const __vector_pair*)vpp); + __builtin_vsx_stxvp(vp, offset, (__vector_pair*)vpp); + __builtin_mma_xxmtacc((__vector_quad *)vpp); + __builtin_mma_pmxvf64ger((__vector_quad *)vpp, vp, vc, 0, 0); +// CHECK: error: '__builtin_vsx_assemble_pair' needs target feature paired-vector-memops +// CHECK: error: '__builtin_vsx_disassemble_pair' needs target feature paired-vector-memops +// CHECK: error: '__builtin_vsx_lxvp' needs target feature paired-vector-memops +// CHECK: error: '__builtin_vsx_stxvp' needs target feature paired-vector-memops +// CHECK: error: '__builtin_mma_xxmtacc' needs target feature mma,paired-vector-memops +// CHECK: error: '__builtin_mma_pmxvf64ger' needs target feature mma,paired-vector-memops +} diff --git a/clang/test/Sema/ppc-mma-builtins.c b/clang/test/Sema/ppc-mma-builtins.c deleted file mode 100644 --- a/clang/test/Sema/ppc-mma-builtins.c +++ /dev/null @@ -1,33 +0,0 @@ -// REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ -// RUN: -target-feature -mma -fsyntax-only %s -verify - -void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __vector_pair res; - __builtin_vsx_assemble_pair(&res, vc, vc); -} - -void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); -} - -void test3(const __vector_pair *vpp, signed long offset, __vector_pair *vp2) { - __vector_pair vp = __builtin_vsx_lxvp(offset, vpp); - __builtin_vsx_stxvp(vp, offset, vp2); -} - -void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __vector_quad vq = *((__vector_quad *)vqp); - __vector_pair vp = *((__vector_pair *)vpp); - __builtin_mma_xxmtacc(&vq); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} - *((__vector_quad *)resp) = vq; -} - -void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __vector_quad vq = *((__vector_quad *)vqp); - __vector_pair vp = *((__vector_pair *)vpp); - __builtin_mma_pmxvf64ger(&vq, vp, vc, 0, 0); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} - *((__vector_quad *)resp) = vq; -} - - diff --git a/clang/test/Sema/ppc-paired-vector-builtins.c b/clang/test/Sema/ppc-paired-vector-builtins.c deleted file mode 100644 --- a/clang/test/Sema/ppc-paired-vector-builtins.c +++ /dev/null @@ -1,28 +0,0 @@ -// REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ -// RUN: -target-feature -paired-vector-memops -fsyntax-only %s -verify -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \ -// RUN: -fsyntax-only %s -verify - -void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __vector_pair res; - __builtin_vsx_assemble_pair(&res, vc, vc); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} -} - -void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} -} - -void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) { - __vector_pair vp = __builtin_vsx_lxvp(offset, vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} - __builtin_vsx_stxvp(vp, offset, vp2); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} -} - -void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { - __vector_quad vq = *((__vector_quad *)vqp); - __vector_pair vp = *((__vector_pair *)vpp); - __builtin_mma_xxmtacc(&vq); // expected-error {{this builtin is only valid on POWER10 or later CPUs}} - *((__vector_quad *)resp) = vq; -} - -