diff --git a/clang/lib/Driver/SanitizerArgs.cpp b/clang/lib/Driver/SanitizerArgs.cpp --- a/clang/lib/Driver/SanitizerArgs.cpp +++ b/clang/lib/Driver/SanitizerArgs.cpp @@ -19,6 +19,7 @@ #include "llvm/Support/TargetParser.h" #include "llvm/Support/VirtualFileSystem.h" #include "llvm/TargetParser/AArch64TargetParser.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h" #include @@ -545,7 +546,8 @@ if ((Kinds & SanitizerKind::ShadowCallStack) && ((TC.getTriple().isAArch64() && !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) || - TC.getTriple().isRISCV()) && + (TC.getTriple().isRISCV() && + !llvm::RISCV::isX18ReservedByDefault(TC.getTriple()))) && !Args.hasArg(options::OPT_ffixed_x18) && DiagnoseErrors) { D.Diag(diag::err_drv_argument_only_allowed_with) << lastArgumentForMask(D, Args, Kinds & SanitizerKind::ShadowCallStack) diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -18,6 +18,9 @@ #include namespace llvm { + +class Triple; + namespace RISCV { // We use 64 bits as the known part in the scalable vector types. @@ -38,6 +41,8 @@ void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64); bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features); +bool isX18ReservedByDefault(const Triple &TT); + } // namespace RISCV } // namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -11,13 +11,13 @@ //===----------------------------------------------------------------------===// #include "RISCVSubtarget.h" +#include "GISel/RISCVCallLowering.h" +#include "GISel/RISCVLegalizerInfo.h" +#include "GISel/RISCVRegisterBankInfo.h" #include "RISCV.h" #include "RISCVFrameLowering.h" #include "RISCVMacroFusion.h" #include "RISCVTargetMachine.h" -#include "GISel/RISCVCallLowering.h" -#include "GISel/RISCVLegalizerInfo.h" -#include "GISel/RISCVRegisterBankInfo.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" @@ -84,6 +84,9 @@ initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this), TargetTriple(TT) { + if (RISCV::isX18ReservedByDefault(TT)) + UserReservedRegister.set(RISCV::X18); + CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); Legalizer.reset(new RISCVLegalizerInfo(*this)); diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -14,6 +14,7 @@ #include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" +#include "llvm/TargetParser/Triple.h" namespace llvm { namespace RISCV { @@ -100,5 +101,10 @@ return true; } +bool isX18ReservedByDefault(const Triple &TT) { + // X18 is reserved for the ShadowCallStack ABI (even when not enabled). + return TT.isOSFuchsia(); +} + } // namespace RISCV } // namespace llvm diff --git a/llvm/test/CodeGen/RISCV/reserved-regs.ll b/llvm/test/CodeGen/RISCV/reserved-regs.ll --- a/llvm/test/CodeGen/RISCV/reserved-regs.ll +++ b/llvm/test/CodeGen/RISCV/reserved-regs.ll @@ -57,6 +57,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31 +; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18 + ; This program is free to use all registers, but needs a stack pointer for ; spill values, so do not test for reserving the stack pointer.