diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17584,7 +17584,8 @@
 }
 
 static SDValue performTruncateCombine(SDNode *N,
-                                      SelectionDAG &DAG) {
+                                      SelectionDAG &DAG,
+                                      const AArch64Subtarget *Subtarget) {
   EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0);
   if (VT.isFixedLengthVector() && VT.is64BitVector() && N0.hasOneUse() &&
@@ -17596,6 +17597,77 @@
     return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Op);
   }
 
+  // If we see something like trunc( lshr( add(add(a, b), c) , 1) ), where one of (a,b,c) should be 0 or 1 then
+  // we can convert that into lshr(a, 1) + lshr(b, 1) + (a|b)&1
+  if(!Subtarget->hasSVE2() && N->getOperand(0).getOpcode() == ISD::SRL) {
+    SDValue Op0 = N->getOperand(0).getOperand(0); //add(add(a, b), c)
+    SDValue Op1 = N->getOperand(0).getOperand(1); //shiftAmount
+
+    if(Op0.getOpcode() != ISD::ADD)
+      return SDValue();
+
+    if(!isOneConstant(Op1))
+      return SDValue();
+
+    if(Op0.getOperand(0).getOpcode() != ISD::ADD) // add(a, b)
+      return SDValue();
+
+    SDValue A, B, C;
+    C = Op0.getOperand(1);
+    A = Op0.getOperand(0).getOperand(0); // a
+    B = Op0.getOperand(0).getOperand(1); // b
+
+    // we have add(add(a, b), c),
+    // one of a or b or c should be a constant 0 or 1:
+    // usually C is the constant, but in some cases, A or B may be the constant.
+    // check if any A or B is the constants, and then swap them with C
+    if(isNullConstant(A) || isOneConstant(A)) {
+      SDValue tmp = A;
+      A = C;
+      C = tmp;
+    }
+    else if(isNullConstant(B) || isOneConstant(B)) {
+      SDValue tmp = B;
+      B = C;
+      C = tmp;
+    }
+    else if(!isNullConstant(C) && !isOneConstant(C))
+      // no constant found
+      return SDValue();
+
+    if(A.getOpcode() == ISD::ZERO_EXTEND)
+      A = A.getOperand(0);
+
+    if(B.getOpcode() == ISD::ZERO_EXTEND)
+      B = B.getOperand(0);
+
+    // (A >> 1)
+    SDValue AShifted = DAG.getNode(ISD::SRL, SDLoc(N), A.getValueType(), A, Op1);
+    // (B >> 1)
+    SDValue BShifted = DAG.getNode(ISD::SRL, SDLoc(N), B.getValueType(), B, Op1);
+
+    SDValue AB;
+    if(isNullConstant(C)) {
+    // (A & B)
+      AB = DAG.getNode(ISD::AND, SDLoc(N), A.getValueType(), A, B);
+    }
+    else {
+    // (A | B)
+      AB = DAG.getNode(ISD::OR, SDLoc(N), A.getValueType(), A, B);
+    }
+
+    // (A & B)&1
+    // (A | B)&1
+    SDValue ABndOne = DAG.getNode(ISD::AND, SDLoc(N), A.getValueType(), AB, DAG.getConstant(1, SDLoc(N), AB.getValueType()));
+
+    // AShifted + BShifted
+    SDValue Add1 = DAG.getNode(ISD::ADD, SDLoc(N), AShifted.getValueType(), AShifted, BShifted);
+    // (AShifted + BShifted) + ABndOne
+    SDValue newInstr = DAG.getNode(ISD::ADD, SDLoc(N), AShifted.getValueType(), Add1, ABndOne);
+
+    return newInstr;
+  }
+
   return SDValue();
 }
 
@@ -18474,7 +18546,8 @@
 
 static SDValue performExtendCombine(SDNode *N,
                                     TargetLowering::DAGCombinerInfo &DCI,
-                                    SelectionDAG &DAG) {
+                                    SelectionDAG &DAG,
+                                    const AArch64Subtarget *Subtarget) {
   // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
   // we can convert that DUP into another extract_high (of a bigger DUP), which
   // helps the backend to decide that an sabdl2 would be useful, saving a real
@@ -18496,6 +18569,66 @@
       N->getOperand(0)->getOpcode() == ISD::SETCC)
     return performSignExtendSetCCCombine(N, DCI, DAG);
 
+  // If we see something like zext( lshr( add(add(a, b), 1) , 1) ) then
+  // we can convert that into lshr(a, 1) + lshr(b, 1) + (a|b)&1
+  if(!Subtarget->hasSVE2() && N->getOperand(0).getOpcode() == ISD::SRL) {
+    SDValue Op0 = N->getOperand(0).getOperand(0); //add(add(a, b), 1)
+    SDValue Op1 = N->getOperand(0).getOperand(1); //shiftAmount
+    if(Op0.getOpcode() != ISD::ADD || !isOneConstant(Op1))
+      return SDValue();
+
+    if(Op0.getOperand(0).getOpcode() != ISD::ADD) // add(a, b)
+      return SDValue();
+
+    SDValue AddedValue = Op0.getOperand(1);
+    // AddedValue must be 0 or 1
+    if(!isNullConstant(AddedValue) && !isOneConstant(AddedValue))
+      return SDValue();
+
+    SDValue A, B;
+    if(Op0.getOperand(0).getOperand(0).getOpcode() == ISD::TRUNCATE)
+      A = Op0.getOperand(0).getOperand(0).getOperand(0); // a
+    else
+      A = Op0.getOperand(0).getOperand(0); // a
+
+    if(Op0.getOperand(0).getOperand(1).getOpcode() == ISD::TRUNCATE)
+      B = Op0.getOperand(0).getOperand(1).getOperand(0); // b
+    else
+      B = Op0.getOperand(0).getOperand(1); // b
+
+    // (A >> 1)
+    SDValue AShifted = DAG.getNode(ISD::SRL, SDLoc(N), A.getValueType(), A, Op1);
+    // (B >> 1)
+    SDValue BShifted = DAG.getNode(ISD::SRL, SDLoc(N), B.getValueType(), B, Op1);
+
+    SDValue AB;
+    if(isNullConstant(AddedValue)) {
+    // (A & B)
+      AB = DAG.getNode(ISD::AND, SDLoc(N), A.getValueType(), A, B);
+    }
+    else {
+    // (A | B)
+      AB = DAG.getNode(ISD::OR, SDLoc(N), A.getValueType(), A, B);
+    }
+
+    // (A & B)&1
+    // (A | B)&1
+    SDValue ABndOne = DAG.getNode(ISD::AND, SDLoc(N), A.getValueType(), AB, DAG.getConstant(1, SDLoc(N), AB.getValueType()));
+
+    // AShifted + BShifted
+    SDValue Add1 = DAG.getNode(ISD::ADD, SDLoc(N), AShifted.getValueType(), AShifted, BShifted);
+    // (AShifted + BShifted) + ABndOne
+    SDValue newInstr = DAG.getNode(ISD::ADD, SDLoc(N), AShifted.getValueType(), Add1, ABndOne);
+
+    if(N->getValueType(0).getSizeInBits() == newInstr.getValueSizeInBits())
+      return newInstr;
+
+    else if(N->getValueType(0).getSizeInBits() > newInstr.getValueSizeInBits())
+      return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), newInstr);
+
+    return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), newInstr);
+  }
+
   return SDValue();
 }
 
@@ -21482,7 +21615,7 @@
   case ISD::BUILD_VECTOR:
     return performBuildVectorCombine(N, DCI, DAG);
   case ISD::TRUNCATE:
-    return performTruncateCombine(N, DAG);
+    return performTruncateCombine(N, DAG, Subtarget);
   case AArch64ISD::ANDS:
     return performFlagSettingCombine(N, DCI, ISD::AND);
   case AArch64ISD::ADC:
@@ -21522,7 +21655,7 @@
   case ISD::ANY_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::SIGN_EXTEND:
-    return performExtendCombine(N, DCI, DAG);
+    return performExtendCombine(N, DCI, DAG, Subtarget);
   case ISD::SIGN_EXTEND_INREG:
     return performSignExtendInRegCombine(N, DCI, DAG);
   case ISD::CONCAT_VECTORS:
diff --git a/llvm/test/CodeGen/AArch64/neon-lshr.ll b/llvm/test/CodeGen/AArch64/neon-lshr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/neon-lshr.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+define i8 @lshr_trunc(i8 %a, i8%b)
+; CHECK-LABEL: lshr_trunc:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w1, #0xfe
+; CHECK-NEXT:    ubfx w9, w0, #1, #7
+; CHECK-NEXT:    orr w10, w0, w1
+; CHECK-NEXT:    add w8, w9, w8, lsr #1
+; CHECK-NEXT:    and w9, w10, #0x1
+; CHECK-NEXT:    add w0, w8, w9
+; CHECK-NEXT:    ret
+{
+  %zexta = zext i8 %a to i16
+  %zextb = zext i8 %b to i16
+  %zextab = add i16 %zexta, %zextb
+  %add = add i16 %zextab, 1
+  %shift = lshr i16 %add, 1
+  %trunca = trunc i16 %shift to i8
+  ret i8 %trunca
+}
+