diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2612,7 +2612,7 @@
 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
 // FIXME: can "hasSideEffects be dropped?
 // This gets lowered to an instruction sequence which takes 16 bytes
-let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1, Size = 16,
+let isCall = 1, Defs = [NZVC, LR, X0, X1], hasSideEffects = 1, Size = 16,
     isCodeGenOnly = 1 in
 def TLSDESC_CALLSEQ
     : Pseudo<(outs), (ins i64imm:$sym),
diff --git a/llvm/test/CodeGen/AArch64/aarch64-tls-flags.ll b/llvm/test/CodeGen/AArch64/aarch64-tls-flags.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-tls-flags.ll
@@ -0,0 +1,29 @@
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -relocation-model=pic -verify-machineinstrs %s -o - | FileCheck %s
+
+@var = thread_local global i32 zeroinitializer
+@test = global i32 zeroinitializer
+
+define i32 @test_thread_local() {
+; CHECK-LABEL: test_thread_local:
+
+  %testval = load i32, ptr @test
+  %test = icmp eq ptr @test, null
+  %val = load i32, ptr @var
+  %result = zext i1 %test to i32
+  %result2 = add i32 %val, %result
+  ret i32 %result2
+
+; CHECK: str x[[SPILL:[0-9]+]], [sp, #-16]
+; CHECK: adrp x[[TEST:[0-9]+]], :got:test
+; CHECK: ldr x[[TEST]], [x[[TEST]], :got_lo12:test]
+; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:var
+; CHECK-NEXT: ldr x[[CALLEE:[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:var]
+; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:var
+; CHECK-NEXT: .tlsdesccall var
+; CHECK-NEXT: blr x[[CALLEE]]
+
+; CHECK-NEXT: mrs x[[TP:[0-9]+]], TPIDR_EL0
+; CHECK-NEXT: ldr w[[TP]], [x[[TP]], x0]
+; CHECK-NEXT: cmp x[[IN:[0-9]+]], #0
+
+}