MSP430 calling convention updates

[Annahita]

Summary

This code updates the MSP430 target calling convention to conform to the MSP430 EABI in order to make it compatible with the new MSP430-GCC framework.

It includes:

1. Pass args in R12-R15
2. Return args in R12-R15
3. Store on stack and pass in registers starting with least significant word
4. 32-bit argument may be split between register (R15) and stack if no args placed on stack yet
5. Register ‘holes’ may be back-filled (but only by arguments that fit entirely in regs, no split args once first arg placed on stack)
6. Only R4 through R10 are callee-saved registers; R11 is updated to be caller-save

[asl]

Ok to commit with these 2 small changes. Thanks!

lib/Target/MSP430/MSP430ISelLowering.cpp

327

Add comment about backfilling here as well.

337

Minor nit: space after )

[iains]

(no comments on the actual patch) .. but...
Is the ABI documented somewhere public?
[I have a patch-in-progress that implements binary output for MSP430, it is likely that I'd need to update it to reflect the ABI]

[meadori]

Is the ABI documented somewhere public?

http://www.ti.com/lit/an/slaa534/slaa534.pdf

[meadori]

This patch looks good to me with respect to the MSP430 ABI. I did find one other change that needs to be made. Now that R11 is not preserved by the callee it should be marked as clobbered by the call instructions:

--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -207,7 +207,7 @@ let isCall = 1 in
   // a use to prevent stack-pointer assignments that appear immediately
   // before calls from potentially appearing dead. Uses for argument
   // registers are added manually.
-  let Defs = [R12, R13, R14, R15, SR],
+  let Defs = [R11, R12, R13, R14, R15, SR],
       Uses = [SP] in {
     def CALLi     : II16i<0x0,
                           (outs), (ins i16imm:$dst),

With that change I was able to run some simple programs compiled with Clang/LLVM against the GDB simulator.

[Annahita]

Please note that there are a couple errors in the ABI document.
First, no one is currently passing small structs in registers (GCC or TI) as the document states.
Second, a couple of the C helper functions are listed incorrectly. mspabi_divlu and mspabi_divllu should be mspabi_divul and mspabi_divull. I have local work implementing the C helper function api but it has not yet been submitted for review and in the meantime, GCC has corrected these 2 in a patch as well.

There is also still an omission in the passing of struct args-- the address of the struct should be passed as an argument, which is currently not implemented.

Also, please note that we are stalled on committing this patch until my supervisor gets some additional feedback on patent issues.

Thanks,
Anna Youssefi

lib/Target/MSP430/MSP430CallingConv.td

 //==- MSP430CallingConv.td - Calling Conventions for MSP430 -*- tablegen -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
-// This describes the calling conventions for MSP430 architecture.
+// This describes the calling conventions for the MSP430 architecture.
+// The calling convention has been updated to conform to the MSP430 EABI.(2015)
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // MSP430 Return Value Calling Convention
 //===----------------------------------------------------------------------===//
 def RetCC_MSP430 : CallingConv<[
-  // i8 are returned in registers R15B, R14B, R13B, R12B
-  CCIfType<[i8], CCAssignToReg<[R15B, R14B, R13B, R12B]>>,
+  // i8 are returned in registers R12B, R13B, R14B, R15B
+  CCIfType<[i8], CCAssignToReg<[R12B, R13B, R14B, R15B]>>,
 
-  // i16 are returned in registers R15, R14, R13, R12
-  CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
+  // i16 are returned in registers R12, R13, R14, R15
+  CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // MSP430 Argument Calling Conventions
 //===----------------------------------------------------------------------===//
 def CC_MSP430_AssignStack : CallingConv<[
   // Pass by value if the byval attribute is given
   CCIfByVal<CCPassByVal<2, 2>>,

lib/Target/MSP430/MSP430ISelLowering.cpp

 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the MSP430TargetLowering class.
 //
 //===----------------------------------------------------------------------===//
-
 #include "MSP430ISelLowering.h"
 #include "MSP430.h"
 #include "MSP430MachineFunctionInfo.h"
 #include "MSP430Subtarget.h"
 #include "MSP430TargetMachine.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
static void AnalyzeVarArgs(CCState &State,
   State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
 }
 
 static void AnalyzeVarArgs(CCState &State,
                            const SmallVectorImpl<ISD::InputArg> &Ins) {
   State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
 }
 
-/// Analyze incoming and outgoing function arguments. We need custom C++ code
-/// to handle special constraints in the ABI like reversing the order of the
-/// pieces of splitted arguments. In addition, all pieces of a certain argument
-/// have to be passed either using registers or the stack but never mixing both.
+/// Analyze incoming and outgoing function arguments.
+/// A 32-bit argument may be split between R15 and the stack if no arguments
+/// have been placed on the stack yet.
+/// 64-bit arguments are never split.
+/// Register 'holes' may be back-filled (but split-pairs no longer allowed).
+/// Arguments are assigned to registers and the stack with LSW first.
 template<typename ArgT>
 static void AnalyzeArguments(CCState &State,
                              SmallVectorImpl<CCValAssign> &ArgLocs,
                              const SmallVectorImpl<ArgT> &Args) {
   static const MCPhysReg RegList[] = {
-    MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
+    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
   };
   static const unsigned NbRegs = array_lengthof(RegList);
 
   if (State.isVarArg()) {
     AnalyzeVarArgs(State, Args);
     return;
   }
 
   SmallVector<unsigned, 4> ArgsParts;
   ParseFunctionArgs(Args, ArgsParts);
 
   unsigned RegsLeft = NbRegs;
-  bool UseStack = false;
   unsigned ValNo = 0;
+  bool StackUsed = false;
 
   for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
     MVT ArgVT = Args[ValNo].VT;
     ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
     MVT LocVT = ArgVT;
     CCValAssign::LocInfo LocInfo = CCValAssign::Full;
 
     // Promote i8 to i16
     if (LocVT == MVT::i8) {
       LocVT = MVT::i16;
       if (ArgFlags.isSExt())
           LocInfo = CCValAssign::SExt;
       else if (ArgFlags.isZExt())
           LocInfo = CCValAssign::ZExt;
       else
           LocInfo = CCValAssign::AExt;
     }
 
     // Handle byval arguments
     if (ArgFlags.isByVal()) {
       State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
       continue;
     }
 
-    unsigned Parts = ArgsParts[i];
+    unsigned PartsLeft = ArgsParts[i];
 
-    if (!UseStack && Parts <= RegsLeft) {
-      unsigned FirstVal = ValNo;
-      for (unsigned j = 0; j < Parts; j++) {
+    // Assign arguments to registers.
+    // Only 32-bit arguments may be split between R15 and the stack, and
+    // only if no arguments have been placed on the stack yet.
+    if ((PartsLeft != 0) &&
+        ((PartsLeft <= RegsLeft) ||
+         (PartsLeft == 2 && RegsLeft == 1 && !StackUsed))) {
+      for (; PartsLeft != 0 && RegsLeft != 0; PartsLeft--, RegsLeft--) {
         unsigned Reg = State.AllocateReg(RegList);
         State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
-        RegsLeft--;
-      }
-
-      // Reverse the order of the pieces to agree with the "big endian" format
-      // required in the calling convention ABI.
-      SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
-      std::reverse(B, B + Parts);
-    } else {
-      UseStack = true;
-      for (unsigned j = 0; j < Parts; j++)
-        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
-    }
       }
     }
-
-static void AnalyzeRetResult(CCState &State,
-                             const SmallVectorImpl<ISD::InputArg> &Ins) {
-  State.AnalyzeCallResult(Ins, RetCC_MSP430);
+    // Assign arguments to stack.
+    if (PartsLeft != 0){
+      StackUsed = true;
+      for (; PartsLeft != 0 ; PartsLeft--)
+        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
     }
-
-static void AnalyzeRetResult(CCState &State,
-                             const SmallVectorImpl<ISD::OutputArg> &Outs) {
-  State.AnalyzeReturn(Outs, RetCC_MSP430);
   }
-
-template<typename ArgT>
-static void AnalyzeReturnValues(CCState &State,
-                                SmallVectorImpl<CCValAssign> &RVLocs,
-                                const SmallVectorImpl<ArgT> &Args) {
-  AnalyzeRetResult(State, Args);
-
-  // Reverse splitted return values to get the "big endian" format required
-  // to agree with the calling convention ABI.
-  std::reverse(RVLocs.begin(), RVLocs.end());
 }
 
 SDValue
 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
                                            CallingConv::ID CallConv,
                                            bool isVarArg,
                                            const SmallVectorImpl<ISD::InputArg>
                                              &Ins,
MSP430TargetLowering::LowerReturn(SDValue Chain,
   // ISRs cannot return any value.
   if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
     report_fatal_error("ISRs cannot return any value");
 
   // CCState - Info about the registers and stack slot.
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
-  // Analize return values.
-  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
+  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
 
   SDValue Flag;
   SmallVector<SDValue, 4> RetOps(1, Chain);
 
   // Copy the result values into the output registers.
   for (unsigned i = 0; i != RVLocs.size(); ++i) {
     CCValAssign &VA = RVLocs[i];
     assert(VA.isRegLoc() && "Can only return in registers!");
MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
                                       SDLoc dl, SelectionDAG &DAG,
                                       SmallVectorImpl<SDValue> &InVals) const {
 
   // Assign locations to each value returned by this call.
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
-  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
+  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
 
   // Copy all of the result registers out of their specified physreg.
   for (unsigned i = 0; i != RVLocs.size(); ++i) {
     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
                                RVLocs[i].getValVT(), InFlag).getValue(1);
     InFlag = Chain.getValue(2);
     InVals.push_back(Chain.getValue(0));
   }

lib/Target/MSP430/MSP430RegisterInfo.cpp

MSP430RegisterInfo::MSP430RegisterInfo()
   : MSP430GenRegisterInfo(MSP430::PC) {}
 
 const MCPhysReg*
 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   const MSP430FrameLowering *TFI = getFrameLowering(*MF);
   const Function* F = MF->getFunction();
   static const MCPhysReg CalleeSavedRegs[] = {
     MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
-    MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
+    MSP430::R8, MSP430::R9, MSP430::R10,
     0
   };
   static const MCPhysReg CalleeSavedRegsFP[] = {
     MSP430::R5, MSP430::R6, MSP430::R7,
-    MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
+    MSP430::R8, MSP430::R9, MSP430::R10,
     0
   };
   static const MCPhysReg CalleeSavedRegsIntr[] = {
     MSP430::FP,  MSP430::R5,  MSP430::R6,  MSP430::R7,
     MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
     0
   };

test/CodeGen/MSP430/AddrMode-bis-rx.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define i16 @am1(i16 %x, i16* %a) nounwind {
   %1 = load i16, i16* %a
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am1:
-; CHECK:    bis.w 0(r14), r15
+; CHECK:    bis.w 0(r13), r12
 
 @foo = external global i16
 
 define i16 @am2(i16 %x) nounwind {
   %1 = load i16, i16* @foo
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am2:
-; CHECK:    bis.w &foo, r15
+; CHECK:    bis.w &foo, r12
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
 define i8 @am3(i8 %x, i16 %n) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
   %2 = load i8, i8* %1
   %3 = or i8 %2,%x
   ret i8 %3
 }
 ; CHECK-LABEL: am3:
-; CHECK:    bis.b bar(r14), r15
+; CHECK:    bis.b bar(r13), r12
 
 define i16 @am4(i16 %x) nounwind {
   %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am4:
-; CHECK:    bis.w &32, r15
+; CHECK:    bis.w &32, r12
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
   %1 = getelementptr i16, i16* %a, i16 2
   %2 = load i16, i16* %1
   %3 = or i16 %2,%x
   ret i16 %3
 }
 ; CHECK-LABEL: am5:
-; CHECK:    bis.w 4(r14), r15
+; CHECK:    bis.w 4(r13), r12
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
 
 define i16 @am6(i16 %x) nounwind {
   %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am6:
-; CHECK:    bis.w &baz+2, r15
+; CHECK:    bis.w &baz+2, r12
 
 %T = type { i16, [2 x i8] }
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
 
 define i8 @am7(i8 %x, i16 %n) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   %3= load i8, i8* %2
   %4 = or i8 %3,%x
   ret i8 %4
 }
 ; CHECK-LABEL: am7:
-; CHECK:    bis.b duh+2(r14), r15
+; CHECK:    bis.b duh+2(r13), r12
 

test/CodeGen/MSP430/AddrMode-bis-xr.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define void @am1(i16* %a, i16 %x) nounwind {
   %1 = load i16, i16* %a
   %2 = or i16 %x, %1
   store i16 %2, i16* %a
   ret void
 }
 ; CHECK-LABEL: am1:
-; CHECK:    bis.w r14, 0(r15)
+; CHECK:    bis.w r13, 0(r12)
 
 @foo = external global i16
 
 define void @am2(i16 %x) nounwind {
   %1 = load i16, i16* @foo
   %2 = or i16 %x, %1
   store i16 %2, i16* @foo
   ret void
 }
 ; CHECK-LABEL: am2:
-; CHECK:    bis.w r15, &foo
+; CHECK:    bis.w r12, &foo
 
 @bar = external global [2 x i8]
 
 define void @am3(i16 %i, i8 %x) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %i
   %2 = load i8, i8* %1
   %3 = or i8 %x, %2
   store i8 %3, i8* %1
   ret void
 }
 ; CHECK-LABEL: am3:
-; CHECK:    bis.b r14, bar(r15)
+; CHECK:    bis.b r13, bar(r12)
 
 define void @am4(i16 %x) nounwind {
   %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
   %2 = or i16 %x, %1
   store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
   ret void
 }
 ; CHECK-LABEL: am4:
-; CHECK:    bis.w r15, &32
+; CHECK:    bis.w r12, &32
 
 define void @am5(i16* %a, i16 %x) readonly {
   %1 = getelementptr inbounds i16, i16* %a, i16 2
   %2 = load i16, i16* %1
   %3 = or i16 %x, %2
   store i16 %3, i16* %1
   ret void
 }
 ; CHECK-LABEL: am5:
-; CHECK:    bis.w r14, 4(r15)
+; CHECK:    bis.w r13, 4(r12)
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer
 
 define void @am6(i16 %x) nounwind {
   %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   %2 = or i16 %x, %1
   store i16 %2, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   ret void
 }
 ; CHECK-LABEL: am6:
-; CHECK:    bis.w r15, &baz+2
+; CHECK:    bis.w r12, &baz+2
 
 %T = type { i16, [2 x i8] }
 @duh = external global %T
 
 define void @am7(i16 %n, i8 %x) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   %3 = load i8, i8* %2
   %4 = or i8 %x, %3
   store i8 %4, i8* %2
   ret void
 }
 ; CHECK-LABEL: am7:
-; CHECK:    bis.b r14, duh+2(r15)
+; CHECK:    bis.b r13, duh+2(r12)
 

test/CodeGen/MSP430/AddrMode-mov-rx.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define i16 @am1(i16* %a) nounwind {
   %1 = load i16, i16* %a
   ret i16 %1
 }
 ; CHECK-LABEL: am1:
-; CHECK:    mov.w 0(r15), r15
+; CHECK:    mov.w 0(r12), r12
 
 @foo = external global i16
 
 define i16 @am2() nounwind {
   %1 = load i16, i16* @foo
   ret i16 %1
 }
 ; CHECK-LABEL: am2:
-; CHECK:    mov.w &foo, r15
+; CHECK:    mov.w &foo, r12
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
 define i8 @am3(i16 %n) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
   %2 = load i8, i8* %1
   ret i8 %2
 }
 ; CHECK-LABEL: am3:
-; CHECK:    mov.b bar(r15), r15
+; CHECK:    mov.b bar(r12), r12
 
 define i16 @am4() nounwind {
   %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
   ret i16 %1
 }
 ; CHECK-LABEL: am4:
-; CHECK:    mov.w &32, r15
+; CHECK:    mov.w &32, r12
 
 define i16 @am5(i16* %a) nounwind {
   %1 = getelementptr i16, i16* %a, i16 2
   %2 = load i16, i16* %1
   ret i16 %2
 }
 ; CHECK-LABEL: am5:
-; CHECK:    mov.w 4(r15), r15
+; CHECK:    mov.w 4(r12), r12
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
 
 define i16 @am6() nounwind {
   %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   ret i16 %1
 }
 ; CHECK-LABEL: am6:
-; CHECK:    mov.w &baz+2, r15
+; CHECK:    mov.w &baz+2, r12
 
 %T = type { i16, [2 x i8] }
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
 
 define i8 @am7(i16 %n) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   %3= load i8, i8* %2
   ret i8 %3
 }
 ; CHECK-LABEL: am7:
-; CHECK:    mov.b duh+2(r15), r15
+; CHECK:    mov.b duh+2(r12), r12
 

test/CodeGen/MSP430/AddrMode-mov-xr.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define void @am1(i16* %a, i16 %b) nounwind {
   store i16 %b, i16* %a
   ret void
 }
 ; CHECK-LABEL: am1:
-; CHECK:    mov.w r14, 0(r15)
+; CHECK:    mov.w r13, 0(r12)
 
 @foo = external global i16
 
 define void @am2(i16 %a) nounwind {
   store i16 %a, i16* @foo
   ret void
 }
 ; CHECK-LABEL: am2:
-; CHECK:    mov.w r15, &foo
+; CHECK:    mov.w r12, &foo
 
 @bar = external global [2 x i8]
 
 define void @am3(i16 %i, i8 %a) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %i
   store i8 %a, i8* %1
   ret void
 }
 ; CHECK-LABEL: am3:
-; CHECK:    mov.b r14, bar(r15)
+; CHECK:    mov.b r13, bar(r12)
 
 define void @am4(i16 %a) nounwind {
   store volatile i16 %a, i16* inttoptr(i16 32 to i16*)
   ret void
 }
 ; CHECK-LABEL: am4:
-; CHECK:    mov.w r15, &32
+; CHECK:    mov.w r12, &32
 
 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
   %1 = getelementptr inbounds i16, i16* %p, i16 2
   store i16 %a, i16* %1
   ret void
 }
 ; CHECK-LABEL: am5:
-; CHECK:    mov.w r14, 4(r15)
+; CHECK:    mov.w r13, 4(r12)
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
 
 define void @am6(i16 %a) nounwind {
   store i16 %a, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   ret void
 }
 ; CHECK-LABEL: am6:
-; CHECK:    mov.w r15, &baz+2
+; CHECK:    mov.w r12, &baz+2
 
 %T = type { i16, [2 x i8] }
 @duh = external global %T
 
 define void @am7(i16 %n, i8 %a) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   store i8 %a, i8* %2
   ret void
 }
 ; CHECK-LABEL: am7:
-; CHECK:    mov.b r14, duh+2(r15)
+; CHECK:    mov.b r13, duh+2(r12)
 

test/CodeGen/MSP430/Inst16mr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define void @mov(i16 %a) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w  r15, &foo
+; CHECK: mov.w  r12, &foo
   store i16 %a, i16* @foo
   ret void
 }
 
 define void @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  r15, &foo
+; CHECK: add.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = add i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 
 define void @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  r15, &foo
+; CHECK: and.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = and i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 
 define void @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  r15, &foo
+; CHECK: bis.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = or i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 
 define void @bic(i16 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w   r15, &foo
+; CHECK: bic.w   r12, &foo
         %1 = xor i16 %m, -1
         %2 = load i16, i16* @foo
         %3 = and i16 %2, %1
         store i16 %3, i16* @foo
         ret void
 }
 
 define void @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  r15, &foo
+; CHECK: xor.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = xor i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 

test/CodeGen/MSP430/Inst16ri.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w  #1, r15
+; CHECK: mov.w  #1, r12
   ret i16 1
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  #1, r15
+; CHECK: add.w  #1, r12
   %1 = add i16 %a, 1
   ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  #1, r15
+; CHECK: and.w  #1, r12
   %1 = and i16 %a, 1
   ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  #1, r15
+; CHECK: bis.w  #1, r12
   %1 = or i16 %a, 1
   ret i16 %1
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  #1, r15
+; CHECK: xor.w  #1, r12
   %1 = xor i16 %a, 1
   ret i16 %1
 }

test/CodeGen/MSP430/Inst16rm.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define i16 @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  &foo, r15
+; CHECK: add.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = add i16 %a, %1
   ret i16 %2
 }
 
 define i16 @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  &foo, r15
+; CHECK: and.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = and i16 %a, %1
   ret i16 %2
 }
 
 define i16 @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  &foo, r15
+; CHECK: bis.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = or i16 %a, %1
   ret i16 %2
 }
 
 define i16  @bic(i16 %a) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w  &foo, r15
+; CHECK: bic.w  &foo, r12
         %1 = load i16, i16* @foo
         %2 = xor i16 %1, -1
         %3 = and i16 %a, %2
         ret i16 %3
 }
 
 define i16 @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  &foo, r15
+; CHECK: xor.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = xor i16 %a, %1
   ret i16 %2
 }
 

test/CodeGen/MSP430/Inst16rr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w  r14, r15
+; CHECK: mov.w  r13, r12
   ret i16 %b
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  r14, r15
+; CHECK: add.w  r13, r12
   %1 = add i16 %a, %b
   ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  r14, r15
+; CHECK: and.w  r13, r12
   %1 = and i16 %a, %b
   ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  r14, r15
+; CHECK: bis.w  r13, r12
   %1 = or i16 %a, %b
   ret i16 %1
 }
 
 define i16 @bic(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w  r14, r15
+; CHECK: bic.w  r13, r12
         %1 = xor i16 %b, -1
         %2 = and i16 %a, %1
         ret i16 %2
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  r14, r15
+; CHECK: xor.w  r13, r12
   %1 = xor i16 %a, %b
   ret i16 %1
 }

test/CodeGen/MSP430/Inst8mr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define void @mov(i8 %a) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.b  r15, &foo
+; CHECK: mov.b  r12, &foo
   store i8 %a, i8* @foo
   ret void
 }
 
 define void @and(i8 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.b  r15, &foo
+; CHECK: and.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = and i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 
 define void @add(i8 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b  r15, &foo
+; CHECK: add.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = add i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 
 define void @bis(i8 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.b  r15, &foo
+; CHECK: bis.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = or i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 
 define void @bic(i8 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.b   r15, &foo
+; CHECK: bic.b   r12, &foo
         %1 = xor i8 %m, -1
         %2 = load i8, i8* @foo
         %3 = and i8 %2, %1
         store i8 %3, i8* @foo
         ret void
 }
 
 define void @xor(i8 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.b  r15, &foo
+; CHECK: xor.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = xor i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 

test/CodeGen/MSP430/Inst8ri.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.b  #1, r15
+; CHECK: mov.b  #1, r12
   ret i8 1
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b  #1, r15
+; CHECK: add.b  #1, r12
   %1 = add i8 %a, 1
   ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.b  #1, r15
+; CHECK: and.b  #1, r12
   %1 = and i8 %a, 1
   ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.b  #1, r15
+; CHECK: bis.b  #1, r12
   %1 = or i8 %a, 1
   ret i8 %1
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.b  #1, r15
+; CHECK: xor.b  #1, r12
   %1 = xor i8 %a, 1
   ret i8 %1
 }

test/CodeGen/MSP430/Inst8rm.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define i8 @add(i8 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b  &foo, r15
+; CHECK: add.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = add i8 %a, %1
   ret i8 %2
 }
 
 define i8 @and(i8 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.b  &foo, r15
+; CHECK: and.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = and i8 %a, %1
   ret i8 %2
 }
 
 define i8 @bis(i8 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.b  &foo, r15
+; CHECK: bis.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = or i8 %a, %1
   ret i8 %2
 }
 
 define i8  @bic(i8 %a) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.b  &foo, r15
+; CHECK: bic.b  &foo, r12
         %1 = load i8, i8* @foo
         %2 = xor i8 %1, -1
         %3 = and i8 %a, %2
         ret i8 %3
 }
 
 define i8 @xor(i8 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.b  &foo, r15
+; CHECK: xor.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = xor i8 %a, %1
   ret i8 %2
 }
 

test/CodeGen/MSP430/Inst8rr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.{{[bw]}} r14, r15
+; CHECK: mov.{{[bw]}} r13, r12
   ret i8 %b
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.b
   %1 = add i8 %a, %b
   ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  r14, r15
+; CHECK: and.w  r13, r12
   %1 = and i8 %a, %b
   ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  r14, r15
+; CHECK: bis.w  r13, r12
   %1 = or i8 %a, %b
   ret i8 %1
 }
 
 define i8 @bic(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.b  r14, r15
+; CHECK: bic.b  r13, r12
         %1 = xor i8 %b, -1
         %2 = and i8 %a, %1
         ret i8 %2
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  r14, r15
+; CHECK: xor.w  r13, r12
   %1 = xor i8 %a, %b
   ret i8 %1
 }
 

test/CodeGen/MSP430/bit.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
 @foo8 = external global i8
 @bar8 = external global i8
 
 define i8 @bitbrr(i8 %a, i8 %b) nounwind {
   %t1 = and i8 %a, %b
   %t2 = icmp ne i8 %t1, 0
   %t3 = zext i1 %t2 to i8
   ret i8 %t3
 }
 ; CHECK-LABEL: bitbrr:
-; CHECK: bit.b  r14, r15
+; CHECK: bit.b  r13, r12
 
 define i8 @bitbri(i8 %a) nounwind {
   %t1 = and i8 %a, 15
   %t2 = icmp ne i8 %t1, 0
   %t3 = zext i1 %t2 to i8
   ret i8 %t3
 }
 ; CHECK-LABEL: bitbri:
-; CHECK: bit.b  #15, r15
+; CHECK: bit.b  #15, r12
 
 define i8 @bitbir(i8 %a) nounwind {
   %t1 = and i8 15, %a
   %t2 = icmp ne i8 %t1, 0
   %t3 = zext i1 %t2 to i8
   ret i8 %t3
 }
 ; CHECK-LABEL: bitbir:
-; CHECK: bit.b  #15, r15
+; CHECK: bit.b  #15, r12
 
 define i8 @bitbmi() nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = and i8 %t1, 15
   %t3 = icmp ne i8 %t2, 0
   %t4 = zext i1 %t3 to i8
   ret i8 %t4
 }

 define i8 @bitbrm(i8 %a) nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = and i8 %a, %t1
   %t3 = icmp ne i8 %t2, 0
   %t4 = zext i1 %t3 to i8
   ret i8 %t4
 }
 ; CHECK-LABEL: bitbrm:
-; CHECK: bit.b  &foo8, r15
+; CHECK: bit.b  &foo8, r12
 
 define i8 @bitbmr(i8 %a) nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = and i8 %t1, %a
   %t3 = icmp ne i8 %t2, 0
   %t4 = zext i1 %t3 to i8
   ret i8 %t4
 }
 ; CHECK-LABEL: bitbmr:
-; CHECK: bit.b  r15, &foo8
+; CHECK: bit.b  r12, &foo8
 
 define i8 @bitbmm() nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = load i8, i8* @bar8
   %t3 = and i8 %t1, %t2
   %t4 = icmp ne i8 %t3, 0
   %t5 = zext i1 %t4 to i8
   ret i8 %t5
 }
 ; CHECK-LABEL: bitbmm:
 ; CHECK: bit.b  &bar8, &foo8
 
 @foo16 = external global i16
 @bar16 = external global i16
 
 define i16 @bitwrr(i16 %a, i16 %b) nounwind {
   %t1 = and i16 %a, %b
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: bitwrr:
-; CHECK: bit.w  r14, r15
+; CHECK: bit.w  r13, r12
 
 define i16 @bitwri(i16 %a) nounwind {
   %t1 = and i16 %a, 4080
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: bitwri:
-; CHECK: bit.w  #4080, r15
+; CHECK: bit.w  #4080, r12
 
 define i16 @bitwir(i16 %a) nounwind {
   %t1 = and i16 4080, %a
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: bitwir:
-; CHECK: bit.w  #4080, r15
+; CHECK: bit.w  #4080, r12
 
 define i16 @bitwmi() nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = and i16 %t1, 4080
   %t3 = icmp ne i16 %t2, 0
   %t4 = zext i1 %t3 to i16
   ret i16 %t4
 }

 define i16 @bitwrm(i16 %a) nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = and i16 %a, %t1
   %t3 = icmp ne i16 %t2, 0
   %t4 = zext i1 %t3 to i16
   ret i16 %t4
 }
 ; CHECK-LABEL: bitwrm:
-; CHECK: bit.w  &foo16, r15
+; CHECK: bit.w  &foo16, r12
 
 define i16 @bitwmr(i16 %a) nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = and i16 %t1, %a
   %t3 = icmp ne i16 %t2, 0
   %t4 = zext i1 %t3 to i16
   ret i16 %t4
 }
 ; CHECK-LABEL: bitwmr:
-; CHECK: bit.w  r15, &foo16
+; CHECK: bit.w  r12, &foo16
 
 define i16 @bitwmm() nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = load i16, i16* @bar16
   %t3 = and i16 %t1, %t2
   %t4 = icmp ne i16 %t3, 0
   %t5 = zext i1 %t4 to i16
   ret i16 %t5
 }
 ; CHECK-LABEL: bitwmm:
 ; CHECK: bit.w  &bar16, &foo16
 

test/CodeGen/MSP430/byval.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 target triple = "msp430---elf"
 
 %struct.Foo = type { i16, i16, i16 }
 @foo = global %struct.Foo { i16 1, i16 2, i16 3 }, align 2
 
 define i16 @callee(%struct.Foo* byval %f) nounwind {
 entry:
 ; CHECK-LABEL: callee:
-; CHECK: mov.w 2(r1), r15
+; CHECK: mov.w 2(r1), r12
   %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
   %1 = load i16, i16* %0, align 2
   ret i16 %1
 }
 
 define void @caller() nounwind {
 entry:
 ; CHECK-LABEL: caller:
 ; CHECK: mov.w &foo+4, 4(r1)
 ; CHECK-NEXT: mov.w &foo+2, 2(r1)
 ; CHECK-NEXT: mov.w &foo, 0(r1)
   %call = call i16 @callee(%struct.Foo* byval @foo)
   ret void
 }

test/CodeGen/MSP430/cc_args.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
 target triple = "msp430---elf"
 
 define void @test() #0 {
 entry:
 ; CHECK: test:
 
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
 ; CHECK: call #f_i16
   call void @f_i16(i16 1)
 
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
+; CHECK: mov.w #772, r12
+; CHECK: mov.w #258, r13
 ; CHECK: call #f_i32
   call void @f_i32(i32 16909060)
 
 ; CHECK: mov.w #1800, r12
 ; CHECK: mov.w #1286, r13
 ; CHECK: mov.w #772, r14
 ; CHECK: mov.w #258, r15
 ; CHECK: call #f_i64
   call void @f_i64(i64 72623859790382856)
 
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
-; CHECK: mov.w #1800, r12
-; CHECK: mov.w #1286, r13
+; CHECK: mov.w #772, r12
+; CHECK: mov.w #258, r13
+; CHECK: mov.w #1800, r14
+; CHECK: mov.w #1286, r15
 ; CHECK: call #f_i32_i32
   call void @f_i32_i32(i32 16909060, i32 84281096)
 
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
 ; CHECK: mov.w #772, r13
 ; CHECK: mov.w #258, r14
-; CHECK: mov.w #2, r12
+; CHECK: mov.w #2, r15
 ; CHECK: call #f_i16_i32_i16
   call void @f_i16_i32_i16(i16 1, i32 16909060, i16 2)
 
-; CHECK: mov.w #2, 8(r1)
 ; CHECK: mov.w #258, 6(r1)
 ; CHECK: mov.w #772, 4(r1)
 ; CHECK: mov.w #1286, 2(r1)
 ; CHECK: mov.w #1800, 0(r1)
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
+; CHECK: mov.w #2, r13
 ; CHECK: call #f_i16_i64_i16
   call void @f_i16_i64_i16(i16 1, i64 72623859790382856, i16 2)
 
+; CHECK: mov.w #258, 0(r1)
+; CHECK: mov.w #1, r12
+; CHECK: mov.w #2, r13
+; CHECK: mov.w #3, r14
+; CHECK: mov.w #772, r15
+; CHECK: call #f_i16_i16_i16_i32
+  call void @f_i16_i16_i16_i32(i16 1, i16 2, i16 3, i32 16909060)
+
+; CHECK: mov.w #258, 10(r1)
+; CHECK: mov.w #772, 8(r1)
+; CHECK: mov.w #258, 6(r1)
+; CHECK: mov.w #772, 4(r1)
+; CHECK: mov.w #1286, 2(r1)
+; CHECK: mov.w #1800, 0(r1)
+; CHECK: mov.w #1, r12
+; CHECK: mov.w #0, r13
+; CHECK: mov.w #2, r14
+; CHECK: call #f_i32_i16_i64_i32
+  call void @f_i32_i16_i64_i32(i32 1, i16 2, i64 72623859790382856, i32 16909060)
+
+; CHECK: mov.w #258, 10(r1)
+; CHECK: mov.w #772, 8(r1)
+; CHECK: mov.w #258, 6(r1)
+; CHECK: mov.w #772, 4(r1)
+; CHECK: mov.w #1286, 2(r1)
+; CHECK: mov.w #1800, 0(r1)
+; CHECK: mov.w #1, r12
+; CHECK: mov.w #0, r13
+; CHECK: mov.w #2, r14
+; CHECK: mov.w #3, r15
+; CHECK: call #f_i32_i16_i64_i32_i16
+  call void @f_i32_i16_i64_i32_i16(i32 1, i16 2, i64 72623859790382856, i32 16909060, i16 3)
+
   ret void
 }
 
 @g_i16 = common global i16 0, align 2
 @g_i32 = common global i32 0, align 2
 @g_i64 = common global i64 0, align 2
 
 define void @f_i16(i16 %a) #0 {
 ; CHECK: f_i16:
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
   ret void
 }
 
 define void @f_i32(i32 %a) #0 {
 ; CHECK: f_i32:
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
+; CHECK: mov.w r13, &g_i32+2
+; CHECK: mov.w r12, &g_i32
   store volatile i32 %a, i32* @g_i32, align 2
   ret void
 }
 
 define void @f_i64(i64 %a) #0 {
 ; CHECK: f_i64:
 ; CHECK: mov.w r15, &g_i64+6
 ; CHECK: mov.w r14, &g_i64+4
 ; CHECK: mov.w r13, &g_i64+2
 ; CHECK: mov.w r12, &g_i64
   store volatile i64 %a, i64* @g_i64, align 2
   ret void
 }
 
 define void @f_i32_i32(i32 %a, i32 %b) #0 {
 ; CHECK: f_i32_i32:
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
-  store volatile i32 %a, i32* @g_i32, align 2
 ; CHECK: mov.w r13, &g_i32+2
 ; CHECK: mov.w r12, &g_i32
+  store volatile i32 %a, i32* @g_i32, align 2
+; CHECK: mov.w r15, &g_i32+2
+; CHECK: mov.w r14, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
   ret void
 }
 
 define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
 ; CHECK: f_i16_i32_i16:
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
 ; CHECK: mov.w r14, &g_i32+2
 ; CHECK: mov.w r13, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov.w r15, &g_i16
   store volatile i16 %c, i16* @g_i16, align 2
   ret void
 }
 
 define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
 ; CHECK: f_i16_i64_i16:
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
-;CHECK: mov.w 10(r4), &g_i64+6
-;CHECK: mov.w 8(r4), &g_i64+4
-;CHECK: mov.w 6(r4), &g_i64+2
-;CHECK: mov.w 4(r4), &g_i64
+; CHECK: mov.w 10(r4), &g_i64+6
+; CHECK: mov.w 8(r4), &g_i64+4
+; CHECK: mov.w 6(r4), &g_i64+2
+; CHECK: mov.w 4(r4), &g_i64
   store volatile i64 %b, i64* @g_i64, align 2
-;CHECK: mov.w 12(r4), &g_i16
+; CHECK: mov.w r13, &g_i16
+  store volatile i16 %c, i16* @g_i16, align 2
+  ret void
+}
+
+define void @f_i16_i16_i16_i32(i16 %a, i16 %b, i16 %c, i32 %d) #0 {
+; CHECK: f_i16_i16_i16_i32:
+; CHECK: mov.w r12, &g_i16
+  store volatile i16 %a, i16* @g_i16, align 2
+; CHECK: mov.w r13, &g_i16
+  store volatile i16 %b, i16* @g_i16, align 2
+; CHECK: mov.w r14, &g_i16
   store volatile i16 %c, i16* @g_i16, align 2
+; CHECK: mov.w r15, &g_i32
+; CHECK: mov.w 4(r4), &g_i32+2
+  store volatile i32 %d, i32* @g_i32, align 2
+  ret void
+}
+
+define void @f_i32_i16_i64_i32(i32 %a, i16 %b, i64 %c, i32 %d) #0 {
+; CHECK: f_i32_i16_i64_i32:
+; CHECK: mov.w r13, &g_i32+2
+; CHECK: mov.w r12, &g_i32
+  store volatile i32 %a, i32* @g_i32, align 2
+; CHECK: mov.w r14, &g_i16
+  store volatile i16 %b, i16* @g_i16, align 2
+; CHECK: mov.w 10(r4), &g_i64+6
+; CHECK: mov.w 8(r4), &g_i64+4
+; CHECK: mov.w 6(r4), &g_i64+2
+; CHECK: mov.w 4(r4), &g_i64
+  store volatile i64 %c, i64* @g_i64, align 2
+; CHECK: mov.w 14(r4), &g_i32+2
+; CHECK: mov.w 12(r4), &g_i32
+  store volatile i32 %d, i32* @g_i32, align 2
+  ret void
+}
+
+define void @f_i32_i16_i64_i32_i16(i32 %a, i16 %b, i64 %c, i32 %d, i16 %e) #0 {
+; CHECK: f_i32_i16_i64_i32_i16:
+; CHECK: mov.w r13, &g_i32+2
+; CHECK: mov.w r12, &g_i32
+  store volatile i32 %a, i32* @g_i32, align 2
+; CHECK: mov.w r14, &g_i16
+  store volatile i16 %b, i16* @g_i16, align 2
+; CHECK: mov.w r15, &g_i16
+  store volatile i16 %e, i16* @g_i16, align 2
+; CHECK: mov.w 10(r4), &g_i64+6
+; CHECK: mov.w 8(r4), &g_i64+4
+; CHECK: mov.w 6(r4), &g_i64+2
+; CHECK: mov.w 4(r4), &g_i64
+  store volatile i64 %c, i64* @g_i64, align 2
+; CHECK: mov.w 14(r4), &g_i32+2
+; CHECK: mov.w 12(r4), &g_i32
+  store volatile i32 %d, i32* @g_i32, align 2
   ret void
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/MSP430/cc_ret.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
 target triple = "msp430---elf"
 
 define void @test() #0 {
 entry:
 ; CHECK: test:
 
 ; CHECK: call #f_i16
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   %0 = call i16 @f_i16()
   store volatile i16 %0, i16* @g_i16
 
 ; CHECK: call #f_i32
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
+; CHECK: mov.w r13, &g_i32+2
+; CHECK: mov.w r12, &g_i32
   %1 = call i32 @f_i32()
   store volatile i32 %1, i32* @g_i32
 
 ; CHECK: call #f_i64
 ; CHECK: mov.w r15, &g_i64+6
 ; CHECK: mov.w r14, &g_i64+4
 ; CHECK: mov.w r13, &g_i64+2
 ; CHECK: mov.w r12, &g_i64
   %2 = call i64 @f_i64()
   store volatile i64 %2, i64* @g_i64
 
   ret void
 }
 
 @g_i16 = common global i16 0, align 2
 @g_i32 = common global i32 0, align 2
 @g_i64 = common global i64 0, align 2
 
 define i16 @f_i16() #0 {
 ; CHECK: f_i16:
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
 ; CHECK: ret
   ret i16 1
 }
 
 define i32 @f_i32() #0 {
 ; CHECK: f_i32:
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
+; CHECK: mov.w #772, r12
+; CHECK: mov.w #258, r13
 ; CHECK: ret
   ret i32 16909060
 }
 
 define i64 @f_i64() #0 {
 ; CHECK: f_i64:
 ; CHECK: mov.w #1800, r12
 ; CHECK: mov.w #1286, r13
 ; CHECK: mov.w #772, r14
 ; CHECK: mov.w #258, r15
 ; CHECK: ret
   ret i64 72623859790382856
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/MSP430/indirectbr2.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i16 @foo(i16 %i) nounwind {
 entry:
   %tmp1 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
   %gotovar.4.0 = load i8*, i8** %tmp1, align 4        ; <i8*> [#uses=1]
-; CHECK: br .LC.0.2070(r12)
+; CHECK: br .LC.0.2070(r13)
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 L5:                                               ; preds = %bb2
   br label %L4
 
 L4:                                               ; preds = %L5, %bb2
   %res.0 = phi i16 [ 385, %L5 ], [ 35, %entry ]     ; <i16> [#uses=1]
   br label %L3

test/CodeGen/MSP430/jumptable.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 target triple = "msp430---elf"
 
 ; Function Attrs: nounwind
 define i16 @test(i16 %i) #0 {
 entry:
 ; CHECK-LABEL: test:
   %retval = alloca i16, align 2
   %i.addr = alloca i16, align 2
   store i16 %i, i16* %i.addr, align 2
   %0 = load i16, i16* %i.addr, align 2
-; CHECK: mov.w #2, r14
+; CHECK: mov.w #2, r13
 ; CHECK: call #__mulhi3hw_noint
-; CHECK: br .LJTI0_0(r15)
+; CHECK: br .LJTI0_0(r12)
   switch i16 %0, label %sw.default [
     i16 0, label %sw.bb
     i16 1, label %sw.bb1
     i16 2, label %sw.bb2
     i16 3, label %sw.bb3
   ]
 
 sw.bb:                                            ; preds = %entry

test/CodeGen/MSP430/memset.ll

 ; RUN: llc < %s | FileCheck %s
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 target triple = "msp430---elf"
 
 @buf = external global i8*
 
 ; Function Attrs: nounwind
 define void @test() nounwind {
 entry:
 ; CHECK-LABEL: test:
   %0 = load i8*, i8** @buf, align 2
-; CHECK: mov.w &buf, r15
-; CHECK-NEXT: mov.w #5, r14
-; CHECK-NEXT: mov.w #128, r13
+; CHECK: mov.w &buf, r12
+; CHECK-NEXT: mov.w #5, r13
+; CHECK-NEXT: mov.w #128, r14
 ; CHECK-NEXT: call #memset
   call void @llvm.memset.p0i8.i16(i8* %0, i8 5, i16 128, i32 1, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind
 declare void @llvm.memset.p0i8.i16(i8* nocapture, i8, i16, i32, i1) nounwind
 

test/CodeGen/MSP430/setcc.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
 define i16 @sccweqand(i16 %a, i16 %b) nounwind {
   %t1 = and i16 %a, %b
   %t2 = icmp eq i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: sccweqand:
-; CHECK:  bit.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  rra.w   r15
-; CHECK:  and.w #1, r15
+; CHECK:  bit.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  rra.w   r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwneand(i16 %a, i16 %b) nounwind {
   %t1 = and i16 %a, %b
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: sccwneand:
-; CHECK:  bit.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  and.w #1, r15
+; CHECK:  bit.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwne(i16 %a, i16 %b) nounwind {
   %t1 = icmp ne i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwne:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w r2, r12
-; CHECK:  rra.w r12
-; CHECK:  mov.w #1, r15
-; CHECK:  bic.w r12, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w r2, r13
+; CHECK:  rra.w r13
+; CHECK:  mov.w #1, r12
+; CHECK:  bic.w r13, r12
 
 define i16 @sccweq(i16 %a, i16 %b) nounwind {
   %t1 = icmp eq i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccweq:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  rra.w r15
-; CHECK:  and.w #1, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  rra.w r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwugt(i16 %a, i16 %b) nounwind {
   %t1 = icmp ugt i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwugt:
-; CHECK:  cmp.w r15, r14
-; CHECK:  mov.w #1, r15
-; CHECK:  bic.w r2, r15
+; CHECK:  cmp.w r12, r13
+; CHECK:  mov.w #1, r12
+; CHECK:  bic.w r2, r12
 
 define i16 @sccwuge(i16 %a, i16 %b) nounwind {
   %t1 = icmp uge i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwuge:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  and.w #1, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwult(i16 %a, i16 %b) nounwind {
   %t1 = icmp ult i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwult:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w #1, r15
-; CHECK:  bic.w r2, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w #1, r12
+; CHECK:  bic.w r2, r12
 
 define i16 @sccwule(i16 %a, i16 %b) nounwind {
   %t1 = icmp ule i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwule:
-; CHECK:  cmp.w r15, r14
-; CHECK:  mov.w r2, r15
-; CHECK:  and.w #1, r15
+; CHECK:  cmp.w r12, r13
+; CHECK:  mov.w r2, r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
   %t1 = icmp sgt i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 
 define i16 @sccwsge(i16 %a, i16 %b) nounwind {

test/CodeGen/MSP430/vararg.ll

; CHECK-NEXT: mov.w [[REG]], 0(r1)
   call void @llvm.va_end(i8* %vl1)
   ret void
 }
 
 define i16 @va_arg(i8* %vl) nounwind {
 entry:
 ; CHECK-LABEL: va_arg:
   %vl.addr = alloca i8*, align 2
-; CHECK: mov.w r15, 0(r1)
+; CHECK: mov.w r12, 0(r1)
   store i8* %vl, i8** %vl.addr, align 2
-; CHECK: mov.w r15, [[REG:r[0-9]+]]
+; CHECK: mov.w r12, [[REG:r[0-9]+]]
 ; CHECK-NEXT: add.w #2, [[REG]]
 ; CHECK-NEXT: mov.w [[REG]], 0(r1)
   %0 = va_arg i8** %vl.addr, i16
-; CHECK-NEXT: mov.w 0(r15), r15
+; CHECK-NEXT: mov.w 0(r12), r12
   ret i16 %0
 }
 
 define void @va_copy(i8* %vl) nounwind {
 entry:
 ; CHECK-LABEL: va_copy:
   %vl.addr = alloca i8*, align 2
   %vl2 = alloca i8*, align 2
-; CHECK: mov.w r15, 2(r1)
+; CHECK: mov.w r12, 2(r1)
   store i8* %vl, i8** %vl.addr, align 2
   %0 = bitcast i8** %vl2 to i8*
   %1 = bitcast i8** %vl.addr to i8*
-; CHECK-NEXT: mov.w r15, 0(r1)
+; CHECK-NEXT: mov.w r12, 0(r1)
   call void @llvm.va_copy(i8* %0, i8* %1)
   ret void
 }