Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp +++ lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -669,30 +669,26 @@ MO.isBlockAddress()) && "Invalid operand for ADDIStocHA!"); MCSymbol *MOSymbol = nullptr; - bool IsExternal = false; - bool IsNonLocalFunction = false; - bool IsCommon = false; - bool IsAvailExt = false; + bool GlobalToc = false; if (MO.isGlobal()) { const GlobalValue *GV = MO.getGlobal(); MOSymbol = getSymbol(GV); - IsExternal = GV->isDeclaration(); - IsCommon = GV->hasCommonLinkage(); - IsNonLocalFunction = GV->getType()->getElementType()->isFunctionTy() && - !GV->isStrongDefinitionForLinker(); - IsAvailExt = GV->hasAvailableExternallyLinkage(); - } else if (MO.isCPI()) + unsigned char gv_flags = Subtarget->ClassifyGlobalReference(GV); + GlobalToc = ((gv_flags & PPCII::MO_NLP_FLAG) || + (gv_flags & PPCII::MO_NLP_HIDDEN_FLAG)); + } else if (MO.isCPI()) { MOSymbol = GetCPISymbol(MO.getIndex()); - else if (MO.isJTI()) + } else if (MO.isJTI()) { MOSymbol = GetJTISymbol(MO.getIndex()); - else if (MO.isBlockAddress()) + } else if (MO.isBlockAddress()) { MOSymbol = GetBlockAddressSymbol(MO.getBlockAddress()); + } - if (IsExternal || IsNonLocalFunction || IsCommon || IsAvailExt || - MO.isJTI() || MO.isBlockAddress() || - TM.getCodeModel() == CodeModel::Large) + if (GlobalToc || MO.isJTI() || MO.isBlockAddress() || + TM.getCodeModel() == CodeModel::Large) { MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); + } const MCExpr *Exp = MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_HA, @@ -727,13 +723,15 @@ MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); } else if (MO.isGlobal()) { - const GlobalValue *GValue = MO.getGlobal(); - MOSymbol = getSymbol(GValue); - if (GValue->getType()->getElementType()->isFunctionTy() || - GValue->isDeclaration() || GValue->hasCommonLinkage() || - GValue->hasAvailableExternallyLinkage() || - TM.getCodeModel() == CodeModel::Large) - MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); + const GlobalValue *GV = MO.getGlobal(); + MOSymbol = getSymbol(GV); + DEBUG( + unsigned char gv_flags = Subtarget->ClassifyGlobalReference(GV); + assert(((gv_flags & PPCII::MO_NLP_FLAG) || + (gv_flags & PPCII::MO_NLP_HIDDEN_FLAG)) && + "LDtocL used on symbol that could be accessed directly is " + "invalid. Must match ADDIStocHA.")); + MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); } const MCExpr *Exp = @@ -754,21 +752,19 @@ const MachineOperand &MO = MI->getOperand(2); assert((MO.isGlobal() || MO.isCPI()) && "Invalid operand for ADDItocL"); MCSymbol *MOSymbol = nullptr; - bool IsExternal = false; - bool IsNonLocalFunction = false; if (MO.isGlobal()) { const GlobalValue *GV = MO.getGlobal(); + DEBUG( + unsigned char gv_flags = Subtarget->ClassifyGlobalReference(GV); + assert ( + !(gv_flags & PPCII::MO_NLP_FLAG) && + !(gv_flags & PPCII::MO_NLP_HIDDEN_FLAG) && + "Interposable definitions must use indirect access.")); MOSymbol = getSymbol(GV); - IsExternal = GV->isDeclaration(); - IsNonLocalFunction = GV->getType()->getElementType()->isFunctionTy() && - !GV->isStrongDefinitionForLinker(); - } else if (MO.isCPI()) + } else if (MO.isCPI()) { MOSymbol = GetCPISymbol(MO.getIndex()); - - if (IsNonLocalFunction || IsExternal || - TM.getCodeModel() == CodeModel::Large) - MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); + } const MCExpr *Exp = MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO, Index: lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- lib/Target/PowerPC/PPCFastISel.cpp +++ lib/Target/PowerPC/PPCFastISel.cpp @@ -1972,19 +1972,16 @@ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA), HighPartReg).addReg(PPC::X2).addGlobalAddress(GV); - // If/when switches are implemented, jump tables should be handled - // on the "if" path here. - if (CModel == CodeModel::Large || - (GV->getType()->getElementType()->isFunctionTy() && - !GV->isStrongDefinitionForLinker()) || - GV->isDeclaration() || GV->hasCommonLinkage() || - GV->hasAvailableExternallyLinkage()) + unsigned char gv_flags = PPCSubTarget->ClassifyGlobalReference(GV); + if ((gv_flags & PPCII::MO_NLP_FLAG) || + (gv_flags & PPCII::MO_NLP_HIDDEN_FLAG)) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL), DestReg).addGlobalAddress(GV).addReg(HighPartReg); - else + } else { // Otherwise generate the ADDItocL. BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL), DestReg).addReg(HighPartReg).addGlobalAddress(GV); + } } return DestReg; Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2902,9 +2902,7 @@ break; // The first source operand is a TargetGlobalAddress or a TargetJumpTable. - // If it is an externally defined symbol, a symbol with common linkage, - // a non-local function address, or a jump table address, or if we are - // generating code for large code model, we generate: + // If it must be toc-referenced according to PPCSubTarget, we generate: // LDtocL(, ADDIStocHA(%X2, )) // Otherwise we generate: // ADDItocL(ADDIStocHA(%X2, ), ) @@ -2919,13 +2917,13 @@ MVT::i64, GA, SDValue(Tmp, 0))); if (GlobalAddressSDNode *G = dyn_cast(GA)) { - const GlobalValue *GValue = G->getGlobal(); - if ((GValue->getType()->getElementType()->isFunctionTy() && - !GValue->isStrongDefinitionForLinker()) || - GValue->isDeclaration() || GValue->hasCommonLinkage() || - GValue->hasAvailableExternallyLinkage()) + const GlobalValue *GV = G->getGlobal(); + unsigned char gv_flags = PPCSubTarget->ClassifyGlobalReference(GV); + if ((gv_flags & PPCII::MO_NLP_FLAG) || + (gv_flags & PPCII::MO_NLP_HIDDEN_FLAG)) { return transferMemOperands(N, CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, SDValue(Tmp, 0))); + } } return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64, Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -285,6 +285,10 @@ bool useAA() const override; bool enableSubRegLiveness() const override; + + /// ClassifyGlobalReference - Classify a global variable reference for the + /// current subtarget accourding to how we should reference it. + unsigned char ClassifyGlobalReference(const GlobalValue *GV) const; }; } // End llvm namespace Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -210,5 +210,32 @@ return UseSubRegLiveness; } +unsigned char PPCSubtarget::ClassifyGlobalReference( + const GlobalValue *GV) const { + + // Large model always uses a non local pointer and is pic. + if (TM.getCodeModel() == CodeModel::Large) + return PPCII::MO_NLP_FLAG | PPCII::MO_PIC_FLAG; + + // Except for large code model, static relocation is always direct. + if (TM.getRelocationModel() == Reloc::Static) + return PPCII::MO_NO_FLAG; + + unsigned char flags = PPCII::MO_NO_FLAG; + if (TM.getRelocationModel() == Reloc::PIC_) { + flags |= PPCII::MO_PIC_FLAG; + } + + if (!GV->hasLocalLinkage()) { + if (GV->hasHiddenVisibility()) { + flags |= PPCII::MO_NLP_HIDDEN_FLAG; + return flags; + } + flags |= PPCII::MO_NLP_FLAG; + return flags; + } + return flags; +} + bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } Index: test/CodeGen/PowerPC/extra-toc-reg-deps.ll =================================================================== --- test/CodeGen/PowerPC/extra-toc-reg-deps.ll +++ test/CodeGen/PowerPC/extra-toc-reg-deps.ll @@ -67,17 +67,17 @@ ; CHECK-LABEL: @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb -; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha +; CHECK: addis [[REG1:[0-9]+]], 2, _ZN4Foam4PoutE@toc@ha ; CHECK: std 2, 40(1) -; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]]) +; CHECK: addi {{[0-9]+}}, [[REG1]], _ZN4Foam4PoutE@toc@l ; CHECK: {{mr|ld}} 2, ; CHECK: mtctr ; CHECK: bctrl ; CHECK: ld 2, 40(1) -; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha +; CHECK: addis [[REG1:[0-9]+]], 2, _ZN4Foam4PoutE@toc@ha ; CHECK: std 2, 40(1) -; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]]) +; CHECK: addi {{[0-9]+}}, [[REG1]], _ZN4Foam4PoutE@toc@l ; CHECK: {{mr|ld}} 2, ; CHECK: mtctr ; CHECK: bctrl Index: test/CodeGen/PowerPC/fast-isel-load-store.ll =================================================================== --- test/CodeGen/PowerPC/fast-isel-load-store.ll +++ test/CodeGen/PowerPC/fast-isel-load-store.ll @@ -196,7 +196,7 @@ %1 = add nsw i64 %v, 1 store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8 ; ELF64: addis -; ELF64: ld +; ELF64: addi ; ELF64: addi ; ELF64: lis ; ELF64: ori Index: test/CodeGen/PowerPC/ldtoc-inv.ll =================================================================== --- test/CodeGen/PowerPC/ldtoc-inv.ll +++ test/CodeGen/PowerPC/ldtoc-inv.ll @@ -1,4 +1,5 @@ -; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -code-model=large < %s | FileCheck %s +; large code model necessary for the toc load to exist at all. target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" Index: test/CodeGen/PowerPC/mcm-1.ll =================================================================== --- test/CodeGen/PowerPC/mcm-1.ll +++ test/CodeGen/PowerPC/mcm-1.ll @@ -1,9 +1,15 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s + ; Test correct code generation for medium and large code model ; for loading and storing an external variable. +; Note that large code model generates the same code in static +; or pic mode, so the prefix PIC for large/static above is correct. + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -18,10 +24,12 @@ } ; CHECK-LABEL: test_external: -; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha -; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; PIC: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; STATIC: addis [[REG1:[0-9]+]], 2, ei@toc@ha +; PIC: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; STATIC: addi [[REG2:[0-9]+]], [[REG1]], ei@toc@l ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) ; CHECK: stw {{[0-9]+}}, 0([[REG2]]) -; CHECK: .section .toc -; CHECK: .LC[[TOCNUM]]: -; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} +; PIC: .section .toc +; PIC: .LC[[TOCNUM]]: +; PIC: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} Index: test/CodeGen/PowerPC/mcm-6.ll =================================================================== --- test/CodeGen/PowerPC/mcm-6.ll +++ test/CodeGen/PowerPC/mcm-6.ll @@ -1,9 +1,16 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s + ; Test correct code generation for medium and large code model ; for loading and storing a tentatively defined variable. +; Note that large code model generates the same code in static +; or pic mode, so the prefix PIC for large/static above is correct. + + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -18,11 +25,13 @@ } ; CHECK-LABEL: test_tentative: -; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha -; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; PIC: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; STATIC: addis [[REG1:[0-9]+]], 2, ti@toc@ha +; PIC: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; STATIC: addi [[REG2:[0-9]+]], [[REG1]], ti@toc@l ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) ; CHECK: stw {{[0-9]+}}, 0([[REG2]]) -; CHECK: .section .toc -; CHECK: .LC[[TOCNUM]]: -; CHECK: .tc [[VAR:[a-z0-9A-Z_.]+]][TC],{{[a-z0-9A-Z_.]+}} -; CHECK: .comm [[VAR]],4,4 +; PIC: .section .toc +; PIC: .LC[[TOCNUM]]: +; PIC: .tc ti[TC],{{[a-z0-9A-Z_.]+}} +; CHECK: .comm ti,4,4 Index: test/CodeGen/PowerPC/mcm-7.ll =================================================================== --- test/CodeGen/PowerPC/mcm-7.ll +++ test/CodeGen/PowerPC/mcm-7.ll @@ -1,9 +1,16 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s + ; Test correct code generation for medium and large code model ; for loading a function address. +; Note that large code model generates the same code in static +; or pic mode, so the prefix PIC for large/static above is correct. + + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -19,8 +26,10 @@ declare signext i32 @foo(i32 signext) ; CHECK-LABEL: test_fnaddr: -; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha -; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) -; CHECK: .section .toc -; CHECK: .LC[[TOCNUM]]: -; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} +; PIC: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; STATIC: addis [[REG1:[0-9]+]], 2, foo@toc@ha +; PIC: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; STATIC: addi [[REG2:[0-9]+]], [[REG1]], foo@toc@l +; PIC: .section .toc +; PIC: .LC[[TOCNUM]]: +; PIC: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} Index: test/CodeGen/PowerPC/mcm-8.ll =================================================================== --- test/CodeGen/PowerPC/mcm-8.ll +++ test/CodeGen/PowerPC/mcm-8.ll @@ -1,9 +1,15 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s + ; Test correct code generation for medium and large code model ; for loading a variable with available-externally linkage. +; Note that large code model generates the same code in static +; or pic mode, so the prefix PIC for large/static above is correct. + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -17,9 +23,11 @@ } ; CHECK-LABEL: test_avext: -; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha -; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; PIC: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; STATIC: addis [[REG1:[0-9]+]], 2, x@toc@ha +; PIC: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; STATIC: addi [[REG2:[0-9]+]], [[REG1]], x@toc@l ; CHECK: lbz {{[0-9]+}}, 0([[REG2]]) -; CHECK: .section .toc -; CHECK: .LC[[TOCNUM]]: -; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} +; PIC: .section .toc +; PIC: .LC[[TOCNUM]]: +; PIC: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} Index: test/CodeGen/PowerPC/mcm-9.ll =================================================================== --- test/CodeGen/PowerPC/mcm-9.ll +++ test/CodeGen/PowerPC/mcm-9.ll @@ -1,9 +1,14 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s ; Test correct code generation for medium and large code model ; for loading and storing an aliased external variable. +; Note that large code model generates the same code in static +; or pic mode, so the prefix PIC for large/static above is correct. + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -18,10 +23,12 @@ } ; CHECK-LABEL: test_external: -; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha -; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; PIC: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; STATIC: addis [[REG1:[0-9]+]], 2, a@toc@ha +; PIC: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; STATIC: addi [[REG2:[0-9]+]], [[REG1]], a@toc@l ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) ; CHECK: stw {{[0-9]+}}, 0([[REG2]]) -; CHECK: .section .toc -; CHECK: .LC[[TOCNUM]]: -; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} +; PIC: .section .toc +; PIC: .LC[[TOCNUM]]: +; PIC: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} Index: test/CodeGen/PowerPC/mcm-default.ll =================================================================== --- test/CodeGen/PowerPC/mcm-default.ll +++ test/CodeGen/PowerPC/mcm-default.ll @@ -1,4 +1,5 @@ -; RUN: llc -mcpu=pwr7 -O0 <%s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 --relocation-model=pic <%s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s +; RUN: llc -mcpu=pwr7 -O0 --relocation-model=static <%s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s ; Test that we generate code for the medium model as the default. ; Use an external variable reference as an example. @@ -17,10 +18,12 @@ } ; CHECK-LABEL: test_external: -; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha -; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; PIC: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; STATIC: addis [[REG1:[0-9]+]], 2, ei@toc@ha +; PIC: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; STATIC: addi [[REG2:[0-9]+]], [[REG1]], ei@toc@l ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) ; CHECK: stw {{[0-9]+}}, 0([[REG2]]) -; CHECK: .section .toc -; CHECK: .LC[[TOCNUM]]: -; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} +; PIC: .section .toc +; PIC: .LC[[TOCNUM]]: +; PIC: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} Index: test/CodeGen/PowerPC/mcm-obj.ll =================================================================== --- test/CodeGen/PowerPC/mcm-obj.ll +++ test/CodeGen/PowerPC/mcm-obj.ll @@ -1,12 +1,12 @@ -; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \ +; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -relocation-model=pic -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \ +; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -relocation-model=pic -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s ; Run jump table test separately since jump tables aren't generated at -O0. -; RUN: llc -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \ +; RUN: llc -mcpu=pwr7 -code-model=medium -filetype=obj -relocation-model=pic -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM-JT %s -; RUN: llc -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \ +; RUN: llc -mcpu=pwr7 -code-model=large -filetype=obj -relocation-model=pic -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE-JT %s ; FIXME: When asm-parse is available, could make this an assembly test. @@ -29,13 +29,13 @@ ; ; MEDIUM: Relocations [ ; MEDIUM: Section {{.*}} .rela.text { -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc [[SYM1:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc [[SYM1]] ; ; LARGE: Relocations [ ; LARGE: Section {{.*}} .rela.text { -; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] -; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc [[SYM1:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc [[SYM1]] @test_fn_static.si = internal global i32 0, align 4 @@ -50,14 +50,14 @@ ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing function-scoped variable si. ; -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .bss [[SYM2:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO .bss [[SYM2]] ; ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing function-scoped variable si. ; -; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] -; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc [[SYM2:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc [[SYM2]] @gi = global i32 5, align 4 @@ -72,14 +72,14 @@ ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing file-scope variable gi. ; -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]] -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc [[SYM3:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc [[SYM3]] ; ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing file-scope variable gi. ; -; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]] -; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc [[SYM3:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc [[SYM3]] define double @test_double_const() nounwind { entry: Index: test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll =================================================================== --- test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -89,9 +89,9 @@ %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0 %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer ret <2 x double> %splat.splat -; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l +; CHECK: addi [[REG1:[0-9]+]], {{[0-9]+}}, d@toc@l ; CHECK: lxvdsx 34, 0, [[REG1]] -; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l +; CHECK-LE: addi [[REG1:[0-9]+]], {{[0-9]+}}, d@toc@l ; CHECK-LE: lxvdsx 34, 0, [[REG1]] } Index: test/CodeGen/PowerPC/ppc64-i128-abi.ll =================================================================== --- test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -223,20 +223,26 @@ ret i128 %ret ; %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2) ; CHECK-LE-LABEL: @call_i128_increment_by_one -; CHECK-LE-DAG: ld 3, 0([[BASEREG:[0-9]+]]) -; CHECK-LE-DAG: ld 4, 8([[BASEREG]]) +; CHECK-LE-DAG: addis [[REG1:[0-9]+]], 2, a@toc@ha +; CHECK-LE-DAG: addi [[REG2:[0-9]+]], [[REG1]], a@toc@l +; CHECK-LE-DAG: ld 3, a@toc@l([[REG1]]) +; CHECK-LE-DAG: ld 4, 8([[REG2]]) ; CHECK-LE: bl i128_increment_by_one ; CHECK-LE: blr ; CHECK-BE-LABEL: @call_i128_increment_by_one -; CHECK-BE-DAG: ld 3, 0([[BASEREG:[0-9]+]]) -; CHECK-BE-DAG: ld 4, 8([[BASEREG]]) +; CHECK-BE-DAG: addis [[REG1:[0-9]+]], 2, a@toc@ha +; CHECK-BE-DAG: addi [[REG2:[0-9]+]], [[REG1]], a@toc@l +; CHECK-BE-DAG: ld 3, a@toc@l([[REG1]]) +; CHECK-BE-DAG: ld 4, 8([[REG2]]) ; CHECK-BE: bl i128_increment_by_one ; CHECK-BE: blr ; CHECK-NOVSX-LABEL: @call_i128_increment_by_one -; CHECK-NOVSX-DAG: ld 3, 0([[BASEREG:[0-9]+]]) -; CHECK-NOVSX-DAG: ld 4, 8([[BASEREG]]) +; CHECK-NOVSX-DAG: addis [[REG1:[0-9]+]], 2, a@toc@ha +; CHECK-NOVSX-DAG: addi [[REG2:[0-9]+]], [[REG1]], a@toc@l +; CHECK-NOVSX-DAG: ld 3, a@toc@l([[REG1]]) +; CHECK-NOVSX-DAG: ld 4, 8([[REG2]]) ; CHECK-NOVSX: bl i128_increment_by_one ; CHECK-NOVSX: blr } @@ -247,26 +253,38 @@ %ret = call i128 @i128_increment_by_val(i128 %tmp, i128 %tmp2) ret i128 %ret ; CHECK-LE-LABEL: @call_i128_increment_by_val -; CHECK-LE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]]) -; CHECK-LE-DAG: ld 4, 8([[P1BASEREG]]) -; CHECK-LE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]]) -; CHECK-LE-DAG: ld 6, 8([[P2BASEREG]]) +; CHECK-LE-DAG: addis [[P1REG1:[0-9]+]], 2, a@toc@ha +; CHECK-LE-DAG: addi [[P1REG2:[0-9]+]], [[P1REG1]], a@toc@l +; CHECK-LE-DAG: addis [[P2REG1:[0-9]+]], 2, b@toc@ha +; CHECK-LE-DAG: addi [[P2REG2:[0-9]+]], [[P2REG1]], b@toc@l +; CHECK-LE-DAG: ld 3, a@toc@l([[P1REG1]]) +; CHECK-LE-DAG: ld 4, 8([[P1REG2]]) +; CHECK-LE-DAG: ld 5, b@toc@l([[P2REG1]]) +; CHECK-LE-DAG: ld 6, 8([[P2REG2]]) ; CHECK-LE: bl i128_increment_by_val ; CHECK-LE: blr ; CHECK-BE-LABEL: @call_i128_increment_by_val -; CHECK-BE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]]) -; CHECK-BE-DAG: ld 4, 8([[P1BASEREG]]) -; CHECK-BE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]]) -; CHECK-BE-DAG: ld 6, 8([[P2BASEREG]]) +; CHECK-BE-DAG: addis [[P1REG1:[0-9]+]], 2, a@toc@ha +; CHECK-BE-DAG: addi [[P1REG2:[0-9]+]], [[P1REG1]], a@toc@l +; CHECK-BE-DAG: addis [[P2REG1:[0-9]+]], 2, b@toc@ha +; CHECK-BE-DAG: addi [[P2REG2:[0-9]+]], [[P2REG1]], b@toc@l +; CHECK-BE-DAG: ld 3, a@toc@l([[P1REG1]]) +; CHECK-BE-DAG: ld 4, 8([[P1REG2]]) +; CHECK-BE-DAG: ld 5, b@toc@l([[P2REG1]]) +; CHECK-BE-DAG: ld 6, 8([[P2REG2]]) ; CHECK-BE: bl i128_increment_by_val ; CHECK-BE: blr ; CHECK-NOVSX-LABEL: @call_i128_increment_by_val -; CHECK-NOVSX-DAG: ld 3, 0([[P1BASEREG:[0-9]+]]) -; CHECK-NOVSX-DAG: ld 4, 8([[P1BASEREG]]) -; CHECK-NOVSX-DAG: ld 5, 0([[P2BASEREG:[0-9]+]]) -; CHECK-NOVSX-DAG: ld 6, 8([[P2BASEREG]]) +; CHECK-NOVSX-DAG: addis [[P1REG1:[0-9]+]], 2, a@toc@ha +; CHECK-NOVSX-DAG: addi [[P1REG2:[0-9]+]], [[P1REG1]], a@toc@l +; CHECK-NOVSX-DAG: addis [[P2REG1:[0-9]+]], 2, b@toc@ha +; CHECK-NOVSX-DAG: addi [[P2REG2:[0-9]+]], [[P2REG1]], b@toc@l +; CHECK-NOVSX-DAG: ld 3, a@toc@l([[P1REG1]]) +; CHECK-NOVSX-DAG: ld 4, 8([[P1REG2]]) +; CHECK-NOVSX-DAG: ld 5, b@toc@l([[P2REG1]]) +; CHECK-NOVSX-DAG: ld 6, 8([[P2REG2]]) ; CHECK-NOVSX: bl i128_increment_by_val ; CHECK-NOVSX: blr } Index: test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll =================================================================== --- test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll +++ test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll @@ -1,4 +1,5 @@ -; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -relocation-model=static < %s | FileCheck --check-prefix=CHECK --check-prefix=STATIC %s +; RUN: llc -mcpu=pwr7 -relocation-model=pic < %s | FileCheck --check-prefix=CHECK --check-prefix=PIC %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -15,9 +16,11 @@ ret void ; CHECK-LABEL: @foo -; CHECK-DAG: addis [[REG1:[0-9]+]], 2, something@toc@ha +; PIC-DAG: addis [[REG1:[0-9]+]], 2, [[NAME:[._A-Za-z0-9]+]]@toc@ha +; PIC-DAG: ld [[REG3:[0-9]+]], [[NAME]]@toc@l([[REG1]]) +; STATIC-DAG: addis [[REG1:[0-9]+]], 2, something@toc@ha +; STATIC-DAG: addi [[REG3:[0-9]+]], [[REG1]], something@toc@l ; CHECK-DAG: std 2, 40(1) -; CHECK-DAG: addi [[REG3:[0-9]+]], [[REG1]], something@toc@l ; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) ; CHECK-DAG: ld 11, 16([[REG3]]) ; CHECK-DAG: ld 2, 8([[REG3]]) @@ -34,10 +37,14 @@ ret void ; CHECK-LABEL: @bar -; CHECK-DAG: addis [[REG1:[0-9]+]], 13, tls_something@tprel@ha +; STATIC-DAG: addis [[REG1:[0-9]+]], 13, tls_something@tprel@ha +; STATIC-DAG: addi [[REG3:[0-9]+]], [[REG1]], tls_something@tprel@l +; PIC-DAG: addis [[REG1:[0-9]+]], 2, tls_something@got@tlsgd@ha +; PIC-DAG: addi 3, [[REG1]], tls_something@got@tlsgd@l ; CHECK-DAG: std 2, 40(1) -; CHECK-DAG: addi [[REG3:[0-9]+]], [[REG1]], tls_something@tprel@l -; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) +; PIC: bl __tls_get_addr(tls_something@tlsgd) +; STATIC-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) +; PIC-DAG: ld [[REG2:[0-9]+]], 0(3) ; CHECK-DAG: ld 11, 16([[REG3]]) ; CHECK-DAG: ld 2, 8([[REG3]]) ; CHECK-DAG: mtctr [[REG2]] @@ -53,9 +60,11 @@ ret void ; CHECK-LABEL: @ext -; CHECK-DAG: addis [[REG1:[0-9]+]], 2, [[NAME:[._A-Za-z0-9]+]]@toc@ha +; PIC-DAG: addis [[REG1:[0-9]+]], 2, [[NAME:[._A-Za-z0-9]+]]@toc@ha +; PIC-DAG: ld [[REG3:[0-9]+]], [[NAME]]@toc@l([[REG1]]) +; STATIC-DAG: addis [[REG1:[0-9]+]], 2, extern_something@toc@ha +; STATIC-DAG: addi [[REG3:[0-9]+]], [[REG1]], extern_something@toc@l ; CHECK-DAG: std 2, 40(1) -; CHECK-DAG: ld [[REG3:[0-9]+]], [[NAME]]@toc@l(3) ; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) ; CHECK-DAG: ld 11, 16([[REG3]]) ; CHECK-DAG: ld 2, 8([[REG3]]) Index: test/CodeGen/PowerPC/ppc64le-aggregates.ll =================================================================== --- test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -264,24 +264,29 @@ ret void } ; CHECK-LABEL: @caller2 -; CHECK: ld {{[0-9]+}}, .LC -; CHECK-DAG: lfs 1, 0({{[0-9]+}}) -; CHECK-DAG: lfs 2, 4({{[0-9]+}}) -; CHECK-DAG: lfs 3, 8({{[0-9]+}}) -; CHECK-DAG: lfs 4, 12({{[0-9]+}}) -; CHECK-DAG: lfs 5, 16({{[0-9]+}}) -; CHECK-DAG: lfs 6, 20({{[0-9]+}}) -; CHECK-DAG: lfs 7, 24({{[0-9]+}}) -; CHECK-DAG: lfs 8, 28({{[0-9]+}}) - -; CHECK-DAG: lfs 9, 0({{[0-9]+}}) -; CHECK-DAG: lfs 10, 4({{[0-9]+}}) -; CHECK-DAG: lfs 11, 8({{[0-9]+}}) -; CHECK-DAG: lfs 12, 12({{[0-9]+}}) -; CHECK-DAG: lfs 13, 16({{[0-9]+}}) - -; CHECK-DAG: lwz [[REG0:[0-9]+]], 0({{[0-9]+}}) -; CHECK-DAG: lwz [[REG1:[0-9]+]], 4({{[0-9]+}}) +; CHECK-DAG: addis [[R2_1:[0-9]+]], 2, g2@toc@ha +; CHECK-DAG: addis [[R5_1:[0-9]+]], 2, g5@toc@ha +; CHECK-DAG: addis [[R8_1:[0-9]+]], 2, g8@toc@ha +; CHECK-DAG: addi [[R2_2:[0-9]+]], [[R2_1]], g2@toc@l +; CHECK-DAG: addi [[R5_2:[0-9]+]], [[R5_1]], g5@toc@l +; CHECK-DAG: addi [[R8_2:[0-9]+]], [[R8_1]], g8@toc@l +; CHECK-DAG: lfs 1, g8@toc@l([[R8_1]]) +; CHECK-DAG: lfs 2, 4([[R8_2]]) +; CHECK-DAG: lfs 3, 8([[R8_2]]) +; CHECK-DAG: lfs 4, 12([[R8_2]]) +; CHECK-DAG: lfs 5, 16([[R8_2]]) +; CHECK-DAG: lfs 6, 20([[R8_2]]) +; CHECK-DAG: lfs 7, 24([[R8_2]]) +; CHECK-DAG: lfs 8, 28([[R8_2]]) + +; CHECK-DAG: lfs 9, g5@toc@l([[R5_1]]) +; CHECK-DAG: lfs 10, 4([[R5_2]]) +; CHECK-DAG: lfs 11, 8([[R5_2]]) +; CHECK-DAG: lfs 12, 12([[R5_2]]) +; CHECK-DAG: lfs 13, 16([[R5_2]]) + +; CHECK-DAG: lwz [[REG0:[0-9]+]], g2@toc@l([[R2_1]]) +; CHECK-DAG: lwz [[REG1:[0-9]+]], 4([[R2_2]]) ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 32 ; CHECK-DAG: or 10, [[REG0]], [[REG2]] ; CHECK: bl test2 Index: test/CodeGen/PowerPC/ppcf128-endian.ll =================================================================== --- test/CodeGen/PowerPC/ppcf128-endian.ll +++ test/CodeGen/PowerPC/ppcf128-endian.ll @@ -14,9 +14,10 @@ ret void } ; CHECK: @callee -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK: stfd 2, 8([[REG]]) -; CHECK: stfd 1, 0([[REG]]) +; CHECK: addis [[REG1:[0-9]+]], 2, g@toc@ha +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], g@toc@l +; CHECK-DAG: stfd 1, g@toc@l([[REG1]]) +; CHECK-DAG: stfd 2, 8([[REG2]]) ; CHECK: blr define void @caller() { @@ -26,9 +27,10 @@ ret void } ; CHECK: @caller -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK: lfd 2, 8([[REG]]) -; CHECK: lfd 1, 0([[REG]]) +; CHECK: addis [[REG1:[0-9]+]], 2, g@toc@ha +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], g@toc@l +; CHECK-DAG: lfd 1, g@toc@l([[REG1]]) +; CHECK-DAG: lfd 2, 8([[REG2]]) ; CHECK: bl test declare void @test(ppc_fp128) @@ -55,9 +57,10 @@ ret ppc_fp128 %0 } ; CHECK: @result -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK: lfd 1, 0([[REG]]) -; CHECK: lfd 2, 8([[REG]]) +; CHECK: addis [[REG1:[0-9]+]], 2, g@toc@ha +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], g@toc@l +; CHECK-DAG: lfd 1, g@toc@l([[REG1]]) +; CHECK-DAG: lfd 2, 8([[REG2]]) ; CHECK: blr define void @use_result() { @@ -68,9 +71,10 @@ } ; CHECK: @use_result ; CHECK: bl test_result -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK: stfd 2, 8([[REG]]) -; CHECK: stfd 1, 0([[REG]]) +; CHECK: addis [[REG1:[0-9]+]], 2, g@toc@ha +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], g@toc@l +; CHECK-DAG: stfd 1, g@toc@l([[REG1]]) +; CHECK-DAG: stfd 2, 8([[REG2]]) ; CHECK: blr declare ppc_fp128 @test_result()