[llvm][SelectionDAGBuilder] change callbr.landingpad intrinsic to accept explicit param

[nickdesaulniers]

Summary

This simplifies code in SelectionDAGBuilder. Originally, this intrinsic
was designed to have an implicit operand, based on
https://gist.github.com/nickdesaulniers/6df8e1a15f23636e2bf8abec96d425c7.

Turns out, codegen is simpler to just have an explicit parameter. Make
what was the implicit corresponding CallBrInst explicit and simplify
codegen.

[efriedma]

LGTM

[nickdesaulniers]

• rebase, format

[void]

LGTM

[nickdesaulniers]

Squashed relevant pieces into https://reviews.llvm.org/D139883, https://reviews.llvm.org/D139970, and https://reviews.llvm.org/D140160.

llvm/include/llvm/IR/Intrinsics.td

def int_instrprof_value_profile : Intrinsic<[],
                                              llvm_i32_ty]>;
 
 def int_call_preallocated_setup : DefaultAttrsIntrinsic<[llvm_token_ty], [llvm_i32_ty]>;
 def int_call_preallocated_arg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_token_ty, llvm_i32_ty]>;
 def int_call_preallocated_teardown : DefaultAttrsIntrinsic<[], [llvm_token_ty]>;
 
 // This intrinsic is intentionally undocumented and users shouldn't call it;
 // it's produced then quickly consumed during codegen.
-def int_callbr_landingpad : Intrinsic<[llvm_any_ty], [], [IntrNoMerge]>;
+def int_callbr_landingpad : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>],
+                                      [IntrNoMerge]>;
 
 //===------------------- Standard C Library Intrinsics --------------------===//
 //
 
 def int_memcpy  : Intrinsic<[],
                             [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
                              llvm_i1_ty],
                             [IntrArgMemOnly, IntrWillReturn, IntrNoFree,

llvm/lib/CodeGen/CallBrPrepare.cpp

 #include "llvm/ADT/iterator.h"
 #include "llvm/Analysis/CFG.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
 #include "llvm/Transforms/Utils/SSAUpdater.h"
 
 using namespace llvm;
 
for (CallBrInst *CBR : CBRs) {
     SSAUpdate.AddAvailableValue(CBR->getParent(), CBR);
     SSAUpdate.AddAvailableValue(CBR->getDefaultDest(), CBR);
 
     for (BasicBlock *IndDest : CBR->getIndirectDests()) {
       if (!Visited.insert(IndDest).second)
         continue;
       Builder.SetInsertPoint(&*IndDest->begin());
       CallInst *Intrinsic = Builder.CreateIntrinsic(
-          CBR->getType(), llvm::Intrinsic::callbr_landingpad, {});
+          CBR->getType(), Intrinsic::callbr_landingpad, {CBR});
       SSAUpdate.AddAvailableValue(IndDest, Intrinsic);
       UpdateSSA(DT, CBR, Intrinsic, SSAUpdate);
       Changed = true;
     }
   }
   return Changed;
 }
 
for (Use *U : Uses) {
     if (!Visited.insert(U).second)
       continue;
 
 #ifndef NDEBUG
     PrintDebugDomInfo(DT, *U, LandingPad, /*IsDefaultDest*/ false);
     PrintDebugDomInfo(DT, *U, DefaultDest, /*IsDefaultDest*/ true);
 #endif
 
+    // Don't rewrite the use in the newly inserted intrinsic.
+    if (const auto *II = dyn_cast<IntrinsicInst>(U->getUser()))
+      if (II->getIntrinsicID() == Intrinsic::callbr_landingpad)
+        continue;
+
     // If the Use is in the same BasicBlock as the Intrinsic call, replace
     // the Use with the value of the Intrinsic call.
     if (IsInSameBasicBlock(*U, LandingPad)) {
       U->set(Intrinsic);
       continue;
     }
 
     // If the Use is dominated by the default dest, do not touch it.

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/CodeGen/WasmEHFuncInfo.h"
 #include "llvm/CodeGen/WinEHFuncInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Instructions.h"
-#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 using namespace llvm;
 
 #define DEBUG_TYPE "function-lowering-info"
 
-static bool isUsedOutsideOfDefiningBlock(const CallBrInst *CBR) {
-  return llvm::any_of(CBR->getIndirectDests(), [](BasicBlock *Dest) {
-    if (const auto *CI = dyn_cast<CallInst>(Dest->begin())) {
-      if (Function *F = CI->getCalledFunction()) {
-        return F->getIntrinsicID() == Intrinsic::callbr_landingpad;
-      }
-    }
-    return false;
-  });
-}
-
 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
 /// PHI nodes or outside of the basic block that defines it, or used by a
 /// switch or atomic instruction, which may expand to multiple basic blocks.
 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
-  if (I->use_empty()) {
-    if (const auto *CBR = dyn_cast<CallBrInst>(I))
-      return isUsedOutsideOfDefiningBlock(CBR);
+  if (I->use_empty())
     return false;
-  }
   if (isa<PHINode>(I)) return true;
   const BasicBlock *BB = I->getParent();
   for (const User *U : I->users())
     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
       return true;
 
   return false;
 }

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 /// registers.
 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
   // Skip empty types
   if (V->getType()->isEmptyTy())
     return;
 
   DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(V);
   if (VMI != FuncInfo.ValueMap.end()) {
-    assert((!V->use_empty() || isa<CallBrInst>(V)) &&
-           "Unused value assigned virtual registers!");
+    assert(!V->use_empty() && "Unused value assigned virtual registers!");
     CopyValueToVirtualRegister(V, VMI->second);
   }
 }
 
 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
 /// the current basic block, add it to ValueMap now so that we'll get a
 /// CopyTo/FromReg.
 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {

llvm/lib/IR/Verifier.cpp

Check(cast<ConstantInt>(Call.getArgOperand(2))->getZExtValue() < 4,
           "target argument to llvm.aarch64.prefetch must be 0-3", Call);
     Check(cast<ConstantInt>(Call.getArgOperand(3))->getZExtValue() < 2,
           "stream argument to llvm.aarch64.prefetch must be 0 or 1", Call);
     Check(cast<ConstantInt>(Call.getArgOperand(4))->getZExtValue() < 2,
           "isdata argument to llvm.aarch64.prefetch must be 0 or 1", Call);
     break;
   }
   case Intrinsic::callbr_landingpad: {
+    const auto *CBR = dyn_cast<CallBrInst>(Call.getOperand(0));
+    Check(CBR, "intrinstic requires callbr operand", &Call);
+    if (!CBR)
+      break;
+
     const BasicBlock *LandingPadBB = Call.getParent();
-    const BasicBlock *CallBrBB = LandingPadBB->getUniquePredecessor();
-    if (!CallBrBB) {
+    const BasicBlock *PredBB = LandingPadBB->getUniquePredecessor();
+    if (!PredBB) {
       CheckFailed("Intrinsic in block must have 1 unique predecessor", &Call);
       break;
     }
-    const auto *CBR = dyn_cast<CallBrInst>(CallBrBB->getTerminator());
-    if (!CBR) {
+    if (!isa<CallBrInst>(PredBB->getTerminator())) {
       CheckFailed("Intrinsic must have corresponding callbr in predecessor",
                   &Call);
       break;
     }
     Check(llvm::any_of(CBR->getIndirectDests(),
                        [LandingPadBB](const BasicBlock *IndDest) {
                          return IndDest == LandingPadBB;
                        }),
           "Intrinsic's corresponding callbr must have intrinsic's parent basic "
           "block in indirect destination list",
           &Call);
-    Check(!CBR->getType()->isVoidTy(),
-          "intrinsic's corresponding callbr must return a value", &Call);
     const Instruction &First = *LandingPadBB->begin();
     Check(&First == &Call, "No other instructions may proceed intrinsic",
           &Call);
     break;
   }
   };
 
   // Verify that there aren't any unmediated control transfers between funclets.

llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll

define i32 @test0() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY3]], %bb.3
   ; CHECK-NEXT:   $w0 = COPY [[PHI]]
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %out = callbr i32 asm "# $0", "=r,!i"()
           to label %direct [label %entry.indirect_crit_edge]
 
 entry.indirect_crit_edge:                         ; preds = %entry
-  %0 = call i32 @llvm.callbr.landingpad.i32()
+  %0 = call i32 @llvm.callbr.landingpad.i32(i32 %out)
   br label %indirect
 
 direct:                                           ; preds = %entry
   %out2 = callbr i32 asm "# $0", "=r,!i"()
           to label %direct2 [label %direct.indirect_crit_edge]
 
 direct.indirect_crit_edge:                        ; preds = %direct
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %out2)
   br label %indirect
 
 direct2:                                          ; preds = %direct
   ret i32 0
 
 indirect:                                         ; preds = %direct.indirect_crit_edge, %entry.indirect_crit_edge
   %out3 = phi i32 [ %0, %entry.indirect_crit_edge ], [ %1, %direct.indirect_crit_edge ]
   ret i32 %out3

 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %x [label %y]
 
 x:                                                ; preds = %entry
   ret i32 42
 
 y:                                                ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   ret i32 %1
 }
 
 define i32 @dont_split2() {
   ; CHECK-LABEL: name: dont_split2
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
   ; CHECK-NEXT: {{  $}}
define i32 @split_me0() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
   ; CHECK-NEXT:   $w0 = COPY [[PHI]]
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %x [label %entry.y_crit_edge]
 
 entry.y_crit_edge:                                ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %y
 
 x:                                                ; preds = %entry
   br label %y
 
 y:                                                ; preds = %entry.y_crit_edge, %x
   %2 = phi i32 [ %1, %entry.y_crit_edge ], [ 42, %x ]
   ret i32 %2

 entry:
   br i1 %z, label %w, label %v
 
 w:                                                ; preds = %entry
   %0 = callbr i32 asm "", "=r,!i,!i"()
           to label %x [label %w.v_crit_edge, label %w.v_crit_edge]
 
 w.v_crit_edge:                                    ; preds = %w, %w
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %v
 
 x:                                                ; preds = %w
   ret i32 42
 
 v:                                                ; preds = %w.v_crit_edge, %entry
   %2 = phi i32 [ %1, %w.v_crit_edge ], [ undef, %entry ]
   ret i32 %2

 entry:
   br i1 %z, label %w, label %v
 
 w:                                                ; preds = %entry
   %0 = callbr i32 asm "", "=r,!i,!i"()
           to label %x [label %w.v_crit_edge, label %w.v_crit_edge]
 
 w.v_crit_edge:                                    ; preds = %w, %w
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %v
 
 x:                                                ; preds = %w
   ret i32 42
 
 v:                                                ; preds = %w.v_crit_edge, %entry
   %2 = phi i32 [ %1, %w.v_crit_edge ], [ 42, %entry ]
   ret i32 %2

 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %x [label %y]
 
 x:                                                ; preds = %entry
   br label %out
 
 y:                                                ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %out
 
 out:                                              ; preds = %y, %x
   %2 = phi i32 [ %1, %y ], [ %0, %x ]
   ret i32 %2
 }
 
 define i32 @dont_split5() {
define i32 @dont_split5() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
   ; CHECK-NEXT:   $w0 = COPY [[PHI]]
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %out [label %y]
 
 y:                                                ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %out
 
 out:                                              ; preds = %y, %entry
   %2 = phi i32 [ %1, %y ], [ %0, %entry ]
   ret i32 %2
 }
 
 define i32 @split_me3() {
define i32 @split_me3() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2
   ; CHECK-NEXT:   $w0 = COPY [[PHI]]
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %y [label %entry.out_crit_edge]
 
 entry.out_crit_edge:                              ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %out
 
 y:                                                ; preds = %entry
   br label %out
 
 out:                                              ; preds = %entry.out_crit_edge, %y
   %2 = phi i32 [ %1, %entry.out_crit_edge ], [ %0, %y ]
   ret i32 %2
entry:
   br label %loop
 
 loop:                                             ; preds = %loop.loop_crit_edge, %entry
   %1 = phi i32 [ %0, %entry ], [ %3, %loop.loop_crit_edge ]
   %2 = callbr i32 asm "", "=r,0,!i"(i32 %1)
           to label %exit [label %loop.loop_crit_edge]
 
 loop.loop_crit_edge:                              ; preds = %loop
-  %3 = call i32 @llvm.callbr.landingpad.i32()
+  %3 = call i32 @llvm.callbr.landingpad.i32(i32 %2)
   br label %loop
 
 exit:                                             ; preds = %loop
   ret i32 0
 }
 
 define i32 @split_me4() {
   ; CHECK-LABEL: name: split_me4
define i32 @split_me4() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
   ; CHECK-NEXT:   $w0 = COPY [[PHI]]
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %same [label %entry.same_crit_edge]
 
 entry.same_crit_edge:                             ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %same
 
 same:                                             ; preds = %entry.same_crit_edge, %entry
   %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]
   ret i32 %2
 }
 
 define i32 @split_me5() {
define i32 @split_me5() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
   ; CHECK-NEXT:   $w0 = COPY [[PHI]]
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %same [label %entry.same_crit_edge]
 
 entry.same_crit_edge:                             ; preds = %entry
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %same
 
 same:                                             ; preds = %entry.same_crit_edge, %entry
   %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]
   ret i32 %2
 }
 
 ; Function Attrs: nounwind
-declare i32 @llvm.callbr.landingpad.i32() #0
+declare i32 @llvm.callbr.landingpad.i32(i32) #0
 
 ; Function Attrs: nounwind
-declare i64 @llvm.callbr.landingpad.i64() #0
+declare i64 @llvm.callbr.landingpad.i64(i64) #0
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/callbr-prepare.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -callbrprepare -S -o - | FileCheck %s
 
 define i32 @test0() {
 ; CHECK-LABEL: @test0(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[OUT:%.*]] = callbr i32 asm "# $0", "=r,!i"()
 ; CHECK-NEXT:    to label [[DIRECT:%.*]] [label %entry.indirect_crit_edge]
 ; CHECK:       entry.indirect_crit_edge:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT]])
 ; CHECK-NEXT:    br label [[INDIRECT:%.*]]
 ; CHECK:       direct:
 ; CHECK-NEXT:    [[OUT2:%.*]] = callbr i32 asm "# $0", "=r,!i"()
 ; CHECK-NEXT:    to label [[DIRECT2:%.*]] [label %direct.indirect_crit_edge]
 ; CHECK:       direct.indirect_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT2]])
 ; CHECK-NEXT:    br label [[INDIRECT]]
 ; CHECK:       direct2:
 ; CHECK-NEXT:    ret i32 0
 ; CHECK:       indirect:
 ; CHECK-NEXT:    [[OUT3:%.*]] = phi i32 [ [[TMP0]], [[ENTRY_INDIRECT_CRIT_EDGE:%.*]] ], [ [[TMP1]], [[DIRECT_INDIRECT_CRIT_EDGE:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[OUT3]]
 ;
 entry:

 define i32 @dont_split1() {
 ; CHECK-LABEL: @dont_split1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       y:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
   to label %x [label %y]
 
 x:
   ret i32 42

 ; that output is used.
 ; Here we have output and a critical edge along an indirect branch.
 define i32 @split_me0() {
 ; CHECK-LABEL: @split_me0(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[X:%.*]] [label %entry.y_crit_edge]
 ; CHECK:       entry.y_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[Y:%.*]]
 ; CHECK:       x:
 ; CHECK-NEXT:    br label [[Y]]
 ; CHECK:       y:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[ENTRY_Y_CRIT_EDGE:%.*]] ], [ 42, [[X]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:

 define i32 @split_me1(i1 %z) {
 ; CHECK-LABEL: @split_me1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[Z:%.*]], label [[W:%.*]], label [[V:%.*]]
 ; CHECK:       w:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i,!i"()
 ; CHECK-NEXT:    to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
 ; CHECK:       w.v_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[V]]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       v:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[W_V_CRIT_EDGE]] ], [ undef, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:

 define i32 @split_me2(i1 %z) {
 ; CHECK-LABEL: @split_me2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[Z:%.*]], label [[W:%.*]], label [[V:%.*]]
 ; CHECK:       w:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i,!i"()
 ; CHECK-NEXT:    to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
 ; CHECK:       w.v_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[V]]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       v:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[W_V_CRIT_EDGE]] ], [ 42, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:

 define i32 @dont_split4() {
 ; CHECK-LABEL: @dont_split4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    br label [[OUT:%.*]]
 ; CHECK:       y:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[OUT]]
 ; CHECK:       out:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[Y:%.*]] ], [ [[TMP0]], [[X]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
   to label %x [label %y]

 
 ; Triangle with no phi.
 define i32 @dont_split5() {
 ; CHECK-LABEL: @dont_split5(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[OUT:%.*]] [label %y]
 ; CHECK:       y:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[OUT]]
 ; CHECK:       out:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[Y:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
   to label %out [label %y]
 
 y:
   br label %out
 
 out:
   ret i32 %0
 }
 
 ; Triangle the other way with no phi.
 define i32 @split_me3() {
 ; CHECK-LABEL: @split_me3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[Y:%.*]] [label %entry.out_crit_edge]
 ; CHECK:       entry.out_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[OUT:%.*]]
 ; CHECK:       y:
 ; CHECK-NEXT:    br label [[OUT]]
 ; CHECK:       out:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[ENTRY_OUT_CRIT_EDGE:%.*]] ], [ [[TMP0]], [[Y]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:

 ; CHECK-LABEL: @dont_split6(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[TMP1:%.*]] = phi i32 [ [[TMP0:%.*]], [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
 ; CHECK-NEXT:    [[TMP2:%.*]] = callbr i32 asm "", "=r,0,!i"(i32 [[TMP1]])
 ; CHECK-NEXT:    to label [[EXIT:%.*]] [label %loop.loop_crit_edge]
 ; CHECK:       loop.loop_crit_edge:
-; CHECK-NEXT:    [[TMP3]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP3]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP2]])
 ; CHECK-NEXT:    br label [[LOOP]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop
 loop:
   %1 = phi i32 [%0, %entry], [%2, %loop]
   %2 = callbr i32 asm "", "=r,0,!i"(i32 %1) to label %exit [label %loop]
 exit:
   ret i32 0
 }
 
 ; Test same direct+indirect dest no phi.
 define i32 @split_me4() {
 ; CHECK-LABEL: @split_me4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[SAME:%.*]] [label %entry.same_crit_edge]
 ; CHECK:       entry.same_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[SAME]]
 ; CHECK:       same:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[ENTRY_SAME_CRIT_EDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:
   %0 = callbr i32 asm "", "=r,!i"() to label %same [label %same]
 same:
   ret i32 %0
 }
 
 ; Test same direct+indirect dest w/ phi.
 define i32 @split_me5() {
 ; CHECK-LABEL: @split_me5(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[SAME:%.*]] [label %entry.same_crit_edge]
 ; CHECK:       entry.same_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[SAME]]
 ; CHECK:       same:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ [[TMP1]], [[ENTRY_SAME_CRIT_EDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:
   %0 = callbr i32 asm "", "=r,!i"() to label %same [label %same]
 same:
   %1 = phi i32 [%0, %entry], [%0, %entry]
   ret i32 %1
 }
 
 ; "The Devil's cross" (i.e. two asm goto with conflicting physreg constraints
 ; going to the same destination).
 define i64 @split_me6() {
 ; CHECK-LABEL: @split_me6(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i64 asm "# $0 $1", "={dx},!i"()
 ; CHECK-NEXT:    to label [[ASM_FALLTHROUGH:%.*]] [label %entry.foo_crit_edge]
 ; CHECK:       entry.foo_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.callbr.landingpad.i64()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.callbr.landingpad.i64(i64 [[TMP0]])
 ; CHECK-NEXT:    br label [[FOO:%.*]]
 ; CHECK:       asm.fallthrough:
 ; CHECK-NEXT:    [[TMP2:%.*]] = callbr i64 asm "# $0 $1", "={bx},!i"()
 ; CHECK-NEXT:    to label [[FOO]] [label %asm.fallthrough.foo_crit_edge]
 ; CHECK:       asm.fallthrough.foo_crit_edge:
-; CHECK-NEXT:    [[TMP3:%.*]] = call i64 @llvm.callbr.landingpad.i64()
+; CHECK-NEXT:    [[TMP3:%.*]] = call i64 @llvm.callbr.landingpad.i64(i64 [[TMP2]])
 ; CHECK-NEXT:    br label [[FOO]]
 ; CHECK:       foo:
 ; CHECK-NEXT:    [[X_0:%.*]] = phi i64 [ [[TMP1]], [[ENTRY_FOO_CRIT_EDGE:%.*]] ], [ [[TMP3]], [[ASM_FALLTHROUGH_FOO_CRIT_EDGE:%.*]] ], [ [[TMP2]], [[ASM_FALLTHROUGH]] ]
 ; CHECK-NEXT:    ret i64 [[X_0]]
 ;
 entry:
   %0 = callbr i64 asm "# $0 $1", "={dx},!i"()
   to label %asm.fallthrough [label %foo]

 define i32 @multiple_split() {
 ; CHECK-LABEL: @multiple_split(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
 ; CHECK-NEXT:    to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       y:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[TMP1]], [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
   to label %x [label %y]
 
 x:
   ret i32 42
 
 y:
   %1 = add nsw i32 %0, %0
   ret i32 %1
 }

llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll

define i32 @test0() {
   ; CHECK-NEXT:   $eax = COPY %1
   ; CHECK-NEXT:   RET 0, $eax
   %direct = callbr i32 asm "", "=r,!i"()
           to label %cleanup [label %z.split]
 
 cleanup:
   ret i32 42
 z.split:
-  %indirect = call i32 @llvm.callbr.landingpad.i32()
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
   ret i32 %indirect
 }
 
 ; One virtual register, w/ phi
 define i32 @test1() {
   ; CHECK-LABEL: name: test1
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
define i32 @test1() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY1]], %bb.1
   ; CHECK-NEXT:   $eax = COPY [[PHI]]
   ; CHECK-NEXT:   RET 0, $eax
 entry:
   %direct = callbr i32 asm "", "=r,!i"()
           to label %cleanup [label %z.split]
 
 z.split:
-  %indirect = call i32 @llvm.callbr.landingpad.i32()
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ]
   ret i32 %retval.0
 }
 
 ; Two virtual registers
define i32 @test2() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY2]], %bb.1
   ; CHECK-NEXT:   $eax = COPY [[PHI]]
   ; CHECK-NEXT:   RET 0, $eax
 entry:
   %direct = callbr { i32, i32 } asm "", "=r,=r,!i"()
           to label %cleanup [label %z.split]
 
 z.split:
-  %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s()
+  %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 } %direct)
   %asmresult2 = extractvalue { i32, i32 } %indirect, 0
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ]
   ret i32 %retval.0
 }
 
define i32 @test3() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY3]], %bb.1
   ; CHECK-NEXT:   $eax = COPY [[PHI]]
   ; CHECK-NEXT:   RET 0, $eax
 entry:
   %direct = callbr i32 asm "", "={bx},!i"()
           to label %cleanup [label %z.split]
 
 z.split:
-  %indirect = call i32 @llvm.callbr.landingpad.i32()
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ]
   ret i32 %retval.0
 }
 
 ; Two physical registers
define i32 @test4() {
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY5]], %bb.1
   ; CHECK-NEXT:   $eax = COPY [[PHI]]
   ; CHECK-NEXT:   RET 0, $eax
 entry:
   %direct = callbr { i32, i32 } asm "", "={bx},={dx},!i"()
           to label %cleanup [label %z.split]
 
 z.split:
-  %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s()
+  %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 } %direct)
   %asmresult2 = extractvalue { i32, i32 } %indirect, 0
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ]
   ret i32 %retval.0
 }
 
define i32 @test5() {
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $ebx
   ; CHECK-NEXT:   $eax = COPY [[COPY2]]
   ; CHECK-NEXT:   RET 0, $eax
 entry:
   %direct = callbr i32 asm "# $0", "={bx},!i"()
           to label %cleanup [label %cleanup]
 
 cleanup:
-  %indirect = call i32 @llvm.callbr.landingpad.i32()
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
   ret i32 %indirect
 }
 
 ; "The Devil's cross" (i.e. two asm goto with conflicting physreg constraints
 ; going to the same destination) as expressed by clang.
 define i64 @test6() {
   ; CHECK-LABEL: name: test6
   ; CHECK: bb.0.entry:
asm.fallthrough:
   %1 = callbr i64 asm "", "={bx},!i"()
           to label %foo [label %foo.split2]
 
 foo:
   %x.0 = phi i64 [ %3, %foo.split2 ], [ %2, %foo.split ], [ %1, %asm.fallthrough ]
   ret i64 %x.0
 
 foo.split:
-  %2 = call i64 @llvm.callbr.landingpad.i64()
+  %2 = call i64 @llvm.callbr.landingpad.i64(i64 %0)
   br label %foo
 
 foo.split2:
-  %3 = call i64 @llvm.callbr.landingpad.i64()
+  %3 = call i64 @llvm.callbr.landingpad.i64(i64 %1)
   br label %foo
 }
 
 
 ; Test a callbr looping back on itself.
 define i32 @test7() {
   ; CHECK-LABEL: name: test7
   ; CHECK: bb.0.entry:
retry:
   %x.0 = phi i32 [ undef, %entry ], [ %1, %retry.split ]
   %0 = callbr i32 asm "", "={dx},0,!i"(i32 %x.0)
           to label %asm.fallthrough [label %retry.split]
 
 asm.fallthrough:
   ret i32 %0
 
 retry.split:
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   br label %retry
 }
 
 ; Test the same destination appearing in the direct/fallthrough branch as the
 ; indirect branch. Same as test5 but with a virtreg rather than a physreg
 ; constraint.
 define i32 @test8() {
   ; CHECK-LABEL: name: test8
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.1
   ; CHECK-NEXT:   %0:gr32 = COPY %1
   ; CHECK-NEXT:   JMP_1 %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target):
   ; CHECK-NEXT:   $eax = COPY %1
   ; CHECK-NEXT:   RET 0, $eax
 entry:
   %direct = callbr i32 asm "# $0", "=r,!i"()
           to label %cleanup [label %cleanup]
 
 cleanup:
-  %indirect = call i32 @llvm.callbr.landingpad.i32()
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
   ret i32 %indirect
 }
 
-declare i64 @llvm.callbr.landingpad.i64()
-declare i32 @llvm.callbr.landingpad.i32()
-declare { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s()
+declare i64 @llvm.callbr.landingpad.i64(i64)
+declare i32 @llvm.callbr.landingpad.i32(i32)
+declare { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 })

llvm/test/Transforms/SimplifyCFG/callbr-destinations.ll

 ; Validate that callbr landingpad intrinsics do not get merged (via the
 ; IntrNoMerge attribute).
 define i32 @callbr_landingpad_nomerge() {
 ; CHECK-LABEL: @callbr_landingpad_nomerge(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[OUT:%.*]] = callbr i32 asm "# $0", "=r,!i"()
 ; CHECK-NEXT:    to label [[DIRECT:%.*]] [label %entry.indirect_crit_edge]
 ; CHECK:       entry.indirect_crit_edge:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT]])
 ; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       direct:
 ; CHECK-NEXT:    [[OUT2:%.*]] = callbr i32 asm "# $0", "=r,!i"()
 ; CHECK-NEXT:    to label [[COMMON_RET]] [label %direct.indirect_crit_edge]
 ; CHECK:       direct.indirect_crit_edge:
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT2]])
 ; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 0, [[DIRECT]] ], [ [[TMP0]], [[ENTRY_INDIRECT_CRIT_EDGE:%.*]] ], [ [[TMP1]], [[DIRECT_INDIRECT_CRIT_EDGE:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   %out = callbr i32 asm "# $0", "=r,!i"()
   to label %direct [label %entry.indirect_crit_edge]
 
 entry.indirect_crit_edge:
-  %0 = call i32 @llvm.callbr.landingpad.i32()
+  %0 = call i32 @llvm.callbr.landingpad.i32(i32 %out)
   br label %indirect
 
 direct:
   %out2 = callbr i32 asm "# $0", "=r,!i"()
   to label %direct2 [label %direct.indirect_crit_edge]
 
 direct.indirect_crit_edge:
-  %1 = call i32 @llvm.callbr.landingpad.i32()
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %out2)
   br label %indirect
 
 direct2:
   ret i32 0
 
 indirect:
   %out3 = phi i32 [ %0, %entry.indirect_crit_edge ], [ %1, %direct.indirect_crit_edge ]
   ret i32 %out3
 }
 
-declare i32 @llvm.callbr.landingpad.i32()
+declare i32 @llvm.callbr.landingpad.i32(i32)

llvm/test/Verifier/callbr.ll

 normal:
   ret i32 0
 
 abnormal:
   ret i32 %ret
 }
 
 ;; Tests of the callbr.landingpad intrinsic function.
-; The intrinsic does not accept parameters.
-declare i32 @llvm.callbr.landingpad.i64(i64 %x)
+declare i32 @llvm.callbr.landingpad.i64(i64)
 define void @callbrpad_bad_type() {
 entry:
 ; CHECK: Intrinsic has incorrect argument type!
 ; CHECK-NEXT: ptr @llvm.callbr.landingpad.i64
   %foo = call i32 @llvm.callbr.landingpad.i64(i64 42)
   ret void
 }
 
-declare i32 @llvm.callbr.landingpad.i32()
+declare i32 @llvm.callbr.landingpad.i32(i32)
 define i32 @callbrpad_multi_preds() {
 entry:
   %foo = callbr i32 asm "", "=r,!i"() to label %direct [label %indirect]
 direct:
   br label %indirect
 indirect:
 ; CHECK-NEXT: Intrinsic in block must have 1 unique predecessor
-; CHECK-NEXT: %out = call i32 @llvm.callbr.landingpad.i32()
-  %out = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT: %out = call i32 @llvm.callbr.landingpad.i32(i32 %foo)
+  %out = call i32 @llvm.callbr.landingpad.i32(i32 %foo)
   ret i32 %out
 }
 
-define void @callbrpad_no_callbr() {
-entry:
-  br label %foo
-foo:
-; CHECK-NEXT: Intrinsic must have corresponding callbr in predecessor
-; CHECK-NEXT: %out = call i32 @llvm.callbr.landingpad.i32()
-  %out = call i32 @llvm.callbr.landingpad.i32()
-  ret void
-}
-
 define void @callbrpad_wrong_callbr() {
 entry:
   %foo = callbr i32 asm "", "=r,!i"() to label %direct [label %indirect]
 direct:
 ; CHECK-NEXT: Intrinsic's corresponding callbr must have intrinsic's parent basic block in indirect destination list
-; CHECK-NEXT: %x = call i32 @llvm.callbr.landingpad.i32()
-  %x = call i32 @llvm.callbr.landingpad.i32()
-  ret void
-indirect:
-  ret void
-}
-
-define void @callbrpad_void_callbr() {
-entry:
-  callbr void asm "", "!i"() to label %direct [label %indirect]
-direct:
+; CHECK-NEXT: %x = call i32 @llvm.callbr.landingpad.i32(i32 %foo)
+  %x = call i32 @llvm.callbr.landingpad.i32(i32 %foo)
   ret void
 indirect:
-; CHECK-NEXT: intrinsic's corresponding callbr must return a value
-; CHECK-NEXT: %out = call i32 @llvm.callbr.landingpad.i32()
-  %out = call i32 @llvm.callbr.landingpad.i32()
   ret void
 }
 
 declare i32 @foo(i32)
 define i32 @test_callbr_landingpad_not_first_inst() {
 entry:
   %0 = callbr i32 asm "", "=r,!i"()
           to label %asm.fallthrough [label %landingpad]
 
 asm.fallthrough:
   ret i32 42
 
 landingpad:
   %foo = call i32 @foo(i32 42)
 ; CHECK-NEXT: No other instructions may proceed intrinsic
-; CHECK-NEXT: %out = call i32 @llvm.callbr.landingpad.i32()
-  %out = call i32 @llvm.callbr.landingpad.i32()
+; CHECK-NEXT: %out = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  %out = call i32 @llvm.callbr.landingpad.i32(i32 %0)
   ret i32 %out
 }