diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13265,7 +13265,10 @@
   SDNode *Copy = *N->use_begin();
   // TODO: Handle additional opcodes in order to support tail-calling libcalls
   // with soft float ABIs.
-  if (Copy->getOpcode() != ISD::CopyToReg) {
+  if (Copy->getOpcode() == ISD::BITCAST)
+    return isUsedByReturnOnly(Copy, Chain);
+
+  if (!(Copy->getOpcode() == ISD::CopyToReg)) {
     return false;
   }
 
diff --git a/llvm/test/CodeGen/RISCV/float-frem.ll b/llvm/test/CodeGen/RISCV/float-frem.ll
--- a/llvm/test/CodeGen/RISCV/float-frem.ll
+++ b/llvm/test/CodeGen/RISCV/float-frem.ll
@@ -11,12 +11,7 @@
 define float @frem_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: frem_f32:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    addi sp, sp, -16
-; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    call fmodf@plt
-; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    addi sp, sp, 16
-; RV32IF-NEXT:    ret
+; RV32IF-NEXT:    tail fmodf@plt
 ;
 ; RV64IF-LABEL: frem_f32:
 ; RV64IF:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
--- a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
@@ -240,14 +240,18 @@
 ; F-ABI-ALL:       # %bb.0:
 ; F-ABI-ALL-NEXT:    tail sinf@plt
 ;
-; RV32-ILP32-ALL-LABEL: sin_f32:
-; RV32-ILP32-ALL:       # %bb.0:
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, -16
-; RV32-ILP32-ALL-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32-ALL-NEXT:    call sinf@plt
-; RV32-ILP32-ALL-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, 16
-; RV32-ILP32-ALL-NEXT:    ret
+; RV32IFD-ILP32-LABEL: sin_f32:
+; RV32IFD-ILP32:       # %bb.0:
+; RV32IFD-ILP32-NEXT:    tail sinf@plt
+;
+; RV32I-ILP32-LABEL: sin_f32:
+; RV32I-ILP32:       # %bb.0:
+; RV32I-ILP32-NEXT:    addi sp, sp, -16
+; RV32I-ILP32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32-NEXT:    call sinf@plt
+; RV32I-ILP32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32-NEXT:    addi sp, sp, 16
+; RV32I-ILP32-NEXT:    ret
 ;
 ; RV64-LP64-ALL-LABEL: sin_f32:
 ; RV64-LP64-ALL:       # %bb.0:
@@ -272,14 +276,18 @@
 ; RV32IF-ILP32F:       # %bb.0:
 ; RV32IF-ILP32F-NEXT:    tail __powisf2@plt
 ;
-; RV32-ILP32-ALL-LABEL: powi_f32:
-; RV32-ILP32-ALL:       # %bb.0:
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, -16
-; RV32-ILP32-ALL-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32-ALL-NEXT:    call __powisf2@plt
-; RV32-ILP32-ALL-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, 16
-; RV32-ILP32-ALL-NEXT:    ret
+; RV32IFD-ILP32-LABEL: powi_f32:
+; RV32IFD-ILP32:       # %bb.0:
+; RV32IFD-ILP32-NEXT:    tail __powisf2@plt
+;
+; RV32I-ILP32-LABEL: powi_f32:
+; RV32I-ILP32:       # %bb.0:
+; RV32I-ILP32-NEXT:    addi sp, sp, -16
+; RV32I-ILP32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32-NEXT:    call __powisf2@plt
+; RV32I-ILP32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32-NEXT:    addi sp, sp, 16
+; RV32I-ILP32-NEXT:    ret
 ;
 ; RV64IFD-LP64D-LABEL: powi_f32:
 ; RV64IFD-LP64D:       # %bb.0:
@@ -390,14 +398,18 @@
 ; RV64IF-LP64F-NEXT:    addi sp, sp, 16
 ; RV64IF-LP64F-NEXT:    ret
 ;
-; RV64-LP64-ALL-LABEL: sin_f64:
-; RV64-LP64-ALL:       # %bb.0:
-; RV64-LP64-ALL-NEXT:    addi sp, sp, -16
-; RV64-LP64-ALL-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-LP64-ALL-NEXT:    call sin@plt
-; RV64-LP64-ALL-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-LP64-ALL-NEXT:    addi sp, sp, 16
-; RV64-LP64-ALL-NEXT:    ret
+; RV64IFD-LP64-LABEL: sin_f64:
+; RV64IFD-LP64:       # %bb.0:
+; RV64IFD-LP64-NEXT:    tail sin@plt
+;
+; RV64I-LP64-LABEL: sin_f64:
+; RV64I-LP64:       # %bb.0:
+; RV64I-LP64-NEXT:    addi sp, sp, -16
+; RV64I-LP64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64-NEXT:    call sin@plt
+; RV64I-LP64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64-NEXT:    addi sp, sp, 16
+; RV64I-LP64-NEXT:    ret
   %1 = call double @llvm.sin.f64(double %a)
   ret double %1
 }