Index: lib/Target/Mips/MicroMipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -55,8 +55,18 @@ class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>; class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>; class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>; +class MUL_PH_MMR2_ENC : POOL32A_3R_FMT<"mul.ph", 0b00000101101>; +class MUL_S_PH_MMR2_ENC : POOL32A_3R_FMT<"mul_s.ph", 0b10000101101>; +class MULEQ_S_W_PHL_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phl", 0b0000100101>; +class MULEQ_S_W_PHR_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phr", 0b0001100101>; +class MULEU_S_PH_QBL_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbl", 0b0010010101>; +class MULEU_S_PH_QBR_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbr", 0b0011010101>; +class MULQ_RS_PH_MM_ENC : POOL32A_3RB0_FMT<"mulq_rs.ph", 0b0100010101>; +class MULQ_RS_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_rs.w", 0b0110010101>; +class MULQ_S_PH_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.ph", 0b0101010101>; +class MULQ_S_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.w", 0b0111010101>; -// Instruction desc. +//Instruction descriptions class ABSQ_S_PH_MM_R2_DESC_BASE { @@ -148,6 +158,11 @@ def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC; def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC; def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC; +def MULEQ_S_W_PHL_MM : DspMMRel, MULEQ_S_W_PHL_MM_ENC, MULEQ_S_W_PHL_DESC; +def MULEQ_S_W_PHR_MM : DspMMRel, MULEQ_S_W_PHR_MM_ENC, MULEQ_S_W_PHR_DESC; +def MULEU_S_PH_QBL_MM : DspMMRel, MULEU_S_PH_QBL_MM_ENC, MULEU_S_PH_QBL_DESC; +def MULEU_S_PH_QBR_MM : DspMMRel, MULEU_S_PH_QBR_MM_ENC, MULEU_S_PH_QBR_DESC; +def MULQ_RS_PH_MM : DspMMRel, MULQ_RS_PH_MM_ENC, MULQ_RS_PH_DESC; // microMIPS DSP Rev 2 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, ISA_DSPR2; @@ -168,3 +183,8 @@ def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2; def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC, ISA_DSPR2; +def MUL_PH_MMR2 : DspMMRel, MUL_PH_MMR2_ENC, MUL_PH_DESC, ISA_DSPR2; +def MUL_S_PH_MMR2 : DspMMRel, MUL_S_PH_MMR2_ENC, MUL_S_PH_DESC, ISA_DSPR2; +def MULQ_RS_W_MMR2 : DspMMRel, MULQ_RS_W_MMR2_ENC, MULQ_RS_W_DESC, ISA_DSPR2; +def MULQ_S_PH_MMR2 : DspMMRel, MULQ_S_PH_MMR2_ENC, MULQ_S_PH_DESC, ISA_DSPR2; +def MULQ_S_W_MMR2 : DspMMRel, MULQ_S_W_MMR2_ENC, MULQ_S_W_DESC, ISA_DSPR2; Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -1128,11 +1128,11 @@ def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC; def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC; def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC; -def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; -def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; -def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; -def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; -def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; +def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; +def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; +def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; +def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; +def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; @@ -1219,11 +1219,11 @@ def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC; def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; -def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; -def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; -def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; -def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; -def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; +def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC; +def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC; +def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC; +def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC; +def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC; def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC; def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; Index: test/MC/Disassembler/Mips/micromips-dsp/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips-dsp/valid.txt +++ test/MC/Disassembler/Mips/micromips-dsp/valid.txt @@ -28,3 +28,8 @@ 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5 +0x00 0x62 0x08 0x25 # CHECK: muleq_s.w.phl $1, $2, $3 +0x00 0x62 0x08 0x65 # CHECK: muleq_s.w.phr $1, $2, $3 +0x00 0x62 0x08 0x95 # CHECK: muleu_s.ph.qbl $1, $2, $3 +0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3 +0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3 Index: test/MC/Disassembler/Mips/micromips-dspr2/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips-dspr2/valid.txt +++ test/MC/Disassembler/Mips/micromips-dspr2/valid.txt @@ -15,3 +15,8 @@ 0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1 0x00 0x64 0xa1 0xfc # CHECK: shra.qb $3, $4, 5 0x00 0x64 0xb1 0xfc # CHECK: shra_r.qb $3, $4, 5 +0x00 0x62 0x08 0x2d # CHECK: mul.ph $1, $2, $3 +0x00 0x62 0x0c 0x2d # CHECK: mul_s.ph $1, $2, $3 +0x00 0x62 0x09 0x95 # CHECK: mulq_rs.w $1, $2, $3 +0x00 0x62 0x09 0x55 # CHECK: mulq_s.ph $1, $2, $3 +0x00 0x62 0x09 0xd5 # CHECK: mulq_s.w $1, $2, $3 Index: test/MC/Mips/micromips-dsp/valid.s =================================================================== --- test/MC/Mips/micromips-dsp/valid.s +++ test/MC/Mips/micromips-dsp/valid.s @@ -29,3 +29,8 @@ shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95] shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5] shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5] + muleq_s.w.phl $1, $2, $3 # CHECK: muleq_s.w.phl $1, $2, $3 # encoding: [0x00,0x62,0x08,0x25] + muleq_s.w.phr $1, $2, $3 # CHECK: muleq_s.w.phr $1, $2, $3 # encoding: [0x00,0x62,0x08,0x65] + muleu_s.ph.qbl $1, $2, $3 # CHECK: muleu_s.ph.qbl $1, $2, $3 # encoding: [0x00,0x62,0x08,0x95] + muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5] + mulq_rs.ph $1, $2, $3 # CHECK: mulq_rs.ph $1, $2, $3 # encoding: [0x00,0x62,0x09,0x15] Index: test/MC/Mips/micromips-dspr2/valid.s =================================================================== --- test/MC/Mips/micromips-dspr2/valid.s +++ test/MC/Mips/micromips-dspr2/valid.s @@ -16,3 +16,8 @@ dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc] shra.qb $3, $4, 5 # CHECK: shra.qb $3, $4, 5 # encoding: [0x00,0x64,0xa1,0xfc] shra_r.qb $3, $4, 5 # CHECK: shra_r.qb $3, $4, 5 # encoding: [0x00,0x64,0xb1,0xfc] + mul.ph $1, $2, $3 # CHECK: mul.ph $1, $2, $3 # encoding: [0x00,0x62,0x08,0x2d] + mul_s.ph $1, $2, $3 # CHECK: mul_s.ph $1, $2, $3 # encoding: [0x00,0x62,0x0c,0x2d] + mulq_rs.w $1, $2, $3 # CHECK: mulq_rs.w $1, $2, $3 # encoding: [0x00,0x62,0x09,0x95] + mulq_s.ph $1, $2, $3 # CHECK: mulq_s.ph $1, $2, $3 # encoding: [0x00,0x62,0x09,0x55] + mulq_s.w $1, $2, $3 # CHECK: mulq_s.w $1, $2, $3 # encoding: [0x00,0x62,0x09,0xd5]