diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -166,58 +166,6 @@ DecodeStatus convertVOPCDPPInst(MCInst &MI) const; void convertMacDPPInst(MCInst &MI) const; - MCOperand decodeOperand_VGPR_32(unsigned Val) const; - MCOperand decodeOperand_VGPR_32_Lo128(unsigned Val) const; - MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const; - - MCOperand decodeOperand_VS_32(unsigned Val) const; - MCOperand decodeOperand_VS_64(unsigned Val) const; - MCOperand decodeOperand_VS_128(unsigned Val) const; - MCOperand decodeOperand_VSrc16(unsigned Val) const; - MCOperand decodeOperand_VSrcV216(unsigned Val) const; - MCOperand decodeOperand_VSrcV232(unsigned Val) const; - - MCOperand decodeOperand_VReg_64(unsigned Val) const; - MCOperand decodeOperand_VReg_96(unsigned Val) const; - MCOperand decodeOperand_VReg_128(unsigned Val) const; - MCOperand decodeOperand_VReg_256(unsigned Val) const; - MCOperand decodeOperand_VReg_288(unsigned Val) const; - MCOperand decodeOperand_VReg_320(unsigned Val) const; - MCOperand decodeOperand_VReg_352(unsigned Val) const; - MCOperand decodeOperand_VReg_384(unsigned Val) const; - MCOperand decodeOperand_VReg_512(unsigned Val) const; - MCOperand decodeOperand_VReg_1024(unsigned Val) const; - - MCOperand decodeOperand_SReg_32(unsigned Val) const; - MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const; - MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const; - MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const; - MCOperand decodeOperand_SReg_64(unsigned Val) const; - MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const; - MCOperand decodeOperand_SReg_128(unsigned Val) const; - MCOperand decodeOperand_SReg_256(unsigned Val) const; - MCOperand decodeOperand_SReg_288(unsigned Val) const; - MCOperand decodeOperand_SReg_320(unsigned Val) const; - MCOperand decodeOperand_SReg_352(unsigned Val) const; - MCOperand decodeOperand_SReg_384(unsigned Val) const; - MCOperand decodeOperand_SReg_512(unsigned Val) const; - - MCOperand decodeOperand_AGPR_32(unsigned Val) const; - MCOperand decodeOperand_AReg_64(unsigned Val) const; - MCOperand decodeOperand_AReg_128(unsigned Val) const; - MCOperand decodeOperand_AReg_256(unsigned Val) const; - MCOperand decodeOperand_AReg_288(unsigned Val) const; - MCOperand decodeOperand_AReg_320(unsigned Val) const; - MCOperand decodeOperand_AReg_352(unsigned Val) const; - MCOperand decodeOperand_AReg_384(unsigned Val) const; - MCOperand decodeOperand_AReg_512(unsigned Val) const; - MCOperand decodeOperand_AReg_1024(unsigned Val) const; - MCOperand decodeOperand_AV_32(unsigned Val) const; - MCOperand decodeOperand_AV_64(unsigned Val) const; - MCOperand decodeOperand_AV_128(unsigned Val) const; - MCOperand decodeOperand_AVDst_128(unsigned Val) const; - MCOperand decodeOperand_AVDst_512(unsigned Val) const; - enum OpWidthTy { OPW32, OPW64, @@ -244,18 +192,21 @@ unsigned getTtmpClassId(const OpWidthTy Width) const; static MCOperand decodeIntImmed(unsigned Imm); - static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm); + static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm); + MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const; MCOperand decodeLiteralConstant() const; MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, - bool MandatoryLiteral = false) const; - MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const; + bool MandatoryLiteral = false, + unsigned ImmWidth = 0) const; + MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const; MCOperand decodeSpecialReg32(unsigned Val) const; MCOperand decodeSpecialReg64(unsigned Val) const; - MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const; + MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, + unsigned ImmWidth = 0) const; MCOperand decodeSDWASrc16(unsigned Val) const; MCOperand decodeSDWASrc32(unsigned Val) const; MCOperand decodeSDWAVopcDst(unsigned Val) const; diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -118,149 +118,151 @@ #define DECODE_OPERAND_REG(RegClass) \ DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) -DECODE_OPERAND_REG(VGPR_32) -DECODE_OPERAND_REG(VGPR_32_Lo128) -DECODE_OPERAND_REG(VRegOrLds_32) -DECODE_OPERAND_REG(VS_32) -DECODE_OPERAND_REG(VS_64) -DECODE_OPERAND_REG(VS_128) - -DECODE_OPERAND_REG(VReg_64) -DECODE_OPERAND_REG(VReg_96) -DECODE_OPERAND_REG(VReg_128) -DECODE_OPERAND_REG(VReg_256) -DECODE_OPERAND_REG(VReg_288) -DECODE_OPERAND_REG(VReg_352) -DECODE_OPERAND_REG(VReg_384) -DECODE_OPERAND_REG(VReg_512) -DECODE_OPERAND_REG(VReg_1024) - -DECODE_OPERAND_REG(SReg_32) -DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) -DECODE_OPERAND_REG(SReg_32_XEXEC_HI) -DECODE_OPERAND_REG(SRegOrLds_32) -DECODE_OPERAND_REG(SReg_64) -DECODE_OPERAND_REG(SReg_64_XEXEC) -DECODE_OPERAND_REG(SReg_128) -DECODE_OPERAND_REG(SReg_256) -DECODE_OPERAND_REG(SReg_512) - -DECODE_OPERAND_REG(AGPR_32) -DECODE_OPERAND_REG(AReg_64) -DECODE_OPERAND_REG(AReg_128) -DECODE_OPERAND_REG(AReg_256) -DECODE_OPERAND_REG(AReg_512) -DECODE_OPERAND_REG(AReg_1024) -DECODE_OPERAND_REG(AV_32) -DECODE_OPERAND_REG(AV_64) -DECODE_OPERAND_REG(AV_128) -DECODE_OPERAND_REG(AVDst_128) -DECODE_OPERAND_REG(AVDst_512) - -static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); -} - -static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); -} - -static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); -} - -static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); -} - -static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); -} - -static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); -} - -static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); -} - -static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); -} - -static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); -} - -static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); -} - -static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); -} - -static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); -} +// Decoder for registers, decode directly using RegClassID. Imm(8-bit) is +// number of register. Used by VGPR only and AGPR only operands. +#define DECODE_OPERAND_REG_8(RegClass) \ + static DecodeStatus Decode##RegClass##RegisterClass( \ + MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ + const MCDisassembler *Decoder) { \ + assert(Imm < (1 << 8) && "8-bit encoding"); \ + auto DAsm = static_cast(Decoder); \ + return addOperand( \ + Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ + } -static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); -} +#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ + ImmWidth) \ + static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ + const MCDisassembler *Decoder) { \ + assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ + auto DAsm = static_cast(Decoder); \ + return addOperand(Inst, \ + DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ + MandatoryLiteral, ImmWidth)); \ + } -static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); -} +// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to +// get register class. Used by SGPR only operands. +#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ + DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) + +// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, +// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). +// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. +// Used by AV_ register classes (AGPR or VGPR only register operands). +#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ + DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ + Imm | AMDGPU::EncValues::IS_VGPR, false, 0) + +// Decoder for Src(9-bit encoding) registers only. +#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ + DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) + +// Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set +// Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers +// only. +#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ + DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) + +// Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding +// Imm{9} is acc, registers only. +#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ + DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) + +// Decoder for RegisterOperands using 9-bit Src encoding. Operand can be +// register from RegClass or immediate. Registers that don't belong to RegClass +// will be decoded and InstPrinter will report warning. Immediate will be +// decoded into constant of size ImmWidth, should match width of immediate used +// by OperandType (important for floating point types). +#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ + DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ + false, ImmWidth) + +// Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) +// and decode using 'enum10' from decodeSrcOp. +#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ + DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ + Imm | 512, false, ImmWidth) + +#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ + DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ + OpWidth, Imm, true, ImmWidth) + +// Default decoders generated by tablegen: 'DecodeRegisterClass' +// when RegisterClass is used as an operand. Most often used for destination +// operands. -static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); -} +DECODE_OPERAND_REG_8(VGPR_32) +DECODE_OPERAND_REG_8(VGPR_32_Lo128) +DECODE_OPERAND_REG_8(VReg_64) +DECODE_OPERAND_REG_8(VReg_96) +DECODE_OPERAND_REG_8(VReg_128) +DECODE_OPERAND_REG_8(VReg_256) +DECODE_OPERAND_REG_8(VReg_288) +DECODE_OPERAND_REG_8(VReg_352) +DECODE_OPERAND_REG_8(VReg_384) +DECODE_OPERAND_REG_8(VReg_512) +DECODE_OPERAND_REG_8(VReg_1024) + +DECODE_OPERAND_REG_7(SReg_32, OPW32) +DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) +DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) +DECODE_OPERAND_REG_7(SReg_64, OPW64) +DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) +DECODE_OPERAND_REG_7(SReg_128, OPW128) +DECODE_OPERAND_REG_7(SReg_256, OPW256) +DECODE_OPERAND_REG_7(SReg_512, OPW512) + +DECODE_OPERAND_REG_8(AGPR_32) +DECODE_OPERAND_REG_8(AReg_64) +DECODE_OPERAND_REG_8(AReg_128) +DECODE_OPERAND_REG_8(AReg_256) +DECODE_OPERAND_REG_8(AReg_512) +DECODE_OPERAND_REG_8(AReg_1024) + +DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) +DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) + +// Decoders for register only source RegisterOperands that use use 9-bit Src +// encoding: 'decodeOperand_'. + +DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) +DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) +DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) +DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) +DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) + +DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) + +DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) +DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) +DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) + +// Decoders for register or immediate RegisterOperands that use 9-bit Src +// encoding: 'decodeOperand__Imm'. + +DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) +DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) + +DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) +DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) +DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) +DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) + +DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) +DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) +DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, @@ -276,22 +278,6 @@ return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); } -static DecodeStatus -decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, - const MCDisassembler *Decoder) { - const auto *DAsm = static_cast(Decoder); - return addOperand( - Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); -} - -static DecodeStatus -decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, - const MCDisassembler *Decoder) { - const auto *DAsm = static_cast(Decoder); - return addOperand( - Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); -} - static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder) { const auto *DAsm = static_cast(Decoder); @@ -381,13 +367,6 @@ Decoder); } -static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - auto DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); -} - #define DECODE_SDWA(DecName) \ DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) @@ -1159,214 +1138,6 @@ return createRegOperand(SRegClassID, Val >> shift); } -MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { - return decodeSrcOp(OPW32, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { - return decodeSrcOp(OPW64, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { - return decodeSrcOp(OPW128, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { - return decodeSrcOp(OPW16, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { - return decodeSrcOp(OPWV216, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { - return decodeSrcOp(OPWV232, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128(unsigned Val) const { - return createRegOperand(AMDGPU::VGPR_32_Lo128RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { - // Some instructions have operand restrictions beyond what the encoding - // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra - // high bit. - Val &= 255; - - return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { - return decodeSrcOp(OPW32, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { - return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_288(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_288RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_320(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_320RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_352(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_352RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_384(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_384RegClassID, Val & 255); -} - - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { - return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { - return decodeSrcOp(OPW32, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { - return decodeSrcOp(OPW64, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { - return decodeSrcOp(OPW128, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { - using namespace AMDGPU::EncValues; - assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. - return decodeSrcOp(OPW128, Val | IS_VGPR); -} - -MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { - using namespace AMDGPU::EncValues; - assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. - return decodeSrcOp(OPW512, Val | IS_VGPR); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_64RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_96RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_128RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_256RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_288(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_288RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_320(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_320RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_352(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_352RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_384(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_384RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_512RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { - return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { - // table-gen generated disassembler doesn't care about operand types - // leaving only registry class so SSrc_32 operand turns into SReg_32 - // and therefore we accept immediates and literals here as well - return decodeSrcOp(OPW32, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( - unsigned Val) const { - // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI - return decodeOperand_SReg_32(Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( - unsigned Val) const { - // SReg_32_XM0 is SReg_32 without EXEC_HI - return decodeOperand_SReg_32(Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { - // table-gen generated disassembler doesn't care about operand types - // leaving only registry class so SSrc_32 operand turns into SReg_32 - // and therefore we accept immediates and literals here as well - return decodeSrcOp(OPW32, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { - return decodeSrcOp(OPW64, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { - return decodeSrcOp(OPW64, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { - return decodeSrcOp(OPW128, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { - return decodeDstOp(OPW256, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_288(unsigned Val) const { - return decodeDstOp(OPW288, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_320(unsigned Val) const { - return decodeDstOp(OPW320, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_352(unsigned Val) const { - return decodeDstOp(OPW352, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_384(unsigned Val) const { - return decodeDstOp(OPW384, Val); -} - -MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { - return decodeDstOp(OPW512, Val); -} - // Decode Literals for insts which always have a literal in the encoding MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { @@ -1482,23 +1253,21 @@ } } -MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { +MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); // ToDo: case 248: 1/(2*PI) - is allowed only on VI - switch (Width) { - case OPW32: - case OPW128: // splat constants - case OPW512: - case OPW1024: - case OPWV232: + // ImmWidth 0 is a default case where operand should not allow immediates. + // Imm value is still decoded into 32 bit immediate operand, inst printer will + // use it to print verbose error message. + switch (ImmWidth) { + case 0: + case 32: return MCOperand::createImm(getInlineImmVal32(Imm)); - case OPW64: - case OPW256: + case 64: return MCOperand::createImm(getInlineImmVal64(Imm)); - case OPW16: - case OPWV216: + case 16: return MCOperand::createImm(getInlineImmVal16(Imm)); default: llvm_unreachable("implement me"); @@ -1612,7 +1381,8 @@ } MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, - bool MandatoryLiteral) const { + bool MandatoryLiteral, + unsigned ImmWidth) const { using namespace AMDGPU::EncValues; assert(Val < 1024); // enum10 @@ -1639,7 +1409,7 @@ return decodeIntImmed(Val); if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) - return decodeFPImmed(Width, Val); + return decodeFPImmed(ImmWidth, Val); if (Val == LITERAL_CONST) { if (MandatoryLiteral) @@ -1662,26 +1432,6 @@ } } -MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { - using namespace AMDGPU::EncValues; - - assert(Val < 128); - assert(Width == OPW256 || Width == OPW512); - - if (Val <= SGPR_MAX) { - // "SGPR_MIN <= Val" is always true and causes compilation warning. - static_assert(SGPR_MIN == 0); - return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); - } - - int TTmpIdx = getTTmpIdx(Val); - if (TTmpIdx >= 0) { - return createSRegOperand(getTtmpClassId(Width), TTmpIdx); - } - - llvm_unreachable("unknown dst register"); -} - // Bit 0 of DstY isn't stored in the instruction, because it's always the // opposite of bit 0 of DstX. MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, @@ -1764,7 +1514,8 @@ } MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, - const unsigned Val) const { + const unsigned Val, + unsigned ImmWidth) const { using namespace AMDGPU::SDWA; using namespace AMDGPU::EncValues; @@ -1795,7 +1546,7 @@ return decodeIntImmed(SVal); if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) - return decodeFPImmed(Width, SVal); + return decodeFPImmed(ImmWidth, SVal); return decodeSpecialReg32(SVal); } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { @@ -1805,11 +1556,11 @@ } MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { - return decodeSDWASrc(OPW16, Val); + return decodeSDWASrc(OPW16, Val, 16); } MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { - return decodeSDWASrc(OPW32, Val); + return decodeSDWASrc(OPW32, Val, 32); } MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { @@ -1840,8 +1591,9 @@ } MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { - return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? - decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); + return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] + ? decodeSrcOp(OPW64, Val) + : decodeSrcOp(OPW32, Val); } bool AMDGPUDisassembler::isVI() const { diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -737,9 +737,10 @@ O << formatDec(Op.getImm()); break; case MCOI::OPERAND_REGISTER: - // FIXME: This should be removed and handled somewhere else. Seems to come - // from a disassembler bug. - O << "/*invalid immediate*/"; + // Disassembler does not fail when operand should not allow immediate + // operands but decodes them into 32bit immediate operand. + printImmediate32(Op.getImm(), STI, O); + O << "/*Invalid immediate*/"; break; default: // We hit this for the immediate instruction bits that don't yet have a diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1707,7 +1707,7 @@ bit isFP = isFloatType.ret; RegisterOperand ret = !if(!eq(VT.Size, 128), - VSrc_128, + VRegSrc_128, !if(!eq(VT.Size, 64), !if(isFP, !if(!eq(VT.Value, v2f32.Value), @@ -2435,7 +2435,7 @@ field RegisterClass Src1DPP = getVregSrcForVT.ret; field RegisterClass Src2DPP = getVregSrcForVT.ret; field RegisterOperand Src0VOP3DPP = VGPRSrc_32; - field RegisterOperand Src1VOP3DPP = VGPRSrc_32; + field RegisterOperand Src1VOP3DPP = VRegSrc_32; field RegisterOperand Src2VOP3DPP = getVOP3DPPSrcForVT.ret; field RegisterOperand Src0SDWA = getSDWASrcForVT.ret; field RegisterOperand Src1SDWA = getSDWASrcForVT.ret; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -1066,185 +1066,123 @@ let RenderMethod = "addRegOrImmOperands"; } -// For VOP1,2,C True16 instructions. Uses first 128 32-bit VGPRs only -multiclass SIRegOperand16 { - let OperandNamespace = "AMDGPU" in { - def _b16_Lo128 : RegisterOperand(rc#rc_suffix#"_Lo128")> { - let OperandType = opType#"_INT16"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_VSrc16"; - } - - def _f16_Lo128 : RegisterOperand(rc#rc_suffix#"_Lo128")> { - let OperandType = opType#"_FP16"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # "_16"; - } - } -} - - -multiclass SIRegOperand32 { - let OperandNamespace = "AMDGPU" in { - def _b16 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_INT16"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_VSrc16"; - } - - def _f16 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_FP16"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # "_16"; - } - - def _b32 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_INT32"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # rc_suffix; - } - - def _f32 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_FP32"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # rc_suffix; - } - - def _v2b16 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_V2INT16"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_VSrcV216"; - } - - def _v2f16 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_V2FP16"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_VSrcV216"; - } - } -} - -multiclass SIRegOperand64 { - let OperandNamespace = "AMDGPU" in { - def _b64 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_INT64"; - let ParserMatchClass = RegImmMatcher; - } - - def _f64 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_FP64"; - let ParserMatchClass = RegImmMatcher; - } - - if Vectors then - def _v2f32 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_V2FP32"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_VSrcV232"; - } - if Vectors then - def _v2b32 : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_V2INT32"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_VSrcV232"; - } - } -} - -multiclass SIRegOperand : - SIRegOperand32, - SIRegOperand64; - -// FIXME: 64-bit sources can sometimes use 32-bit constants. -multiclass RegImmOperand - : SIRegOperand; - -multiclass RegInlineOperand - : SIRegOperand; - -multiclass RegInlineOperand32 - : SIRegOperand32; - -multiclass RegInlineOperand64 - : SIRegOperand64; - -multiclass RegInlineOperandAC - : SIRegOperand32; - -multiclass RegInlineOperandAC64 - : SIRegOperand64; - +class RegOrImmOperand + : RegisterOperand(RegisterClassName)> { + let OperandNamespace = "AMDGPU"; + let OperandType = OperandTypeName; + let ParserMatchClass = RegImmMatcher; + let DecoderMethod = "decodeOperand_" # RegisterClassName # decoderImmSize; + } + + class RegOrB16 + : RegOrImmOperand ; + + class RegOrF16 + : RegOrImmOperand ; + + class RegOrB32 + : RegOrImmOperand ; + + class RegOrF32 + : RegOrImmOperand ; + + class RegOrV2B16 + : RegOrImmOperand ; + + class RegOrV2F16 + : RegOrImmOperand ; + + class RegOrF64 + : RegOrImmOperand ; + + class RegOrB64 + : RegOrImmOperand ; + + class RegOrV2F32 + : RegOrImmOperand ; + + class RegOrV2B32 + : RegOrImmOperand ; + + // For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only. + class RegOrB16_Lo128 + : RegOrImmOperand ; + + class RegOrF16_Lo128 + : RegOrImmOperand ; + + // Deferred operands + class RegOrF16_Deferred + : RegOrImmOperand ; + + class RegOrF32_Deferred + : RegOrImmOperand ; + + class RegOrF16_Lo128_Deferred + : RegOrImmOperand ; //===----------------------------------------------------------------------===// // SSrc_* Operands with an SGPR or a 32-bit immediate //===----------------------------------------------------------------------===// -defm SSrc : RegImmOperand<"SReg", "SSrc">; +def SSrc_b32 : RegOrB32 <"SReg_32", "OPERAND_REG_IMM">; +def SSrc_f32 : RegOrF32 <"SReg_32", "OPERAND_REG_IMM">; +def SSrc_b64 : RegOrB64 <"SReg_64", "OPERAND_REG_IMM">; -def SSrcOrLds_b32 : RegisterOperand { - let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_REG_IMM_INT32"; - let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">; -} +def SSrcOrLds_b32 : RegOrB32 <"SRegOrLds_32", "OPERAND_REG_IMM">; //===----------------------------------------------------------------------===// // SCSrc_* Operands with an SGPR or a inline constant //===----------------------------------------------------------------------===// -defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ; +def SCSrc_b32 : RegOrB32 <"SReg_32", "OPERAND_REG_INLINE_C">; +def SCSrc_b64 : RegOrB64 <"SReg_64", "OPERAND_REG_INLINE_C">; //===----------------------------------------------------------------------===// // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate //===----------------------------------------------------------------------===// -defm VSrc : RegImmOperand<"VS", "VSrc">; -defm VSrcT : SIRegOperand16<"VS", "VSrcT", "OPERAND_REG_IMM">; +def VSrc_b16 : RegOrB16 <"VS_32", "OPERAND_REG_IMM">; +def VSrc_f16 : RegOrF16 <"VS_32", "OPERAND_REG_IMM">; +def VSrc_b32 : RegOrB32 <"VS_32", "OPERAND_REG_IMM">; +def VSrc_f32 : RegOrF32 <"VS_32", "OPERAND_REG_IMM">; +def VSrc_v2b16 : RegOrV2B16 <"VS_32", "OPERAND_REG_IMM">; +def VSrc_v2f16 : RegOrV2F16 <"VS_32", "OPERAND_REG_IMM">; +def VSrc_b64 : RegOrB64 <"VS_64", "OPERAND_REG_IMM">; +def VSrc_f64 : RegOrF64 <"VS_64", "OPERAND_REG_IMM">; +def VSrc_v2b32 : RegOrV2B32 <"VS_64", "OPERAND_REG_IMM">; +def VSrc_v2f32 : RegOrV2F32 <"VS_64", "OPERAND_REG_IMM">; -def VSrc_128 : RegisterOperand { - let DecoderMethod = "DecodeVS_128RegisterClass"; -} +def VSrcT_b16_Lo128 : RegOrB16_Lo128 <"VS_32_Lo128", "OPERAND_REG_IMM">; +def VSrcT_f16_Lo128 : RegOrF16_Lo128 <"VS_32_Lo128", "OPERAND_REG_IMM">; //===----------------------------------------------------------------------===// // VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use // with FMAMK/FMAAK //===----------------------------------------------------------------------===// -multiclass SIRegOperand16_Deferred { - let OperandNamespace = "AMDGPU" in { - def _f16_Lo128_Deferred : RegisterOperand(rc#rc_suffix#"_Lo128")> { - let OperandType = opType#"_FP16_DEFERRED"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # "_16_Deferred"; - } - } -} - -multiclass SIRegOperand32_Deferred { - let OperandNamespace = "AMDGPU" in { - def _f16_Deferred : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_FP16_DEFERRED"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # "_16_Deferred"; - } - - def _f32_Deferred : RegisterOperand(rc#rc_suffix)> { - let OperandType = opType#"_FP32_DEFERRED"; - let ParserMatchClass = RegImmMatcher; - let DecoderMethod = "decodeOperand_" # rc # "_32_Deferred"; - } - } -} +def VSrc_f16_Deferred : RegOrF16_Deferred<"VS_32", "OPERAND_REG_IMM">; +def VSrc_f32_Deferred : RegOrF32_Deferred<"VS_32", "OPERAND_REG_IMM">; -defm VSrc : SIRegOperand32_Deferred<"VS", "VSrc", "OPERAND_REG_IMM">; -defm VSrcT : SIRegOperand16_Deferred<"VS", "VSrcT", "OPERAND_REG_IMM">; +def VSrcT_f16_Lo128_Deferred : RegOrF16_Lo128_Deferred<"VS_32_Lo128", + "OPERAND_REG_IMM">; //===----------------------------------------------------------------------===// // VRegSrc_* Operands with a VGPR @@ -1253,8 +1191,7 @@ // This is for operands with the enum(9), VSrc encoding restriction, // but only allows VGPRs. def VRegSrc_32 : RegisterOperand { - //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; - let DecoderMethod = "DecodeVS_32RegisterClass"; + let DecoderMethod = "decodeOperand_VGPR_32"; } def VRegSrc_64 : RegisterOperand { @@ -1269,6 +1206,10 @@ let DecoderMethod = "decodeOperand_VReg_256"; } +def VRegOrLdsSrc_32 : RegisterOperand { + let DecoderMethod = "decodeOperand_VRegOrLds_32"; +} + //===----------------------------------------------------------------------===// // VGPRSrc_* //===----------------------------------------------------------------------===// @@ -1286,7 +1227,7 @@ //===----------------------------------------------------------------------===// def ARegSrc_32 : RegisterOperand { - let DecoderMethod = "DecodeAGPR_32RegisterClass"; + let DecoderMethod = "decodeOperand_AGPR_32"; let EncoderMethod = "getAVOperandEncoding"; } @@ -1294,38 +1235,42 @@ // VCSrc_* Operands with an SGPR, VGPR or an inline constant //===----------------------------------------------------------------------===// -defm VCSrc : RegInlineOperand<"VS", "VCSrc">; -defm VCSrcT : SIRegOperand16<"VS", "VCSrcT", "OPERAND_REG_INLINE_C">; +def VCSrc_b16 : RegOrB16 <"VS_32", "OPERAND_REG_INLINE_C">; +def VCSrc_f16 : RegOrF16 <"VS_32", "OPERAND_REG_INLINE_C">; +def VCSrc_b32 : RegOrB32 <"VS_32", "OPERAND_REG_INLINE_C">; +def VCSrc_f32 : RegOrF32 <"VS_32", "OPERAND_REG_INLINE_C">; +def VCSrc_v2b16 : RegOrV2B16 <"VS_32", "OPERAND_REG_INLINE_C">; +def VCSrc_v2f16 : RegOrV2F16 <"VS_32", "OPERAND_REG_INLINE_C">; //===----------------------------------------------------------------------===// // VISrc_* Operands with a VGPR or an inline constant //===----------------------------------------------------------------------===// -defm VISrc : RegInlineOperand32<"VGPR", "VISrc">; -let DecoderMethod = "decodeOperand_VReg_64" in -defm VISrc_64 : RegInlineOperand64<"VReg", "VISrc_64", "_64">; -defm VISrc_128 : RegInlineOperandAC<"VReg", "VISrc_128", "_128">; -let DecoderMethod = "decodeOperand_VReg_256" in -defm VISrc_256 : RegInlineOperand64<"VReg", "VISrc_256", "_256">; -defm VISrc_512 : RegInlineOperandAC<"VReg", "VISrc_512", "_512">; -defm VISrc_1024 : RegInlineOperandAC<"VReg", "VISrc_1024", "_1024">; +def VISrc_64_f64 : RegOrF64 <"VReg_64", "OPERAND_REG_INLINE_C">; +def VISrc_128_b32 : RegOrB32 <"VReg_128", "OPERAND_REG_INLINE_C">; +def VISrc_128_f32 : RegOrF32 <"VReg_128", "OPERAND_REG_INLINE_C">; +def VISrc_256_f64 : RegOrF64 <"VReg_256", "OPERAND_REG_INLINE_C">; +def VISrc_512_b32 : RegOrB32 <"VReg_512", "OPERAND_REG_INLINE_C">; +def VISrc_512_f32 : RegOrF32 <"VReg_512", "OPERAND_REG_INLINE_C">; +def VISrc_1024_b32 : RegOrB32 <"VReg_1024", "OPERAND_REG_INLINE_C">; +def VISrc_1024_f32 : RegOrF32 <"VReg_1024", "OPERAND_REG_INLINE_C">; //===----------------------------------------------------------------------===// // AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR //===----------------------------------------------------------------------===// def AVSrc_32 : RegisterOperand { - let DecoderMethod = "DecodeAV_32RegisterClass"; + let DecoderMethod = "decodeOperand_AV_32"; let EncoderMethod = "getAVOperandEncoding"; } def AVSrc_64 : RegisterOperand { - let DecoderMethod = "DecodeAV_64RegisterClass"; + let DecoderMethod = "decodeOperand_AV_64"; let EncoderMethod = "getAVOperandEncoding"; } def AVSrc_128 : RegisterOperand { - let DecoderMethod = "DecodeAV_128RegisterClass"; + let DecoderMethod = "decodeOperand_AV_128"; let EncoderMethod = "getAVOperandEncoding"; } @@ -1368,12 +1313,11 @@ // ACSrc_* Operands with an AGPR or an inline constant //===----------------------------------------------------------------------===// -defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; -defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; -defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; -defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; - -let DecoderMethod = "decodeOperand_AReg_64" in -defm AISrc_64 : RegInlineOperandAC64<"AReg", "AISrc_64", "_64">; -let DecoderMethod = "decodeOperand_AReg_256" in -defm AISrc_256 : RegInlineOperandAC64<"AReg", "AISrc_256", "_256">; +def AISrc_64_f64 : RegOrF64 <"AReg_64", "OPERAND_REG_INLINE_AC">; +def AISrc_128_f32 : RegOrF32 <"AReg_128", "OPERAND_REG_INLINE_AC">; +def AISrc_128_b32 : RegOrB32 <"AReg_128", "OPERAND_REG_INLINE_AC">; +def AISrc_256_f64 : RegOrF64 <"AReg_256", "OPERAND_REG_INLINE_AC">; +def AISrc_512_f32 : RegOrF32 <"AReg_512", "OPERAND_REG_INLINE_AC">; +def AISrc_512_b32 : RegOrB32 <"AReg_512", "OPERAND_REG_INLINE_AC">; +def AISrc_1024_f32 : RegOrF32 <"AReg_1024", "OPERAND_REG_INLINE_AC">; +def AISrc_1024_b32 : RegOrB32 <"AReg_1024", "OPERAND_REG_INLINE_AC">; diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -229,9 +229,9 @@ // TODO: Make profile for this, there is VOP3 encoding also def V_READFIRSTLANE_B32 : InstSI <(outs SReg_32:$vdst), - (ins VRegOrLds_32:$src0), + (ins VRegOrLdsSrc_32:$src0), "v_readfirstlane_b32 $vdst, $src0", - [(set i32:$vdst, (int_amdgcn_readfirstlane (i32 VRegOrLds_32:$src0)))]>, + [(set i32:$vdst, (int_amdgcn_readfirstlane (i32 VRegOrLdsSrc_32:$src0)))]>, Enc32 { let isCodeGenOnly = 0; @@ -529,8 +529,8 @@ } def VOP_SWAP_I32 : VOPProfile<[i32, i32, i32, untyped]> { - let Outs32 = (outs VGPR_32:$vdst, VGPR_32:$vdst1); - let Ins32 = (ins VGPR_32:$src0, VGPR_32:$src1); + let Outs32 = (outs VGPR_32:$vdst, VRegSrc_32:$vdst1); + let Ins32 = (ins VRegSrc_32:$src0, VGPR_32:$src1); let Outs64 = Outs32; let Asm32 = " $vdst, $src0"; let Asm64 = ""; @@ -633,7 +633,7 @@ def VOPProfileAccMov : VOP_NO_EXT { let DstRC = RegisterOperand; - let Src0RC32 = RegisterOperand; + let Src0RC32 = ARegSrc_32; let Asm32 = " $vdst, $src0"; } diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -660,7 +660,7 @@ def VOP_READLANE : VOPProfile<[i32, i32, i32, untyped]> { let Outs32 = (outs SReg_32:$vdst); let Outs64 = Outs32; - let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1); + let Ins32 = (ins VRegOrLdsSrc_32:$src0, SCSrc_b32:$src1); let Ins64 = Ins32; let Asm32 = " $vdst, $src0, $src1"; let Asm64 = Asm32; diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -35,7 +35,7 @@ FP16InputMods:$src2_modifiers, VCSrc_f16:$src2); dag dpp_srcs = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, - FPVRegInputMods:$src1_modifiers, VGPRSrc_32:$src1, + FPVRegInputMods:$src1_modifiers, VRegSrc_32:$src1, FP16InputMods:$src2_modifiers, VCSrc_f16:$src2); // FIXME: clampmod0 misbehaves with the non-default vdst_in diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td --- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -770,7 +770,7 @@ // DPP8 forbids modifiers and can inherit from VOPC_Profile let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); - dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1); + dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VRegSrc_32:$src1); let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel), (ins))); let AsmVOP3Base = "$sdst, $src0_modifiers, $src1"; diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt --- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt @@ -17,8 +17,8 @@ # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c] 0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c -# W32: v_wmma_f32_16x16x16_f16 v[16:23], /*invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] -# W64: v_wmma_f32_16x16x16_f16 v[16:19], /*invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] +# W32: v_wmma_f32_16x16x16_f16 v[16:23], 1.0/*Invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] +# W64: v_wmma_f32_16x16x16_f16 v[16:19], 1.0/*Invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] 0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0 # W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]