diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -430,9 +430,9 @@ // RUN: %clang --target=riscv32-unknown-elf -march=rv32izca0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s // RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izca0p1' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zca' (this compiler supports 0.70) +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zca' (this compiler supports 1.0) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca0p70 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s // RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zca" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -466,25 +466,25 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s // CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}} -// RUN: %clang -target riscv32 -march=rv32izca0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv32 -march=rv32izca1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s -// RUN: %clang -target riscv64 -march=rv64izca0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv64 -march=rv64izca1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s -// CHECK-ZCA-EXT: __riscv_zca 70000{{$}} +// CHECK-ZCA-EXT: __riscv_zca 1000000{{$}} -// RUN: %clang -target riscv32 -march=rv32izcb0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv32 -march=rv32izcb1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s -// RUN: %clang -target riscv64 -march=rv64izcb0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv64 -march=rv64izcb1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s -// CHECK-ZCB-EXT: __riscv_zca 70000{{$}} -// CHECK-ZCB-EXT: __riscv_zcb 70000{{$}} +// CHECK-ZCB-EXT: __riscv_zca 1000000{{$}} +// CHECK-ZCB-EXT: __riscv_zcb 1000000{{$}} -// RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv32 -march=rv32izcd1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s -// RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv64 -march=rv64izcd1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s -// CHECK-ZCD-EXT: __riscv_zcd 70000{{$}} +// CHECK-ZCD-EXT: __riscv_zcd 1000000{{$}} -// RUN: %clang -target riscv32 -march=rv32izcf0p70 -menable-experimental-extensions \ +// RUN: %clang -target riscv32 -march=rv32izcf1p0 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s -// CHECK-ZCF-EXT: __riscv_zcf 70000{{$}} +// CHECK-ZCF-EXT: __riscv_zcf 1000000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -136,13 +136,13 @@ LLVM implements the `1.0-rc3 draft specification `_. Note that have been backwards incompatible changes made between release candidates for the 1.0 draft. ``experimental-zca`` - LLVM implements the `0.70 draft specification `_. + LLVM implements the `1.0.1 draft specification `_. ``experimental-zcd`` - LLVM implements the `0.70 draft specification `_. + LLVM implements the `1.0.1 draft specification `_. ``experimental-zcf`` - LLVM implements the `0.70 draft specification `_. + LLVM implements the `1.0.1 draft specification `_. ``experimental-zcb`` LLVM implements the `0.70 draft specification `_. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -100,7 +100,8 @@ Changes to the RISC-V Backend ----------------------------- -* Assembler support for the Zcb extension was added. +* Assembler support for version 1.0.1 of the Zcb extension was added. +* Zca, Zcf, and Zcd extensions were upgraded to version 1.0.1. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -114,10 +114,10 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zihintntl", RISCVExtensionVersion{0, 2}}, - {"zca", RISCVExtensionVersion{0, 70}}, - {"zcb", RISCVExtensionVersion{0, 70}}, - {"zcd", RISCVExtensionVersion{0, 70}}, - {"zcf", RISCVExtensionVersion{0, 70}}, + {"zca", RISCVExtensionVersion{1, 0}}, + {"zcb", RISCVExtensionVersion{1, 0}}, + {"zcd", RISCVExtensionVersion{1, 0}}, + {"zcf", RISCVExtensionVersion{1, 0}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"zawrs", RISCVExtensionVersion{1, 0}}, {"ztso", RISCVExtensionVersion{0, 1}}, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// /// This file describes the RISC-V instructions from the 'Zc*' compressed -/// instruction extensions, version 0.70.4. +/// instruction extensions, version 1.0.1. /// This version is still experimental as the 'Zc*' extensions haven't been /// ratified yet. /// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -42,6 +42,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV32ZCB %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefix=RV32ZCD %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefix=RV32ZCF %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s @@ -89,6 +91,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV64ZCB %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefix=RV64ZCD %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0" @@ -130,8 +133,10 @@ ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0" -; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70" -; RV32ZCB: .attribute 5, "rv32i2p0_zca0p70_zcb0p70" +; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0" +; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0" +; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0" +; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" @@ -177,8 +182,9 @@ ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0" ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1" -; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70" -; RV64ZCB: .attribute 5, "rv64i2p0_zca0p70_zcb0p70" +; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0" +; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0" +; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -176,11 +176,17 @@ .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0" # CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0" -.attribute arch, "rv32izca0p70" -# CHECK: attribute 5, "rv32i2p0_zca0p70" +.attribute arch, "rv32izca1p0" +# CHECK: attribute 5, "rv32i2p0_zca1p0" -.attribute arch, "rv32izcb0p70" -# CHECK: attribute 5, "rv32i2p0_zca0p70_zcb0p70" +.attribute arch, "rv32izcd1p0" +# CHECK: attribute 5, "rv32i2p0_zcd1p0" + +.attribute arch, "rv32izcf1p0" +# CHECK: attribute 5, "rv32i2p0_zcf1p0" + +.attribute arch, "rv32izcb1p0" +# CHECK: attribute 5, "rv32i2p0_zca1p0_zcb1p0" .attribute arch, "rv32izawrs1p0" # CHECK: attribute 5, "rv32i2p0_zawrs1p0"